43 		dd_dev_err(dd, "pci enable failed: error %d\n", -ret);  in hfi1_pcie_init()
49 		dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret);  in hfi1_pcie_init()
62 			dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret);  in hfi1_pcie_init()
111 		dd_dev_err(dd, "chip PIO range does not match\n");  in hfi1_pcie_ddinit()
117 		dd_dev_err(dd, "UC mapping of kregbase1 failed\n");  in hfi1_pcie_ddinit()
125 		dd_dev_err(dd, "Cannot read chip CSRs\n");  in hfi1_pcie_ddinit()
137 		dd_dev_err(dd, "UC mapping of kregbase2 failed\n");  in hfi1_pcie_ddinit()
145 		dd_dev_err(dd, "WC mapping of send buffers failed\n");  in hfi1_pcie_ddinit()
159 		dd_dev_err(dd, "WC mapping of receive array failed\n");  in hfi1_pcie_ddinit()
229 		dd_dev_err(dd, "Unable to read from PCI config\n");  in update_lbus_info()
250 		dd_dev_err(dd, "Can't find PCI Express capability!\n");  in pcie_speeds()
259 		dd_dev_err(dd, "Unable to read from PCI config\n");  in pcie_speeds()
343 	dd_dev_err(dd, "Unable to write to PCI config\n");  in restore_pci_variables()
402 	dd_dev_err(dd, "Unable to read from PCI config\n");  in save_pci_variables()
748 			dd_dev_err(dd, "Unable to read from PCI config\n");  in load_eq_table()
756 				dd_dev_err(dd,  in load_eq_table()
758 				dd_dev_err(dd, "         prec   attn   post\n");  in load_eq_table()
760 			dd_dev_err(dd, "   p%02d:   %02x     %02x     %02x\n",  in load_eq_table()
763 			dd_dev_err(dd, "            %02x     %02x     %02x\n",  in load_eq_table()
811 		dd_dev_err(dd, "%s: no parent device\n", __func__);  in trigger_sbr()
818 			dd_dev_err(dd,  in trigger_sbr()
1013 		dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");  in do_pcie_gen3_transition()
1021 		dd_dev_err(dd, "%s: unable to acquire SBus resource\n",  in do_pcie_gen3_transition()
1128 		dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",  in do_pcie_gen3_transition()
1208 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1224 			dd_dev_err(dd, "Unable to write to PCI config\n");  in do_pcie_gen3_transition()
1235 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1248 		dd_dev_err(dd, "Unable to write to PCI config\n");  in do_pcie_gen3_transition()
1303 		dd_dev_err(dd, "%s: Could not restore PCI variables\n",  in do_pcie_gen3_transition()
1325 		dd_dev_err(dd, "SBR failed - unable to read from device\n");  in do_pcie_gen3_transition()
1340 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1351 		dd_dev_err(dd,  in do_pcie_gen3_transition()
1362 		dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);  in do_pcie_gen3_transition()
1376 		dd_dev_err(dd, "PCIe link speed or width did not match target%s\n",  in do_pcie_gen3_transition()
1397 		dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");  in do_pcie_gen3_transition()