Lines Matching +full:reset +full:- +full:post +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
8 #include <linux/delay.h>
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
33 * We did a chip reset, and then failed to reprogram the in hfi1_pcie_init()
34 * BAR, or the chip reset due to an internal error. We then in hfi1_pcie_init()
37 * Both reset cases set the BAR back to initial state. For in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
91 * fields required to re-initialize after a chip reset, or for
112 return -EINVAL; in hfi1_pcie_ddinit()
115 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
116 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
118 return -ENOMEM; in hfi1_pcie_ddinit()
120 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
122 /* verify that reads actually work, save revision for reset check */ in hfi1_pcie_ddinit()
123 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
124 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
129 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
131 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
133 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
134 addr + dd->base2_start, in hfi1_pcie_ddinit()
135 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
136 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
140 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
141 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
143 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
144 if (!dd->piobase) { in hfi1_pcie_ddinit()
148 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
150 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
153 * Map the chip's RcvArray as write-combining to allow us in hfi1_pcie_ddinit()
156 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
158 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
163 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
165 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
168 ret = -ENOMEM; in hfi1_pcie_ddinit()
174 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
180 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
181 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
182 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
183 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
184 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
185 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
186 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
187 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
188 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
189 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
190 if (dd->piobase) in hfi1_pcie_ddcleanup()
191 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
192 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
221 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
227 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
233 dd->lbus_width = extract_width(linkstat); in update_lbus_info()
234 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
235 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
236 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
246 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
249 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
251 return -EINVAL; in pcie_speeds()
255 dd->link_gen3_capable = 1; in pcie_speeds()
257 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
267 dd->link_gen3_capable = 0; in pcie_speeds()
271 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed in pcie_speeds()
274 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
275 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
277 dd->link_gen3_capable = 0; in pcie_speeds()
283 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
289 * Restore command and BARs after a reset has wiped them out
297 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
301 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
302 dd->pcibar0); in restore_pci_variables()
306 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
307 dd->pcibar1); in restore_pci_variables()
311 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
315 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
316 dd->pcie_devctl); in restore_pci_variables()
320 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
321 dd->pcie_lnkctl); in restore_pci_variables()
325 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
326 dd->pcie_devctl2); in restore_pci_variables()
330 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
334 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
335 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
336 dd->pci_tph2); in restore_pci_variables()
348 * Save BARs and command to rewrite after device reset
356 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
357 &dd->pcibar0); in save_pci_variables()
361 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
362 &dd->pcibar1); in save_pci_variables()
366 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
370 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
374 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
375 &dd->pcie_devctl); in save_pci_variables()
379 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
380 &dd->pcie_lnkctl); in save_pci_variables()
384 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
385 &dd->pcie_devctl2); in save_pci_variables()
389 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
393 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
394 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
395 &dd->pci_tph2); in save_pci_variables()
407 * BIOS may not set PCIe bus-utilization parameters for best performance.
415 * tune_pcie_caps() - Code to adjust PCIe capabilities.
430 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
434 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
440 parent = dd->pcidev->bus->self; in tune_pcie_caps()
449 if (!pci_is_root_bus(parent->bus)) { in tune_pcie_caps()
457 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
461 rc_mpss = parent->pcie_mpss; in tune_pcie_caps()
462 rc_mps = ffs(pcie_get_mps(parent)) - 8; in tune_pcie_caps()
463 /* Find out supported and configured values for endpoint (us) */ in tune_pcie_caps()
464 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
465 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
482 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
488 * which is code '5' (log2(4096) - 7) in tune_pcie_caps()
496 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
504 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
526 dd_dev_info(dd, "State Frozen, requesting reset\n"); in pci_error_detected()
535 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
557 if (dd && dd->pport) { in pci_mmio_enabled()
558 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
585 * unlike sysfs-requested reset. Better than in pci_resume()
588 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
621 /* gasket block secondary bus reset delay */
626 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
641 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
645 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/…
650 #define POST 2 macro
654 /* prec attn post */
670 /* prec attn post */
715 #define eq_value(pre, curr, post) \ argument
719 | (((u32)(post)) << \
728 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
740 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); in load_eq_table()
741 c_plus1 = eq[i][POST] / div; in load_eq_table()
745 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
758 dd_dev_err(dd, " prec attn post\n"); in load_eq_table()
769 return -EINVAL; in load_eq_table()
791 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
799 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
806 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
810 if (!dev->bus->self) { in trigger_sbr()
812 return -ENOTTY; in trigger_sbr()
816 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in trigger_sbr()
821 return -ENOTTY; in trigger_sbr()
829 return pci_bridge_secondary_bus_reset(dev->bus->self); in trigger_sbr()
844 * Tell the gasket logic how to react to the reset.
850 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
852 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
879 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
892 * For Discrete, use full-swing. in write_xmt_margin()
893 * - PCIe TX defaults to full-swing. in write_xmt_margin()
895 * For Integrated, use half-swing in write_xmt_margin()
896 * - Copy xmt_margin and xmt_margin_oe in write_xmt_margin()
899 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
920 lane_delay = 0xF; /* Delay 240ns. */ in write_xmt_margin()
944 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
964 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
977 /* off or invalid target - skip */ in do_pcie_gen3_transition()
983 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
986 pcie_force ? "re-doing anyway" : "skipping"); in do_pcie_gen3_transition()
1002 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1012 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1014 ret = -ENOSYS; in do_pcie_gen3_transition()
1036 /* the SBus download will reset the spico for thermal */ in do_pcie_gen3_transition()
1052 * PcieCfgSpcie1 - Link Control 3 in do_pcie_gen3_transition()
1053 * Leave at reset value. No need to set PerfEq - link equalization in do_pcie_gen3_transition()
1058 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ in do_pcie_gen3_transition()
1059 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1064 * PcieCfgRegPl2 - Port Force Link in do_pcie_gen3_transition()
1070 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1073 * PcieCfgRegPl100 - Gen3 Control in do_pcie_gen3_transition()
1080 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1083 * PcieCfgRegPl101 - Gen3 EQ FS and LF in do_pcie_gen3_transition()
1084 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping in do_pcie_gen3_transition()
1085 * PcieCfgRegPl103 - Gen3 EQ Preset Index in do_pcie_gen3_transition()
1086 * PcieCfgRegPl105 - Gen3 EQ Status in do_pcie_gen3_transition()
1090 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1098 /* bit 0 - discrete on/off */ in do_pcie_gen3_transition()
1108 /* bit 1 - integrated on/off */ in do_pcie_gen3_transition()
1111 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1121 * PcieCfgRegPl106 - Gen3 EQ Control in do_pcie_gen3_transition()
1127 if (pset > 10) { /* valid range is 0-10, inclusive */ in do_pcie_gen3_transition()
1133 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1140 * step 5b: Do post firmware download steps via SBus in do_pcie_gen3_transition()
1142 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); in do_pcie_gen3_transition()
1233 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); in do_pcie_gen3_transition()
1246 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); in do_pcie_gen3_transition()
1254 /* hold DC in reset across the SBR */ in do_pcie_gen3_transition()
1256 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1265 * The chip has already been reset, so there will be no traffic in do_pcie_gen3_transition()
1268 * do it while we are doing the reset. in do_pcie_gen3_transition()
1272 * step 7: initiate the secondary bus reset (SBR) in do_pcie_gen3_transition()
1284 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1295 ret = -EIO; in do_pcie_gen3_transition()
1299 /* restore PCI space registers we know were reset */ in do_pcie_gen3_transition()
1318 * Once we're sure we can read and write, clear the DC reset after in do_pcie_gen3_transition()
1319 * the SBR. Then check for any per-lane errors. Then look over in do_pcie_gen3_transition()
1325 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1327 ret = -ENOSYS; in do_pcie_gen3_transition()
1331 /* clear the DC reset */ in do_pcie_gen3_transition()
1337 /* check for any per-lane errors */ in do_pcie_gen3_transition()
1338 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1345 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1350 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1353 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1354 ret = -EIO; in do_pcie_gen3_transition()
1363 ret = -EIO; in do_pcie_gen3_transition()
1370 dd->lbus_info); in do_pcie_gen3_transition()
1372 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1373 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1383 ret = -EIO; in do_pcie_gen3_transition()
1390 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()