121 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,  in xadc_write_reg()  argument
124 	writel(val, xadc->base + reg);  in xadc_write_reg()
127 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,  in xadc_read_reg()  argument
130 	*val = readl(xadc->base + reg);  in xadc_read_reg()
143 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,  in xadc_zynq_write_fifo()  argument
149 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);  in xadc_zynq_write_fifo()
152 static void xadc_zynq_drain_fifo(struct xadc *xadc)  in xadc_zynq_drain_fifo()  argument
156 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
159 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_drain_fifo()
160 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
164 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,  in xadc_zynq_update_intmsk()  argument
167 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
168 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
170 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,  in xadc_zynq_update_intmsk()
171 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
174 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_write_adc_reg()  argument
181 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
182 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_write_adc_reg()
185 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
188 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_write_adc_reg()
189 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_write_adc_reg()
192 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_write_adc_reg()
194 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_write_adc_reg()
195 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
197 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
203 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_write_adc_reg()
208 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_read_adc_reg()  argument
218 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
219 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_read_adc_reg()
221 	xadc_zynq_drain_fifo(xadc);  in xadc_zynq_read_adc_reg()
222 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
224 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_read_adc_reg()
225 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_read_adc_reg()
228 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_read_adc_reg()
230 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_read_adc_reg()
231 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
232 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
238 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
239 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
263 	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);  in xadc_zynq_unmask_worker()  local
266 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);  in xadc_zynq_unmask_worker()
270 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
273 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
274 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
277 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
280 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);  in xadc_zynq_unmask_worker()
282 	xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_unmask_worker()
284 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
287 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
288 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
297 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_interrupt_handler()  local
300 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_interrupt_handler()
302 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
307 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
309 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);  in xadc_zynq_interrupt_handler()
312 		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_interrupt_handler()
314 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
319 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
324 		xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_interrupt_handler()
330 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
333 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
345 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_setup()  local
357 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
359 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
364 		ret = clk_set_rate(xadc->clk,  in xadc_zynq_setup()
387 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);  in xadc_zynq_setup()
388 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);  in xadc_zynq_setup()
389 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);  in xadc_zynq_setup()
390 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
391 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |  in xadc_zynq_setup()
396 		ret = clk_set_rate(xadc->clk, pcap_rate);  in xadc_zynq_setup()
404 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)  in xadc_zynq_get_dclk_rate()  argument
409 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);  in xadc_zynq_get_dclk_rate()
426 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
429 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_zynq_update_alarm()  argument
437 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
440 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_update_alarm()
441 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);  in xadc_zynq_update_alarm()
443 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,  in xadc_zynq_update_alarm()
446 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
464 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_read_adc_reg()  argument
469 	xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_read_adc_reg()
476 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_write_adc_reg()  argument
479 	xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,  in xadc_axi_write_adc_reg()
488 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_setup()  local
490 	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);  in xadc_axi_setup()
491 	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);  in xadc_axi_setup()
499 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_interrupt_handler()  local
503 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);  in xadc_axi_interrupt_handler()
504 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);  in xadc_axi_interrupt_handler()
510 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
511 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
526 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);  in xadc_axi_interrupt_handler()
531 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_axi_update_alarm()  argument
545 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
546 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_axi_update_alarm()
549 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_axi_update_alarm()
550 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
553 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)  in xadc_axi_get_dclk()  argument
555 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
580 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in _xadc_update_adc_reg()  argument
586 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);  in _xadc_update_adc_reg()
590 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);  in _xadc_update_adc_reg()
593 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_update_adc_reg()  argument
598 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
599 	ret = _xadc_update_adc_reg(xadc, reg, mask, val);  in xadc_update_adc_reg()
600 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
605 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)  in xadc_get_dclk_rate()  argument
607 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
613 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_update_scan_mode()  local
619 	if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))  in xadc_update_scan_mode()
622 	data = devm_krealloc(indio_dev->dev.parent, xadc->data,  in xadc_update_scan_mode()
628 	xadc->data = data;  in xadc_update_scan_mode()
665 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_trigger_handler()  local
669 	if (!xadc->data)  in xadc_trigger_handler()
676 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
680 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
690 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);  in xadc_trigger_set_state()  local
696 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
700 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
704 			xadc->trigger = trigger;  in xadc_trigger_set_state()
705 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
710 		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,  in xadc_trigger_set_state()
715 		xadc->trigger = NULL;  in xadc_trigger_set_state()
718 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
719 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_trigger_set_state()
720 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);  in xadc_trigger_set_state()
725 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_trigger_set_state()
726 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
729 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
760 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)  in xadc_power_adc_b()  argument
770 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_power_adc_b()
784 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,  in xadc_power_adc_b()
788 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)  in xadc_get_seq_mode()  argument
793 	if (xadc->ops->type == XADC_TYPE_US)  in xadc_get_seq_mode()
796 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
808 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_postdisable()  local
818 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_postdisable()
822 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_postdisable()
826 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_postdisable()
831 	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);  in xadc_postdisable()
836 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_preenable()  local
841 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
847 	seq_mode = xadc_get_seq_mode(xadc, scan_mask);  in xadc_preenable()
849 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_preenable()
863 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_preenable()
867 	ret = xadc_power_adc_b(xadc, seq_mode);  in xadc_preenable()
871 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
887 static int xadc_read_samplerate(struct xadc *xadc)  in xadc_read_samplerate()  argument
893 	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);  in xadc_read_samplerate()
901 	return xadc_get_dclk_rate(xadc) / div / 26;  in xadc_read_samplerate()
907 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_read_raw()  local
916 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
961 		ret = xadc_read_samplerate(xadc);  in xadc_read_raw()
972 static int xadc_write_samplerate(struct xadc *xadc, int val)  in xadc_write_samplerate()  argument
974 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);  in xadc_write_samplerate()
1005 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,  in xadc_write_samplerate()
1012 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_write_raw()  local
1017 	return xadc_write_samplerate(xadc, val);  in xadc_write_raw()
1188 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_parse_dt()  local
1203 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1205 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1207 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1211 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1217 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1233 	if (xadc->ops->type == XADC_TYPE_S7) {  in xadc_parse_dt()
1313 	struct xadc *xadc;  in xadc_probe()  local
1329 	indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));  in xadc_probe()
1333 	xadc = iio_priv(indio_dev);  in xadc_probe()
1334 	xadc->ops = id->data;  in xadc_probe()
1335 	xadc->irq = irq;  in xadc_probe()
1336 	init_completion(&xadc->completion);  in xadc_probe()
1337 	mutex_init(&xadc->mutex);  in xadc_probe()
1338 	spin_lock_init(&xadc->lock);  in xadc_probe()
1339 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1341 	xadc->base = devm_platform_ioremap_resource(pdev, 0);  in xadc_probe()
1342 	if (IS_ERR(xadc->base))  in xadc_probe()
1343 		return PTR_ERR(xadc->base);  in xadc_probe()
1345 	indio_dev->name = xadc_type_names[xadc->ops->type];  in xadc_probe()
1353 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1361 		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1362 		if (IS_ERR(xadc->convst_trigger))  in xadc_probe()
1363 			return PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1365 		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1367 		if (IS_ERR(xadc->samplerate_trigger))  in xadc_probe()
1368 			return PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1371 	xadc->clk = devm_clk_get(dev, NULL);  in xadc_probe()
1372 	if (IS_ERR(xadc->clk))  in xadc_probe()
1373 		return PTR_ERR(xadc->clk);  in xadc_probe()
1375 	ret = clk_prepare_enable(xadc->clk);  in xadc_probe()
1380 				       xadc_clk_disable_unprepare, xadc->clk);  in xadc_probe()
1388 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1389 		ret = xadc_read_samplerate(xadc);  in xadc_probe()
1394 			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);  in xadc_probe()
1400 	ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0,  in xadc_probe()
1406 				       &xadc->zynq_unmask_work);  in xadc_probe()
1410 	ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);  in xadc_probe()
1415 		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1416 			&xadc->threshold[i]);  in xadc_probe()
1418 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);  in xadc_probe()
1428 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);  in xadc_probe()
1432 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),  in xadc_probe()
1438 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,  in xadc_probe()
1450 			xadc->threshold[i] = 0xffff;  in xadc_probe()
1452 			xadc->threshold[i] = 0;  in xadc_probe()
1453 		ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1454 			xadc->threshold[i]);  in xadc_probe()