Lines Matching +full:spi +full:- +full:rx +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments TSC2046 SPI ADC driver
9 #include <linux/delay.h>
11 #include <linux/spi/spi.h>
26 * - rate limiting:
28 * - hrtimer:
58 * conversion has 12-bit resolution, whereas with this bit high, the next
59 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
65 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
72 * auto-wake/suspend mode. In most case this bits should stay zero.
89 * Command transmitted to the controller. This field is empty on the RX
102 /* Group offset within the SPI RX buffer */
127 struct spi_device *spi; member
146 * Lock to protect the layout and the SPI transfer buffer.
148 * in this case the l[] and tx/rx buffer will be out of sync to each
153 struct tsc2046_adc_atom *rx; member
213 bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns); in tsc2046_adc_time_to_count()
216 …dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\… in tsc2046_adc_time_to_count()
217 priv->effective_speed_hz, priv->time_per_bit_ns, in tsc2046_adc_time_to_count()
242 return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data)); in tsc2046_adc_get_value()
253 priv->tx_one->cmd = tsc2046_adc_get_cmd(priv, ch_idx, false); in tsc2046_adc_read_one()
254 priv->tx_one->data = 0; in tsc2046_adc_read_one()
255 xfer.tx_buf = priv->tx_one; in tsc2046_adc_read_one()
256 xfer.rx_buf = priv->rx_one; in tsc2046_adc_read_one()
257 xfer.len = sizeof(*priv->tx_one); in tsc2046_adc_read_one()
264 ret = spi_sync(priv->spi, &msg); in tsc2046_adc_read_one()
266 dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n", in tsc2046_adc_read_one()
274 return tsc2046_adc_get_value(priv->rx_one); in tsc2046_adc_read_one()
281 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx]; in tsc2046_adc_group_set_layout()
287 offset = priv->l[group - 1].offset + priv->l[group - 1].count; in tsc2046_adc_group_set_layout()
289 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us); in tsc2046_adc_group_set_layout()
290 max_count = count_skip + ch->oversampling_ratio; in tsc2046_adc_group_set_layout()
292 cur = &priv->l[group]; in tsc2046_adc_group_set_layout()
293 cur->offset = offset; in tsc2046_adc_group_set_layout()
294 cur->count = max_count; in tsc2046_adc_group_set_layout()
295 cur->skip = count_skip; in tsc2046_adc_group_set_layout()
297 return sizeof(*priv->tx) * max_count; in tsc2046_adc_group_set_layout()
303 struct tsc2046_adc_group_layout *l = &priv->l[group]; in tsc2046_adc_group_set_cmd()
313 for (i = 0; i < l->count - 1; i++) in tsc2046_adc_group_set_cmd()
314 priv->tx[l->offset + i].cmd = cmd; in tsc2046_adc_group_set_cmd()
317 priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false); in tsc2046_adc_group_set_cmd()
326 l = &priv->l[group]; in tsc2046_adc_get_val()
327 valid_count = l->count - l->skip; in tsc2046_adc_get_val()
330 val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]); in tsc2046_adc_get_val()
340 struct device *dev = &priv->spi->dev; in tsc2046_adc_scan()
344 ret = spi_sync(priv->spi, &priv->msg); in tsc2046_adc_scan()
346 dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret)); in tsc2046_adc_scan()
350 for (group = 0; group < priv->groups; group++) in tsc2046_adc_scan()
351 priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group); in tsc2046_adc_scan()
353 ret = iio_push_to_buffers_with_timestamp(indio_dev, &priv->scan_buf, in tsc2046_adc_scan()
355 /* If the consumer is kfifo, we may get a EBUSY here - ignore it. */ in tsc2046_adc_scan()
356 if (ret < 0 && ret != -EBUSY) { in tsc2046_adc_scan()
369 struct iio_dev *indio_dev = pf->indio_dev; in tsc2046_adc_trigger_handler()
372 mutex_lock(&priv->slock); in tsc2046_adc_trigger_handler()
374 mutex_unlock(&priv->slock); in tsc2046_adc_trigger_handler()
376 iio_trigger_notify_done(indio_dev->trig); in tsc2046_adc_trigger_handler()
388 mutex_lock(&priv->slock); in tsc2046_adc_update_scan_mode()
391 for_each_set_bit(ch_idx, active_scan_mask, indio_dev->num_channels) { in tsc2046_adc_update_scan_mode()
397 priv->groups = group; in tsc2046_adc_update_scan_mode()
398 priv->xfer.len = size; in tsc2046_adc_update_scan_mode()
399 priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC; in tsc2046_adc_update_scan_mode()
401 if (priv->scan_interval_us > priv->time_per_scan_us) in tsc2046_adc_update_scan_mode()
402 dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n", in tsc2046_adc_update_scan_mode()
403 priv->scan_interval_us, priv->time_per_scan_us); in tsc2046_adc_update_scan_mode()
405 mutex_unlock(&priv->slock); in tsc2046_adc_update_scan_mode()
421 spin_lock_irqsave(&priv->trig_lock, flags); in tsc2046_adc_trig_more()
423 disable_irq_nosync(priv->spi->irq); in tsc2046_adc_trig_more()
425 priv->trig_more_count++; in tsc2046_adc_trig_more()
426 iio_trigger_poll(priv->trig); in tsc2046_adc_trig_more()
428 spin_unlock_irqrestore(&priv->trig_lock, flags); in tsc2046_adc_trig_more()
438 spin_lock(&priv->trig_lock); in tsc2046_adc_irq()
440 hrtimer_try_to_cancel(&priv->trig_timer); in tsc2046_adc_irq()
442 priv->trig_more_count = 0; in tsc2046_adc_irq()
443 disable_irq_nosync(priv->spi->irq); in tsc2046_adc_irq()
444 iio_trigger_poll(priv->trig); in tsc2046_adc_irq()
446 spin_unlock(&priv->trig_lock); in tsc2046_adc_irq()
465 delta = priv->scan_interval_us - priv->time_per_scan_us; in tsc2046_adc_reenable_trigger()
469 spin_lock_irqsave(&priv->trig_lock, flags); in tsc2046_adc_reenable_trigger()
475 if (!priv->trig_more_count) { in tsc2046_adc_reenable_trigger()
476 int timeout_ms = DIV_ROUND_UP(priv->scan_interval_us, in tsc2046_adc_reenable_trigger()
479 hrtimer_start(&priv->trig_timer, ms_to_ktime(timeout_ms), in tsc2046_adc_reenable_trigger()
483 enable_irq(priv->spi->irq); in tsc2046_adc_reenable_trigger()
485 spin_unlock_irqrestore(&priv->trig_lock, flags); in tsc2046_adc_reenable_trigger()
494 enable_irq(priv->spi->irq); in tsc2046_adc_set_trigger_state()
496 disable_irq(priv->spi->irq); in tsc2046_adc_set_trigger_state()
497 hrtimer_try_to_cancel(&priv->trig_timer); in tsc2046_adc_set_trigger_state()
514 priv->tx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->tx_one), in tsc2046_adc_setup_spi_msg()
516 if (!priv->tx_one) in tsc2046_adc_setup_spi_msg()
517 return -ENOMEM; in tsc2046_adc_setup_spi_msg()
519 priv->rx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->rx_one), in tsc2046_adc_setup_spi_msg()
521 if (!priv->rx_one) in tsc2046_adc_setup_spi_msg()
522 return -ENOMEM; in tsc2046_adc_setup_spi_msg()
525 * Make dummy read to set initial power state and get real SPI clock in tsc2046_adc_setup_spi_msg()
530 &priv->effective_speed_hz); in tsc2046_adc_setup_spi_msg()
535 * In case SPI controller do not report effective_speed_hz, use in tsc2046_adc_setup_spi_msg()
538 if (!priv->effective_speed_hz) in tsc2046_adc_setup_spi_msg()
539 priv->effective_speed_hz = priv->spi->max_speed_hz; in tsc2046_adc_setup_spi_msg()
542 priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US; in tsc2046_adc_setup_spi_msg()
543 priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC, in tsc2046_adc_setup_spi_msg()
544 priv->effective_speed_hz); in tsc2046_adc_setup_spi_msg()
551 for (ch_idx = 0; ch_idx < priv->dcfg->num_channels; ch_idx++) in tsc2046_adc_setup_spi_msg()
554 priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL); in tsc2046_adc_setup_spi_msg()
555 if (!priv->tx) in tsc2046_adc_setup_spi_msg()
556 return -ENOMEM; in tsc2046_adc_setup_spi_msg()
558 priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL); in tsc2046_adc_setup_spi_msg()
559 if (!priv->rx) in tsc2046_adc_setup_spi_msg()
560 return -ENOMEM; in tsc2046_adc_setup_spi_msg()
562 priv->xfer.tx_buf = priv->tx; in tsc2046_adc_setup_spi_msg()
563 priv->xfer.rx_buf = priv->rx; in tsc2046_adc_setup_spi_msg()
564 priv->xfer.len = size; in tsc2046_adc_setup_spi_msg()
565 spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1); in tsc2046_adc_setup_spi_msg()
573 struct device *dev = &priv->spi->dev; in tsc2046_adc_parse_fwnode()
576 for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) { in tsc2046_adc_parse_fwnode()
577 priv->ch_cfg[i].settling_time_us = 1; in tsc2046_adc_parse_fwnode()
578 priv->ch_cfg[i].oversampling_ratio = 1; in tsc2046_adc_parse_fwnode()
592 if (reg >= ARRAY_SIZE(priv->ch_cfg)) { in tsc2046_adc_parse_fwnode()
594 child, reg, ARRAY_SIZE(priv->ch_cfg)); in tsc2046_adc_parse_fwnode()
598 ret = fwnode_property_read_u32(child, "settling-time-us", &stl); in tsc2046_adc_parse_fwnode()
600 priv->ch_cfg[reg].settling_time_us = stl; in tsc2046_adc_parse_fwnode()
602 ret = fwnode_property_read_u32(child, "oversampling-ratio", in tsc2046_adc_parse_fwnode()
605 priv->ch_cfg[reg].oversampling_ratio = overs; in tsc2046_adc_parse_fwnode()
609 static int tsc2046_adc_probe(struct spi_device *spi) in tsc2046_adc_probe() argument
612 struct device *dev = &spi->dev; in tsc2046_adc_probe()
618 if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) { in tsc2046_adc_probe()
619 dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n", in tsc2046_adc_probe()
620 spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ); in tsc2046_adc_probe()
621 return -EINVAL; in tsc2046_adc_probe()
626 return -EINVAL; in tsc2046_adc_probe()
628 spi->bits_per_word = 8; in tsc2046_adc_probe()
629 spi->mode &= ~SPI_MODE_X_MASK; in tsc2046_adc_probe()
630 spi->mode |= SPI_MODE_0; in tsc2046_adc_probe()
631 ret = spi_setup(spi); in tsc2046_adc_probe()
633 return dev_err_probe(dev, ret, "Error in SPI setup\n"); in tsc2046_adc_probe()
637 return -ENOMEM; in tsc2046_adc_probe()
640 priv->dcfg = dcfg; in tsc2046_adc_probe()
642 priv->spi = spi; in tsc2046_adc_probe()
644 indio_dev->name = TI_TSC2046_NAME; in tsc2046_adc_probe()
645 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; in tsc2046_adc_probe()
646 indio_dev->channels = dcfg->channels; in tsc2046_adc_probe()
647 indio_dev->num_channels = dcfg->num_channels; in tsc2046_adc_probe()
648 indio_dev->info = &tsc2046_adc_info; in tsc2046_adc_probe()
656 mutex_init(&priv->slock); in tsc2046_adc_probe()
658 ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq, in tsc2046_adc_probe()
659 IRQF_NO_AUTOEN, indio_dev->name, indio_dev); in tsc2046_adc_probe()
663 trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name); in tsc2046_adc_probe()
665 return -ENOMEM; in tsc2046_adc_probe()
667 priv->trig = trig; in tsc2046_adc_probe()
669 trig->ops = &tsc2046_adc_trigger_ops; in tsc2046_adc_probe()
671 spin_lock_init(&priv->trig_lock); in tsc2046_adc_probe()
672 hrtimer_init(&priv->trig_timer, CLOCK_MONOTONIC, in tsc2046_adc_probe()
674 priv->trig_timer.function = tsc2046_adc_trig_more; in tsc2046_adc_probe()
690 indio_dev->trig = iio_trigger_get(priv->trig); in tsc2046_adc_probe()
696 { .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },