162 static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)  in ads131e08_exec_cmd()  argument
166 	ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);  in ads131e08_exec_cmd()
168 		dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);  in ads131e08_exec_cmd()
173 static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)  in ads131e08_read_reg()  argument
178 			.tx_buf = &st->tx_buf,  in ads131e08_read_reg()
181 				.value = st->sdecode_delay_us,  in ads131e08_read_reg()
185 			.rx_buf = &st->rx_buf,  in ads131e08_read_reg()
190 	st->tx_buf[0] = ADS131E08_CMD_RREG(reg);  in ads131e08_read_reg()
191 	st->tx_buf[1] = 0;  in ads131e08_read_reg()
193 	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));  in ads131e08_read_reg()
195 		dev_err(&st->spi->dev, "Read register failed\n");  in ads131e08_read_reg()
199 	return st->rx_buf[0];  in ads131e08_read_reg()
202 static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)  in ads131e08_write_reg()  argument
207 			.tx_buf = &st->tx_buf,  in ads131e08_write_reg()
210 				.value = st->sdecode_delay_us,  in ads131e08_write_reg()
216 	st->tx_buf[0] = ADS131E08_CMD_WREG(reg);  in ads131e08_write_reg()
217 	st->tx_buf[1] = 0;  in ads131e08_write_reg()
218 	st->tx_buf[2] = value;  in ads131e08_write_reg()
220 	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));  in ads131e08_write_reg()
222 		dev_err(&st->spi->dev, "Write register failed\n");  in ads131e08_write_reg()
227 static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)  in ads131e08_read_data()  argument
232 			.tx_buf = &st->tx_buf,  in ads131e08_read_data()
235 			.rx_buf = &st->rx_buf,  in ads131e08_read_data()
240 	st->tx_buf[0] = ADS131E08_CMD_RDATA;  in ads131e08_read_data()
242 	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));  in ads131e08_read_data()
244 		dev_err(&st->spi->dev, "Read data failed\n");  in ads131e08_read_data()
249 static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)  in ads131e08_set_data_rate()  argument
259 		dev_err(&st->spi->dev, "invalid data rate value\n");  in ads131e08_set_data_rate()
263 	reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);  in ads131e08_set_data_rate()
271 	ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);  in ads131e08_set_data_rate()
275 	st->data_rate = data_rate;  in ads131e08_set_data_rate()
276 	st->readback_len = ADS131E08_NUM_STATUS_BYTES +  in ads131e08_set_data_rate()
277 		ADS131E08_NUM_DATA_BYTES(st->data_rate) *  in ads131e08_set_data_rate()
278 		st->info->max_channels;  in ads131e08_set_data_rate()
283 static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,  in ads131e08_pga_gain_to_field_value()  argument
294 		dev_err(&st->spi->dev, "invalid PGA gain value\n");  in ads131e08_pga_gain_to_field_value()
301 static int ads131e08_set_pga_gain(struct ads131e08_state *st,  in ads131e08_set_pga_gain()  argument
306 	field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);  in ads131e08_set_pga_gain()
310 	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);  in ads131e08_set_pga_gain()
317 	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);  in ads131e08_set_pga_gain()
320 static int ads131e08_validate_channel_mux(struct ads131e08_state *st,  in ads131e08_validate_channel_mux()  argument
331 		dev_err(&st->spi->dev, "invalid channel mux value\n");  in ads131e08_validate_channel_mux()
338 static int ads131e08_set_channel_mux(struct ads131e08_state *st,  in ads131e08_set_channel_mux()  argument
343 	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);  in ads131e08_set_channel_mux()
350 	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);  in ads131e08_set_channel_mux()
353 static int ads131e08_power_down_channel(struct ads131e08_state *st,  in ads131e08_power_down_channel()  argument
358 	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);  in ads131e08_power_down_channel()
365 	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);  in ads131e08_power_down_channel()
368 static int ads131e08_config_reference_voltage(struct ads131e08_state *st)  in ads131e08_config_reference_voltage()  argument
372 	reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);  in ads131e08_config_reference_voltage()
377 	if (!st->vref_reg) {  in ads131e08_config_reference_voltage()
381 			st->vref_mv == ADS131E08_VREF_4V_mV);  in ads131e08_config_reference_voltage()
384 	return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);  in ads131e08_config_reference_voltage()
390 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_initial_config()  local
394 	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);  in ads131e08_initial_config()
398 	udelay(st->reset_delay_us);  in ads131e08_initial_config()
401 	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);  in ads131e08_initial_config()
405 	ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);  in ads131e08_initial_config()
409 	ret = ads131e08_config_reference_voltage(st);  in ads131e08_initial_config()
414 		ret = ads131e08_set_pga_gain(st, channel->channel,  in ads131e08_initial_config()
415 			st->channel_config[i].pga_gain);  in ads131e08_initial_config()
419 		ret = ads131e08_set_channel_mux(st, channel->channel,  in ads131e08_initial_config()
420 			st->channel_config[i].mux);  in ads131e08_initial_config()
429 	for_each_clear_bit(i, &active_channels, st->info->max_channels) {  in ads131e08_initial_config()
430 		ret = ads131e08_power_down_channel(st, i, true);  in ads131e08_initial_config()
436 	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);  in ads131e08_initial_config()
447 	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);  in ads131e08_initial_config()
453 	return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);  in ads131e08_initial_config()
456 static int ads131e08_pool_data(struct ads131e08_state *st)  in ads131e08_pool_data()  argument
461 	reinit_completion(&st->completion);  in ads131e08_pool_data()
463 	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);  in ads131e08_pool_data()
468 	ret = wait_for_completion_timeout(&st->completion, timeout);  in ads131e08_pool_data()
472 	ret = ads131e08_read_data(st, st->readback_len);  in ads131e08_pool_data()
476 	return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);  in ads131e08_pool_data()
482 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_read_direct()  local
486 	ret = ads131e08_pool_data(st);  in ads131e08_read_direct()
490 	src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +  in ads131e08_read_direct()
491 		channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);  in ads131e08_read_direct()
493 	num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);  in ads131e08_read_direct()
503 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_read_raw()  local
520 		if (st->vref_reg) {  in ads131e08_read_raw()
521 			ret = regulator_get_voltage(st->vref_reg);  in ads131e08_read_raw()
527 			*value = st->vref_mv;  in ads131e08_read_raw()
530 		*value /= st->channel_config[channel->address].pga_gain;  in ads131e08_read_raw()
531 		*value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;  in ads131e08_read_raw()
536 		*value = st->data_rate;  in ads131e08_read_raw()
549 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_write_raw()  local
558 		ret = ads131e08_set_data_rate(st, value);  in ads131e08_write_raw()
581 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_debugfs_reg_access()  local
584 		int ret = ads131e08_read_reg(st, reg);  in ads131e08_debugfs_reg_access()
589 	return ads131e08_write_reg(st, reg, writeval);  in ads131e08_debugfs_reg_access()
602 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_set_trigger_state()  local
605 	return ads131e08_exec_cmd(st, cmd);  in ads131e08_set_trigger_state()
617 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_trigger_handler()  local
629 	unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);  in ads131e08_trigger_handler()
633 		ret = ads131e08_read_data(st, st->readback_len);  in ads131e08_trigger_handler()
635 		ret = ads131e08_pool_data(st);  in ads131e08_trigger_handler()
641 		src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;  in ads131e08_trigger_handler()
642 		dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;  in ads131e08_trigger_handler()
669 	iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data,  in ads131e08_trigger_handler()
681 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_interrupt()  local
684 		iio_trigger_poll(st->trig);  in ads131e08_interrupt()
686 		complete(&st->completion);  in ads131e08_interrupt()
693 	struct ads131e08_state *st = iio_priv(indio_dev);  in ads131e08_alloc_channels()  local
695 	struct device *dev = &st->spi->dev;  in ads131e08_alloc_channels()
707 		st->vref_mv = ADS131E08_VREF_2V4_mV;  in ads131e08_alloc_channels()
710 		st->vref_mv = ADS131E08_VREF_4V_mV;  in ads131e08_alloc_channels()
713 		dev_err(&st->spi->dev, "invalid internal voltage reference\n");  in ads131e08_alloc_channels()
719 		dev_err(&st->spi->dev, "no channel children\n");  in ads131e08_alloc_channels()
723 	if (num_channels > st->info->max_channels) {  in ads131e08_alloc_channels()
724 		dev_err(&st->spi->dev, "num of channel children out of range\n");  in ads131e08_alloc_channels()
728 	channels = devm_kcalloc(&st->spi->dev, num_channels,  in ads131e08_alloc_channels()
733 	channel_config = devm_kcalloc(&st->spi->dev, num_channels,  in ads131e08_alloc_channels()
748 			ret = ads131e08_pga_gain_to_field_value(st, tmp);  in ads131e08_alloc_channels()
759 			ret = ads131e08_validate_channel_mux(st, tmp);  in ads131e08_alloc_channels()
784 	st->channel_config = channel_config;  in ads131e08_alloc_channels()
791 	struct ads131e08_state *st = data;  in ads131e08_regulator_disable()  local
793 	regulator_disable(st->vref_reg);  in ads131e08_regulator_disable()
798 	struct ads131e08_state *st = data;  in ads131e08_clk_disable()  local
800 	clk_disable_unprepare(st->adc_clk);  in ads131e08_clk_disable()
806 	struct ads131e08_state *st;  in ads131e08_probe()  local
818 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));  in ads131e08_probe()
824 	st = iio_priv(indio_dev);  in ads131e08_probe()
825 	st->info = info;  in ads131e08_probe()
826 	st->spi = spi;  in ads131e08_probe()
832 	indio_dev->name = st->info->name;  in ads131e08_probe()
836 	init_completion(&st->completion);  in ads131e08_probe()
851 	st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",  in ads131e08_probe()
853 	if (!st->trig) {  in ads131e08_probe()
858 	st->trig->ops = &ads131e08_trigger_ops;  in ads131e08_probe()
859 	st->trig->dev.parent = &spi->dev;  in ads131e08_probe()
860 	iio_trigger_set_drvdata(st->trig, indio_dev);  in ads131e08_probe()
861 	ret = devm_iio_trigger_register(&spi->dev, st->trig);  in ads131e08_probe()
867 	indio_dev->trig = iio_trigger_get(st->trig);  in ads131e08_probe()
876 	st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");  in ads131e08_probe()
877 	if (!IS_ERR(st->vref_reg)) {  in ads131e08_probe()
878 		ret = regulator_enable(st->vref_reg);  in ads131e08_probe()
885 		ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);  in ads131e08_probe()
889 		if (PTR_ERR(st->vref_reg) != -ENODEV)  in ads131e08_probe()
890 			return PTR_ERR(st->vref_reg);  in ads131e08_probe()
892 		st->vref_reg = NULL;  in ads131e08_probe()
895 	st->adc_clk = devm_clk_get(&spi->dev, "adc-clk");  in ads131e08_probe()
896 	if (IS_ERR(st->adc_clk))  in ads131e08_probe()
897 		return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),  in ads131e08_probe()
900 	ret = clk_prepare_enable(st->adc_clk);  in ads131e08_probe()
906 	ret = devm_add_action_or_reset(&spi->dev, ads131e08_clk_disable, st);  in ads131e08_probe()
910 	adc_clk_hz = clk_get_rate(st->adc_clk);  in ads131e08_probe()
917 	st->sdecode_delay_us = DIV_ROUND_UP(  in ads131e08_probe()
919 	st->reset_delay_us = DIV_ROUND_UP(  in ads131e08_probe()