Lines Matching +full:adc +full:- +full:chan
1 // SPDX-License-Identifier: GPL-2.0
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
23 #define DRIVER_NAME "rzg2l-adc"
92 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) in rzg2l_adc_readl() argument
94 return readl(adc->base + reg); in rzg2l_adc_readl()
97 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val) in rzg2l_adc_writel() argument
99 writel(val, adc->base + reg); in rzg2l_adc_writel()
102 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on) in rzg2l_adc_pwr() argument
106 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); in rzg2l_adc_pwr()
111 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); in rzg2l_adc_pwr()
115 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start) in rzg2l_adc_start_stop() argument
120 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); in rzg2l_adc_start_stop()
125 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); in rzg2l_adc_start_stop()
132 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); in rzg2l_adc_start_stop()
133 timeout--; in rzg2l_adc_start_stop()
135 pr_err("%s stopping ADC timed out\n", __func__); in rzg2l_adc_start_stop()
141 static void rzg2l_set_trigger(struct rzg2l_adc *adc) in rzg2l_set_trigger() argument
147 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid in rzg2l_set_trigger()
148 * BS[4] - Enable 1-buffer mode in rzg2l_set_trigger()
149 * MS[1] - Enable Select mode in rzg2l_set_trigger()
150 * TRG[0] - Enable software trigger mode in rzg2l_set_trigger()
152 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1)); in rzg2l_set_trigger()
157 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg); in rzg2l_set_trigger()
160 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch) in rzg2l_adc_conversion_setup() argument
164 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY) in rzg2l_adc_conversion_setup()
165 return -EBUSY; in rzg2l_adc_conversion_setup()
167 rzg2l_set_trigger(adc); in rzg2l_adc_conversion_setup()
170 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2)); in rzg2l_adc_conversion_setup()
173 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg); in rzg2l_adc_conversion_setup()
177 * INTS[31] - Select pulse signal in rzg2l_adc_conversion_setup()
178 * CSEEN[16] - Enable channel select error interrupt in rzg2l_adc_conversion_setup()
179 * INTEN[7:0] - Select channel interrupt in rzg2l_adc_conversion_setup()
181 reg = rzg2l_adc_readl(adc, RZG2L_ADINT); in rzg2l_adc_conversion_setup()
185 rzg2l_adc_writel(adc, RZG2L_ADINT, reg); in rzg2l_adc_conversion_setup()
192 struct device *dev = indio_dev->dev.parent; in rzg2l_adc_set_power()
200 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch) in rzg2l_adc_conversion() argument
208 ret = rzg2l_adc_conversion_setup(adc, ch); in rzg2l_adc_conversion()
214 reinit_completion(&adc->completion); in rzg2l_adc_conversion()
216 rzg2l_adc_start_stop(adc, true); in rzg2l_adc_conversion()
218 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) { in rzg2l_adc_conversion()
219 rzg2l_adc_writel(adc, RZG2L_ADINT, in rzg2l_adc_conversion()
220 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK); in rzg2l_adc_conversion()
221 rzg2l_adc_start_stop(adc, false); in rzg2l_adc_conversion()
223 return -ETIMEDOUT; in rzg2l_adc_conversion()
230 struct iio_chan_spec const *chan, in rzg2l_adc_read_raw() argument
233 struct rzg2l_adc *adc = iio_priv(indio_dev); in rzg2l_adc_read_raw() local
239 if (chan->type != IIO_VOLTAGE) in rzg2l_adc_read_raw()
240 return -EINVAL; in rzg2l_adc_read_raw()
242 mutex_lock(&adc->lock); in rzg2l_adc_read_raw()
243 ch = chan->channel & RZG2L_ADC_CHN_MASK; in rzg2l_adc_read_raw()
244 ret = rzg2l_adc_conversion(indio_dev, adc, ch); in rzg2l_adc_read_raw()
246 mutex_unlock(&adc->lock); in rzg2l_adc_read_raw()
249 *val = adc->last_val[ch]; in rzg2l_adc_read_raw()
250 mutex_unlock(&adc->lock); in rzg2l_adc_read_raw()
255 return -EINVAL; in rzg2l_adc_read_raw()
260 const struct iio_chan_spec *chan, in rzg2l_adc_read_label() argument
263 if (chan->channel >= RZG2L_ADC_MAX_CHANNELS) in rzg2l_adc_read_label()
264 return -EINVAL; in rzg2l_adc_read_label()
266 return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]); in rzg2l_adc_read_label()
276 struct rzg2l_adc *adc = dev_id; in rzg2l_adc_isr() local
281 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS); in rzg2l_adc_isr()
285 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); in rzg2l_adc_isr()
294 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK; in rzg2l_adc_isr()
297 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); in rzg2l_adc_isr()
299 complete(&adc->completion); in rzg2l_adc_isr()
304 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc) in rzg2l_adc_parse_properties() argument
314 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); in rzg2l_adc_parse_properties()
316 return -ENOMEM; in rzg2l_adc_parse_properties()
318 num_channels = device_get_child_node_count(&pdev->dev); in rzg2l_adc_parse_properties()
320 dev_err(&pdev->dev, "no channel children\n"); in rzg2l_adc_parse_properties()
321 return -ENODEV; in rzg2l_adc_parse_properties()
325 dev_err(&pdev->dev, "num of channel children out of range\n"); in rzg2l_adc_parse_properties()
326 return -EINVAL; in rzg2l_adc_parse_properties()
329 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array), in rzg2l_adc_parse_properties()
332 return -ENOMEM; in rzg2l_adc_parse_properties()
335 device_for_each_child_node(&pdev->dev, fwnode) { in rzg2l_adc_parse_properties()
341 return -EINVAL; in rzg2l_adc_parse_properties()
351 data->num_channels = num_channels; in rzg2l_adc_parse_properties()
352 data->channels = chan_array; in rzg2l_adc_parse_properties()
353 adc->data = data; in rzg2l_adc_parse_properties()
358 static int rzg2l_adc_hw_init(struct rzg2l_adc *adc) in rzg2l_adc_hw_init() argument
364 ret = clk_prepare_enable(adc->pclk); in rzg2l_adc_hw_init()
369 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); in rzg2l_adc_hw_init()
371 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); in rzg2l_adc_hw_init()
373 while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) { in rzg2l_adc_hw_init()
375 ret = -EBUSY; in rzg2l_adc_hw_init()
378 timeout--; in rzg2l_adc_hw_init()
383 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC); in rzg2l_adc_hw_init()
386 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg); in rzg2l_adc_hw_init()
390 * ADIL[31:24] - Should be always set to 0 in rzg2l_adc_hw_init()
391 * ADCMP[23:16] - Should be always set to 0xe in rzg2l_adc_hw_init()
392 * ADSMP[15:0] - Set default (0x578) sampling period in rzg2l_adc_hw_init()
394 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3)); in rzg2l_adc_hw_init()
399 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg); in rzg2l_adc_hw_init()
402 clk_disable_unprepare(adc->pclk); in rzg2l_adc_hw_init()
411 pm_runtime_disable(dev->parent); in rzg2l_adc_pm_runtime_disable()
418 pm_runtime_set_suspended(dev->parent); in rzg2l_adc_pm_runtime_set_suspended()
428 struct device *dev = &pdev->dev; in rzg2l_adc_probe()
430 struct rzg2l_adc *adc; in rzg2l_adc_probe() local
434 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); in rzg2l_adc_probe()
436 return -ENOMEM; in rzg2l_adc_probe()
438 adc = iio_priv(indio_dev); in rzg2l_adc_probe()
440 ret = rzg2l_adc_parse_properties(pdev, adc); in rzg2l_adc_probe()
444 mutex_init(&adc->lock); in rzg2l_adc_probe()
446 adc->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_adc_probe()
447 if (IS_ERR(adc->base)) in rzg2l_adc_probe()
448 return PTR_ERR(adc->base); in rzg2l_adc_probe()
450 adc->pclk = devm_clk_get(dev, "pclk"); in rzg2l_adc_probe()
451 if (IS_ERR(adc->pclk)) { in rzg2l_adc_probe()
453 return PTR_ERR(adc->pclk); in rzg2l_adc_probe()
456 adc->adclk = devm_clk_get(dev, "adclk"); in rzg2l_adc_probe()
457 if (IS_ERR(adc->adclk)) { in rzg2l_adc_probe()
459 return PTR_ERR(adc->adclk); in rzg2l_adc_probe()
462 adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n"); in rzg2l_adc_probe()
463 if (IS_ERR(adc->adrstn)) { in rzg2l_adc_probe()
465 return PTR_ERR(adc->adrstn); in rzg2l_adc_probe()
468 adc->presetn = devm_reset_control_get_exclusive(dev, "presetn"); in rzg2l_adc_probe()
469 if (IS_ERR(adc->presetn)) { in rzg2l_adc_probe()
471 return PTR_ERR(adc->presetn); in rzg2l_adc_probe()
474 ret = reset_control_deassert(adc->adrstn); in rzg2l_adc_probe()
476 dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret); in rzg2l_adc_probe()
480 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
481 rzg2l_adc_reset_assert, adc->adrstn); in rzg2l_adc_probe()
483 dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n", in rzg2l_adc_probe()
488 ret = reset_control_deassert(adc->presetn); in rzg2l_adc_probe()
490 dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret); in rzg2l_adc_probe()
494 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
495 rzg2l_adc_reset_assert, adc->presetn); in rzg2l_adc_probe()
497 dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n", in rzg2l_adc_probe()
502 ret = rzg2l_adc_hw_init(adc); in rzg2l_adc_probe()
504 dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret); in rzg2l_adc_probe()
515 0, dev_name(dev), adc); in rzg2l_adc_probe()
519 init_completion(&adc->completion); in rzg2l_adc_probe()
523 indio_dev->name = DRIVER_NAME; in rzg2l_adc_probe()
524 indio_dev->info = &rzg2l_adc_iio_info; in rzg2l_adc_probe()
525 indio_dev->modes = INDIO_DIRECT_MODE; in rzg2l_adc_probe()
526 indio_dev->channels = adc->data->channels; in rzg2l_adc_probe()
527 indio_dev->num_channels = adc->data->num_channels; in rzg2l_adc_probe()
530 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
531 rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev); in rzg2l_adc_probe()
536 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_adc_probe()
537 rzg2l_adc_pm_runtime_disable, &indio_dev->dev); in rzg2l_adc_probe()
545 { .compatible = "renesas,rzg2l-adc",},
553 struct rzg2l_adc *adc = iio_priv(indio_dev); in rzg2l_adc_pm_runtime_suspend() local
555 rzg2l_adc_pwr(adc, false); in rzg2l_adc_pm_runtime_suspend()
556 clk_disable_unprepare(adc->adclk); in rzg2l_adc_pm_runtime_suspend()
557 clk_disable_unprepare(adc->pclk); in rzg2l_adc_pm_runtime_suspend()
565 struct rzg2l_adc *adc = iio_priv(indio_dev); in rzg2l_adc_pm_runtime_resume() local
568 ret = clk_prepare_enable(adc->pclk); in rzg2l_adc_pm_runtime_resume()
572 ret = clk_prepare_enable(adc->adclk); in rzg2l_adc_pm_runtime_resume()
574 clk_disable_unprepare(adc->pclk); in rzg2l_adc_pm_runtime_resume()
578 rzg2l_adc_pwr(adc, true); in rzg2l_adc_pm_runtime_resume()
600 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
601 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");