1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright 2011-2015 Analog Devices Inc.
30 #define AD7192_REG_COMM		0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT		0 /* Status Register	     (RO, 8-bit) */
32 #define AD7192_REG_MODE		1 /* Mode Register	     (RW, 24-bit */
33 #define AD7192_REG_CONF		2 /* Configuration Register  (RW, 24-bit) */
34 #define AD7192_REG_DATA		3 /* Data Register	     (RO, 24/32-bit) */
35 #define AD7192_REG_ID		4 /* ID Register	     (RO, 8-bit) */
36 #define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RO, 8-bit) */
37 #define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit */
38 				  /* (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE	7 /* Full-Scale Register */
40 				  /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
75 #define AD7192_MODE_PWRDN		3 /* Power-Down Mode */
76 #define AD7192_MODE_CAL_INT_ZERO	4 /* Internal Zero-Scale Calibration */
77 #define AD7192_MODE_CAL_INT_FULL	5 /* Internal Full-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_ZERO	6 /* System Zero-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_FULL	7 /* System Full-Scale Calibration */
93 #define AD7192_CONF_REFSEL	BIT(20) /* REFIN1/REFIN2 Reference Select */
102 #define AD7192_CH_AIN1P_AIN2M	BIT(0) /* AIN1(+) - AIN2(-) */
103 #define AD7192_CH_AIN3P_AIN4M	BIT(1) /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_AIN2P_AIN2M	BIT(3) /* AIN2(+) - AIN2(-) */
106 #define AD7192_CH_AIN1		BIT(4) /* AIN1 - AINCOM */
107 #define AD7192_CH_AIN2		BIT(5) /* AIN2 - AINCOM */
108 #define AD7192_CH_AIN3		BIT(6) /* AIN3 - AINCOM */
109 #define AD7192_CH_AIN4		BIT(7) /* AIN4 - AINCOM */
111 #define AD7193_CH_AIN1P_AIN2M	0x001  /* AIN1(+) - AIN2(-) */
112 #define AD7193_CH_AIN3P_AIN4M	0x002  /* AIN3(+) - AIN4(-) */
113 #define AD7193_CH_AIN5P_AIN6M	0x004  /* AIN5(+) - AIN6(-) */
114 #define AD7193_CH_AIN7P_AIN8M	0x008  /* AIN7(+) - AIN8(-) */
116 #define AD7193_CH_AIN2P_AIN2M	0x200 /* AIN2(+) - AIN2(-) */
117 #define AD7193_CH_AIN1		0x401 /* AIN1 - AINCOM */
118 #define AD7193_CH_AIN2		0x402 /* AIN2 - AINCOM */
119 #define AD7193_CH_AIN3		0x404 /* AIN3 - AINCOM */
120 #define AD7193_CH_AIN4		0x408 /* AIN4 - AINCOM */
121 #define AD7193_CH_AIN5		0x410 /* AIN5 - AINCOM */
122 #define AD7193_CH_AIN6		0x420 /* AIN6 - AINCOM */
123 #define AD7193_CH_AIN7		0x440 /* AIN7 - AINCOM */
124 #define AD7193_CH_AIN8		0x480 /* AIN7 - AINCOM */
125 #define AD7193_CH_AINCOM	0x600 /* AINCOM - AINCOM */
135 #define AD7192_GPOCON_BPDSW	BIT(6) /* Bridge power-down switch enable */
206 	st->syscalib_mode[chan->channel] = mode;  in ad7192_set_syscalib_mode()
216 	return st->syscalib_mode[chan->channel];  in ad7192_get_syscalib_mode()
232 	temp = st->syscalib_mode[chan->channel];  in ad7192_write_syscalib()
235 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,  in ad7192_write_syscalib()
236 					      chan->address);  in ad7192_write_syscalib()
238 			ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,  in ad7192_write_syscalib()
239 					      chan->address);  in ad7192_write_syscalib()
273 	st->conf &= ~AD7192_CONF_CHAN_MASK;  in ad7192_set_channel()
274 	st->conf |= AD7192_CONF_CHAN(channel);  in ad7192_set_channel()
276 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_channel()
284 	st->mode &= ~AD7192_MODE_SEL_MASK;  in ad7192_set_mode()
285 	st->mode |= AD7192_MODE_SEL(mode);  in ad7192_set_mode()
287 	return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_mode()
312 	return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,  in ad7192_calibrate_all()
324 	struct device_node *np = st->sd.spi->dev.of_node;  in ad7192_of_clock_select()
330 	if (st->mclk) {  in ad7192_of_clock_select()
331 		if (of_property_read_bool(np, "adi,int-clock-output-enable"))  in ad7192_of_clock_select()
334 		if (of_property_read_bool(np, "adi,clock-xtal"))  in ad7192_of_clock_select()
345 	struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);  in ad7192_setup()
352 	ret = ad_sd_reset(&st->sd, 48);  in ad7192_setup()
358 	ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);  in ad7192_setup()
364 	if (id != st->chip_info->chip_id)  in ad7192_setup()
365 		dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",  in ad7192_setup()
368 	st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |  in ad7192_setup()
369 		AD7192_MODE_CLKSRC(st->clock_sel) |  in ad7192_setup()
372 	st->conf = AD7192_CONF_GAIN(0);  in ad7192_setup()
374 	rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");  in ad7192_setup()
376 		st->mode |= AD7192_MODE_REJ60;  in ad7192_setup()
378 	refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");  in ad7192_setup()
379 	if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)  in ad7192_setup()
380 		st->conf |= AD7192_CONF_REFSEL;  in ad7192_setup()
382 	st->conf &= ~AD7192_CONF_CHOP;  in ad7192_setup()
383 	st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_setup()
385 	buf_en = of_property_read_bool(np, "adi,buffer-enable");  in ad7192_setup()
387 		st->conf |= AD7192_CONF_BUF;  in ad7192_setup()
391 		st->conf |= AD7192_CONF_UNIPOLAR;  in ad7192_setup()
394 						"adi,burnout-currents-enable");  in ad7192_setup()
396 		st->conf |= AD7192_CONF_BURN;  in ad7192_setup()
398 		dev_warn(&st->sd.spi->dev,  in ad7192_setup()
402 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_setup()
406 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_setup()
415 	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {  in ad7192_setup()
416 		scale_uv = ((u64)st->int_vref_mv * 100000000)  in ad7192_setup()
417 			>> (indio_dev->channels[0].scan_type.realbits -  in ad7192_setup()
418 			((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));  in ad7192_setup()
421 		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;  in ad7192_setup()
422 		st->scale_avail[i][0] = scale_uv;  in ad7192_setup()
435 	return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));  in ad7192_show_ac_excitation()
445 	return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));  in ad7192_show_bridge_switch()
467 	switch ((u32)this_attr->address) {  in ad7192_set()
470 			st->gpocon |= AD7192_GPOCON_BPDSW;  in ad7192_set()
472 			st->gpocon &= ~AD7192_GPOCON_BPDSW;  in ad7192_set()
474 		ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);  in ad7192_set()
478 			st->mode |= AD7192_MODE_ACX;  in ad7192_set()
480 			st->mode &= ~AD7192_MODE_ACX;  in ad7192_set()
482 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set()
485 		ret = -EINVAL;  in ad7192_set()
499 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_available_filter_freq()
500 				 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
503 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_available_filter_freq()
504 				 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
507 	fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));  in ad7192_get_available_filter_freq()
524 		len += scnprintf(buf + len, PAGE_SIZE - len,  in ad7192_show_filter_avail()
528 	buf[len - 1] = '\n';  in ad7192_show_filter_avail()
583 		diff_new = abs(freq - freq_avail[i]);  in ad7192_set_3db_filter_freq()
592 		st->f_order = AD7192_SYNC4_FILTER;  in ad7192_set_3db_filter_freq()
593 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
595 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
598 		st->f_order = AD7192_SYNC3_FILTER;  in ad7192_set_3db_filter_freq()
599 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
601 		st->conf |= AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
604 		st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_set_3db_filter_freq()
605 		st->mode &= ~AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
607 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
610 		st->f_order = AD7192_NO_SYNC_FILTER;  in ad7192_set_3db_filter_freq()
611 		st->mode |= AD7192_MODE_SINC3;  in ad7192_set_3db_filter_freq()
613 		st->conf &= ~AD7192_CONF_CHOP;  in ad7192_set_3db_filter_freq()
617 	ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_set_3db_filter_freq()
621 	return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);  in ad7192_set_3db_filter_freq()
628 	fadc = DIV_ROUND_CLOSEST(st->fclk,  in ad7192_get_3db_filter_freq()
629 				 st->f_order * AD7192_MODE_RATE(st->mode));  in ad7192_get_3db_filter_freq()
631 	if (st->conf & AD7192_CONF_CHOP)  in ad7192_get_3db_filter_freq()
633 	if (st->mode & AD7192_MODE_SINC3)  in ad7192_get_3db_filter_freq()
646 	bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);  in ad7192_read_raw()
652 		switch (chan->type) {  in ad7192_read_raw()
654 			mutex_lock(&st->lock);  in ad7192_read_raw()
655 			*val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];  in ad7192_read_raw()
656 			*val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];  in ad7192_read_raw()
657 			mutex_unlock(&st->lock);  in ad7192_read_raw()
664 			return -EINVAL;  in ad7192_read_raw()
668 			*val = -(1 << (chan->scan_type.realbits - 1));  in ad7192_read_raw()
672 		if (chan->type == IIO_TEMP)  in ad7192_read_raw()
673 			*val -= 273 * ad7192_get_temp_scale(unipolar);  in ad7192_read_raw()
676 		*val = st->fclk /  in ad7192_read_raw()
677 			(st->f_order * 1024 * AD7192_MODE_RATE(st->mode));  in ad7192_read_raw()
685 	return -EINVAL;  in ad7192_read_raw()
704 		ret = -EINVAL;  in ad7192_write_raw()
705 		mutex_lock(&st->lock);  in ad7192_write_raw()
706 		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)  in ad7192_write_raw()
707 			if (val2 == st->scale_avail[i][1]) {  in ad7192_write_raw()
709 				tmp = st->conf;  in ad7192_write_raw()
710 				st->conf &= ~AD7192_CONF_GAIN(-1);  in ad7192_write_raw()
711 				st->conf |= AD7192_CONF_GAIN(i);  in ad7192_write_raw()
712 				if (tmp == st->conf)  in ad7192_write_raw()
714 				ad_sd_write_reg(&st->sd, AD7192_REG_CONF,  in ad7192_write_raw()
715 						3, st->conf);  in ad7192_write_raw()
719 		mutex_unlock(&st->lock);  in ad7192_write_raw()
723 			ret = -EINVAL;  in ad7192_write_raw()
727 		div = st->fclk / (val * st->f_order * 1024);  in ad7192_write_raw()
729 			ret = -EINVAL;  in ad7192_write_raw()
733 		st->mode &= ~AD7192_MODE_RATE(-1);  in ad7192_write_raw()
734 		st->mode |= AD7192_MODE_RATE(div);  in ad7192_write_raw()
735 		ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);  in ad7192_write_raw()
741 		ret = -EINVAL;  in ad7192_write_raw()
761 		return -EINVAL;  in ad7192_write_raw_get_fmt()
774 		*vals = (int *)st->scale_avail;  in ad7192_read_avail()
777 		*length = ARRAY_SIZE(st->scale_avail) * 2;  in ad7192_read_avail()
782 	return -EINVAL;  in ad7192_read_avail()
807 		.differential = ((_channel2) == -1 ? 0 : 1), \
835 	__AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
839 	__AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
843 	__AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
898 	switch (st->chip_info->chip_id) {  in ad7192_channels_config()
900 		indio_dev->channels = ad7193_channels;  in ad7192_channels_config()
901 		indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);  in ad7192_channels_config()
904 		indio_dev->channels = ad7192_channels;  in ad7192_channels_config()
905 		indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);  in ad7192_channels_config()
928 	if (!spi->irq) {  in ad7192_probe()
929 		dev_err(&spi->dev, "no IRQ?\n");  in ad7192_probe()
930 		return -ENODEV;  in ad7192_probe()
933 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));  in ad7192_probe()
935 		return -ENOMEM;  in ad7192_probe()
939 	mutex_init(&st->lock);  in ad7192_probe()
941 	st->avdd = devm_regulator_get(&spi->dev, "avdd");  in ad7192_probe()
942 	if (IS_ERR(st->avdd))  in ad7192_probe()
943 		return PTR_ERR(st->avdd);  in ad7192_probe()
945 	ret = regulator_enable(st->avdd);  in ad7192_probe()
947 		dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");  in ad7192_probe()
951 	ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);  in ad7192_probe()
955 	st->dvdd = devm_regulator_get(&spi->dev, "dvdd");  in ad7192_probe()
956 	if (IS_ERR(st->dvdd))  in ad7192_probe()
957 		return PTR_ERR(st->dvdd);  in ad7192_probe()
959 	ret = regulator_enable(st->dvdd);  in ad7192_probe()
961 		dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");  in ad7192_probe()
965 	ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd);  in ad7192_probe()
969 	ret = regulator_get_voltage(st->avdd);  in ad7192_probe()
971 		dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");  in ad7192_probe()
974 	st->int_vref_mv = ret / 1000;  in ad7192_probe()
976 	st->chip_info = of_device_get_match_data(&spi->dev);  in ad7192_probe()
977 	indio_dev->name = st->chip_info->name;  in ad7192_probe()
978 	indio_dev->modes = INDIO_DIRECT_MODE;  in ad7192_probe()
984 	if (st->chip_info->chip_id == CHIPID_AD7195)  in ad7192_probe()
985 		indio_dev->info = &ad7195_info;  in ad7192_probe()
987 		indio_dev->info = &ad7192_info;  in ad7192_probe()
989 	ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);  in ad7192_probe()
991 	ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);  in ad7192_probe()
995 	st->fclk = AD7192_INT_FREQ_MHZ;  in ad7192_probe()
997 	st->mclk = devm_clk_get_optional(&spi->dev, "mclk");  in ad7192_probe()
998 	if (IS_ERR(st->mclk))  in ad7192_probe()
999 		return PTR_ERR(st->mclk);  in ad7192_probe()
1001 	st->clock_sel = ad7192_of_clock_select(st);  in ad7192_probe()
1003 	if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||  in ad7192_probe()
1004 	    st->clock_sel == AD7192_CLK_EXT_MCLK2) {  in ad7192_probe()
1005 		ret = clk_prepare_enable(st->mclk);  in ad7192_probe()
1009 		ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable,  in ad7192_probe()
1010 					       st->mclk);  in ad7192_probe()
1014 		st->fclk = clk_get_rate(st->mclk);  in ad7192_probe()
1015 		if (!ad7192_valid_external_frequency(st->fclk)) {  in ad7192_probe()
1016 			dev_err(&spi->dev,  in ad7192_probe()
1018 			return -EINVAL;  in ad7192_probe()
1022 	ret = ad7192_setup(st, spi->dev.of_node);  in ad7192_probe()
1026 	return devm_iio_device_register(&spi->dev, indio_dev);  in ad7192_probe()