Lines Matching +full:i3c +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
22 /* Master Mode Registers */
146 * struct svc_i3c_master - Silvaco I3C Master structure
147 * @base: I3C master controller
153 * @hj_work: Hot-join work
198 * struct svc_i3c_i2c_dev_data - Device specific data
199 * @index: Index in the master tables corresponding to this device
200 * @ibi: IBI slot index in the master structure
209 static bool svc_i3c_master_error(struct svc_i3c_master *master) in svc_i3c_master_error() argument
213 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_error()
215 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
216 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
217 dev_err(master->dev, in svc_i3c_master_error()
227 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) in svc_i3c_master_enable_interrupts() argument
229 writel(mask, master->regs + SVC_I3C_MINTSET); in svc_i3c_master_enable_interrupts()
232 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) in svc_i3c_master_disable_interrupts() argument
234 u32 mask = readl(master->regs + SVC_I3C_MINTSET); in svc_i3c_master_disable_interrupts()
236 writel(mask, master->regs + SVC_I3C_MINTCLR); in svc_i3c_master_disable_interrupts()
240 to_svc_i3c_master(struct i3c_master_controller *master) in to_svc_i3c_master() argument
242 return container_of(master, struct svc_i3c_master, base); in to_svc_i3c_master()
247 struct svc_i3c_master *master; in svc_i3c_master_hj_work() local
249 master = container_of(work, struct svc_i3c_master, hj_work); in svc_i3c_master_hj_work()
250 i3c_master_do_daa(&master->base); in svc_i3c_master_hj_work()
254 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, in svc_i3c_master_dev_from_addr() argument
260 if (master->addrs[i] == ibiaddr) in svc_i3c_master_dev_from_addr()
266 return master->descs[i]; in svc_i3c_master_dev_from_addr()
269 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) in svc_i3c_master_emit_stop() argument
271 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_emit_stop()
282 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) in svc_i3c_master_clear_merrwarn() argument
284 writel(readl(master->regs + SVC_I3C_MERRWARN), in svc_i3c_master_clear_merrwarn()
285 master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_clear_merrwarn()
288 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, in svc_i3c_master_handle_ibi() argument
297 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); in svc_i3c_master_handle_ibi()
299 return -ENOSPC; in svc_i3c_master_handle_ibi()
301 slot->len = 0; in svc_i3c_master_handle_ibi()
302 buf = slot->data; in svc_i3c_master_handle_ibi()
304 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && in svc_i3c_master_handle_ibi()
305 slot->len < SVC_I3C_FIFO_SIZE) { in svc_i3c_master_handle_ibi()
306 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_handle_ibi()
308 readsl(master->regs + SVC_I3C_MRDATAB, buf, count); in svc_i3c_master_handle_ibi()
309 slot->len += count; in svc_i3c_master_handle_ibi()
313 master->ibi.tbq_slot = slot; in svc_i3c_master_handle_ibi()
318 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master, in svc_i3c_master_ack_ibi() argument
329 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ack_ibi()
332 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master) in svc_i3c_master_nack_ibi() argument
336 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_nack_ibi()
341 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); in svc_i3c_master_ibi_work() local
351 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ibi_work()
354 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, in svc_i3c_master_ibi_work()
357 dev_err(master->dev, "Timeout when polling for IBIWON\n"); in svc_i3c_master_ibi_work()
362 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
364 status = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
371 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); in svc_i3c_master_ibi_work()
373 svc_i3c_master_nack_ibi(master); in svc_i3c_master_ibi_work()
375 svc_i3c_master_handle_ibi(master, dev); in svc_i3c_master_ibi_work()
378 svc_i3c_master_ack_ibi(master, false); in svc_i3c_master_ibi_work()
381 svc_i3c_master_nack_ibi(master); in svc_i3c_master_ibi_work()
392 if (svc_i3c_master_error(master)) { in svc_i3c_master_ibi_work()
393 if (master->ibi.tbq_slot) { in svc_i3c_master_ibi_work()
395 i3c_generic_ibi_recycle_slot(data->ibi_pool, in svc_i3c_master_ibi_work()
396 master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
397 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
400 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
409 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
410 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
412 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
415 queue_work(master->base.wq, &master->hj_work); in svc_i3c_master_ibi_work()
423 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); in svc_i3c_master_ibi_work()
428 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; in svc_i3c_master_irq_handler() local
429 u32 active = readl(master->regs + SVC_I3C_MINTMASKED); in svc_i3c_master_irq_handler()
435 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_irq_handler()
437 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_irq_handler()
440 queue_work(master->base.wq, &master->ibi_work); in svc_i3c_master_irq_handler()
447 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_bus_init() local
456 fclk_rate = clk_get_rate(master->fclk); in svc_i3c_master_bus_init()
458 return -EINVAL; in svc_i3c_master_bus_init()
463 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. in svc_i3c_master_bus_init()
464 * Simplest configuration is using a 50% duty-cycle of 40ns. in svc_i3c_master_bus_init()
466 ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1; in svc_i3c_master_bus_init()
470 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a in svc_i3c_master_bus_init()
471 * duty-cycle tuned so that high levels are filetered out by in svc_i3c_master_bus_init()
476 odbaud = DIV_ROUND_UP(240 - high_period_ns, high_period_ns) - 1; in svc_i3c_master_bus_init()
479 switch (bus->mode) { in svc_i3c_master_bus_init()
489 i2cbaud = DIV_ROUND_UP(1000, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
496 i2cbaud = DIV_ROUND_UP(2500, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
499 return -EINVAL; in svc_i3c_master_bus_init()
512 writel(reg, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_init()
514 /* Master core's registration */ in svc_i3c_master_bus_init()
522 master->regs + SVC_I3C_MDYNADDR); in svc_i3c_master_bus_init()
524 ret = i3c_master_set_info(&master->base, &info); in svc_i3c_master_bus_init()
528 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); in svc_i3c_master_bus_init()
535 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_bus_cleanup() local
537 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_bus_cleanup()
539 /* Disable master */ in svc_i3c_master_bus_cleanup()
540 writel(0, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_cleanup()
543 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) in svc_i3c_master_reserve_slot() argument
547 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) in svc_i3c_master_reserve_slot()
548 return -ENOSPC; in svc_i3c_master_reserve_slot()
550 slot = ffs(master->free_slots) - 1; in svc_i3c_master_reserve_slot()
552 master->free_slots &= ~BIT(slot); in svc_i3c_master_reserve_slot()
557 static void svc_i3c_master_release_slot(struct svc_i3c_master *master, in svc_i3c_master_release_slot() argument
560 master->free_slots |= BIT(slot); in svc_i3c_master_release_slot()
566 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_attach_i3c_dev() local
570 slot = svc_i3c_master_reserve_slot(master); in svc_i3c_master_attach_i3c_dev()
576 svc_i3c_master_release_slot(master, slot); in svc_i3c_master_attach_i3c_dev()
577 return -ENOMEM; in svc_i3c_master_attach_i3c_dev()
580 data->ibi = -1; in svc_i3c_master_attach_i3c_dev()
581 data->index = slot; in svc_i3c_master_attach_i3c_dev()
582 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_attach_i3c_dev()
583 dev->info.static_addr; in svc_i3c_master_attach_i3c_dev()
584 master->descs[slot] = dev; in svc_i3c_master_attach_i3c_dev()
595 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_reattach_i3c_dev() local
598 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_reattach_i3c_dev()
599 dev->info.static_addr; in svc_i3c_master_reattach_i3c_dev()
608 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_detach_i3c_dev() local
610 master->addrs[data->index] = 0; in svc_i3c_master_detach_i3c_dev()
611 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i3c_dev()
619 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_attach_i2c_dev() local
623 slot = svc_i3c_master_reserve_slot(master); in svc_i3c_master_attach_i2c_dev()
629 svc_i3c_master_release_slot(master, slot); in svc_i3c_master_attach_i2c_dev()
630 return -ENOMEM; in svc_i3c_master_attach_i2c_dev()
633 data->index = slot; in svc_i3c_master_attach_i2c_dev()
634 master->addrs[slot] = dev->addr; in svc_i3c_master_attach_i2c_dev()
645 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_detach_i2c_dev() local
647 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i2c_dev()
652 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, in svc_i3c_master_readb() argument
659 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_readb()
664 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_readb()
670 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, in svc_i3c_master_do_daa_locked() argument
684 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_do_daa_locked()
690 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_do_daa_locked()
701 * We only care about the 48-bit provisional ID yet to in svc_i3c_master_do_daa_locked()
705 ret = svc_i3c_master_readb(master, data, 6); in svc_i3c_master_do_daa_locked()
710 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); in svc_i3c_master_do_daa_locked()
713 ret = svc_i3c_master_readb(master, data, 2); in svc_i3c_master_do_daa_locked()
734 return -EIO; in svc_i3c_master_do_daa_locked()
736 dev_nb--; in svc_i3c_master_do_daa_locked()
738 svc_i3c_master_emit_stop(master); in svc_i3c_master_do_daa_locked()
742 return -EIO; in svc_i3c_master_do_daa_locked()
747 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_do_daa_locked()
756 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); in svc_i3c_master_do_daa_locked()
761 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", in svc_i3c_master_do_daa_locked()
764 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_do_daa_locked()
773 static int svc_i3c_update_ibirules(struct svc_i3c_master *master) in svc_i3c_update_ibirules() argument
782 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { in svc_i3c_update_ibirules()
783 if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER) in svc_i3c_update_ibirules()
786 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { in svc_i3c_update_ibirules()
788 dev->info.dyn_addr); in svc_i3c_update_ibirules()
791 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
797 dev->info.dyn_addr); in svc_i3c_update_ibirules()
800 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
816 return -ERANGE; in svc_i3c_update_ibirules()
820 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
822 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
829 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_do_daa() local
835 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
836 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); in svc_i3c_master_do_daa()
837 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
848 /* Configure IBI auto-rules */ in svc_i3c_master_do_daa()
849 ret = svc_i3c_update_ibirules(master); in svc_i3c_master_do_daa()
851 dev_err(master->dev, "Cannot handle such a list of devices"); in svc_i3c_master_do_daa()
858 svc_i3c_master_emit_stop(master); in svc_i3c_master_do_daa()
859 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_do_daa()
864 static int svc_i3c_master_read(struct svc_i3c_master *master, in svc_i3c_master_read() argument
873 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, in svc_i3c_master_read()
882 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_read()
890 static int svc_i3c_master_write(struct svc_i3c_master *master, in svc_i3c_master_write() argument
897 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, in svc_i3c_master_write()
908 if (likely(offset < (len - 1))) in svc_i3c_master_write()
909 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_write()
911 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); in svc_i3c_master_write()
917 static int svc_i3c_master_xfer(struct svc_i3c_master *master, in svc_i3c_master_xfer() argument
931 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_xfer()
933 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
939 ret = svc_i3c_master_read(master, in, xfer_len); in svc_i3c_master_xfer()
941 ret = svc_i3c_master_write(master, out, xfer_len); in svc_i3c_master_xfer()
945 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
951 svc_i3c_master_emit_stop(master); in svc_i3c_master_xfer()
956 svc_i3c_master_emit_stop(master); in svc_i3c_master_xfer()
957 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_xfer()
963 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) in svc_i3c_master_alloc_xfer() argument
971 INIT_LIST_HEAD(&xfer->node); in svc_i3c_master_alloc_xfer()
972 xfer->ncmds = ncmds; in svc_i3c_master_alloc_xfer()
973 xfer->ret = -ETIMEDOUT; in svc_i3c_master_alloc_xfer()
983 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, in svc_i3c_master_dequeue_xfer_locked() argument
986 if (master->xferqueue.cur == xfer) in svc_i3c_master_dequeue_xfer_locked()
987 master->xferqueue.cur = NULL; in svc_i3c_master_dequeue_xfer_locked()
989 list_del_init(&xfer->node); in svc_i3c_master_dequeue_xfer_locked()
992 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, in svc_i3c_master_dequeue_xfer() argument
997 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
998 svc_i3c_master_dequeue_xfer_locked(master, xfer); in svc_i3c_master_dequeue_xfer()
999 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
1002 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) in svc_i3c_master_start_xfer_locked() argument
1004 struct svc_i3c_xfer *xfer = master->xferqueue.cur; in svc_i3c_master_start_xfer_locked()
1010 for (i = 0; i < xfer->ncmds; i++) { in svc_i3c_master_start_xfer_locked()
1011 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_start_xfer_locked()
1013 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, in svc_i3c_master_start_xfer_locked()
1014 cmd->addr, cmd->in, cmd->out, in svc_i3c_master_start_xfer_locked()
1015 cmd->len, cmd->read_len, in svc_i3c_master_start_xfer_locked()
1016 cmd->continued); in svc_i3c_master_start_xfer_locked()
1021 xfer->ret = ret; in svc_i3c_master_start_xfer_locked()
1022 complete(&xfer->comp); in svc_i3c_master_start_xfer_locked()
1025 svc_i3c_master_dequeue_xfer_locked(master, xfer); in svc_i3c_master_start_xfer_locked()
1027 xfer = list_first_entry_or_null(&master->xferqueue.list, in svc_i3c_master_start_xfer_locked()
1031 list_del_init(&xfer->node); in svc_i3c_master_start_xfer_locked()
1033 master->xferqueue.cur = xfer; in svc_i3c_master_start_xfer_locked()
1034 svc_i3c_master_start_xfer_locked(master); in svc_i3c_master_start_xfer_locked()
1037 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, in svc_i3c_master_enqueue_xfer() argument
1042 init_completion(&xfer->comp); in svc_i3c_master_enqueue_xfer()
1043 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1044 if (master->xferqueue.cur) { in svc_i3c_master_enqueue_xfer()
1045 list_add_tail(&xfer->node, &master->xferqueue.list); in svc_i3c_master_enqueue_xfer()
1047 master->xferqueue.cur = xfer; in svc_i3c_master_enqueue_xfer()
1048 svc_i3c_master_start_xfer_locked(master); in svc_i3c_master_enqueue_xfer()
1050 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1054 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, in svc_i3c_master_supports_ccc_cmd() argument
1058 return (cmd->ndests == 1); in svc_i3c_master_supports_ccc_cmd()
1061 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, in svc_i3c_master_send_bdcast_ccc_cmd() argument
1064 unsigned int xfer_len = ccc->dests[0].payload.len + 1; in svc_i3c_master_send_bdcast_ccc_cmd()
1070 xfer = svc_i3c_master_alloc_xfer(master, 1); in svc_i3c_master_send_bdcast_ccc_cmd()
1072 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1077 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1080 buf[0] = ccc->id; in svc_i3c_master_send_bdcast_ccc_cmd()
1081 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); in svc_i3c_master_send_bdcast_ccc_cmd()
1083 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_bdcast_ccc_cmd()
1085 cmd = &xfer->cmds[0]; in svc_i3c_master_send_bdcast_ccc_cmd()
1086 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_bdcast_ccc_cmd()
1087 cmd->rnw = ccc->rnw; in svc_i3c_master_send_bdcast_ccc_cmd()
1088 cmd->in = NULL; in svc_i3c_master_send_bdcast_ccc_cmd()
1089 cmd->out = buf; in svc_i3c_master_send_bdcast_ccc_cmd()
1090 cmd->len = xfer_len; in svc_i3c_master_send_bdcast_ccc_cmd()
1091 cmd->read_len = 0; in svc_i3c_master_send_bdcast_ccc_cmd()
1092 cmd->continued = false; in svc_i3c_master_send_bdcast_ccc_cmd()
1094 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_send_bdcast_ccc_cmd()
1095 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_bdcast_ccc_cmd()
1096 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_send_bdcast_ccc_cmd()
1098 ret = xfer->ret; in svc_i3c_master_send_bdcast_ccc_cmd()
1105 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, in svc_i3c_master_send_direct_ccc_cmd() argument
1108 unsigned int xfer_len = ccc->dests[0].payload.len; in svc_i3c_master_send_direct_ccc_cmd()
1109 unsigned int read_len = ccc->rnw ? xfer_len : 0; in svc_i3c_master_send_direct_ccc_cmd()
1114 xfer = svc_i3c_master_alloc_xfer(master, 2); in svc_i3c_master_send_direct_ccc_cmd()
1116 return -ENOMEM; in svc_i3c_master_send_direct_ccc_cmd()
1118 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_direct_ccc_cmd()
1121 cmd = &xfer->cmds[0]; in svc_i3c_master_send_direct_ccc_cmd()
1122 cmd->addr = I3C_BROADCAST_ADDR; in svc_i3c_master_send_direct_ccc_cmd()
1123 cmd->rnw = 0; in svc_i3c_master_send_direct_ccc_cmd()
1124 cmd->in = NULL; in svc_i3c_master_send_direct_ccc_cmd()
1125 cmd->out = &ccc->id; in svc_i3c_master_send_direct_ccc_cmd()
1126 cmd->len = 1; in svc_i3c_master_send_direct_ccc_cmd()
1127 cmd->read_len = 0; in svc_i3c_master_send_direct_ccc_cmd()
1128 cmd->continued = true; in svc_i3c_master_send_direct_ccc_cmd()
1131 cmd = &xfer->cmds[1]; in svc_i3c_master_send_direct_ccc_cmd()
1132 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_direct_ccc_cmd()
1133 cmd->rnw = ccc->rnw; in svc_i3c_master_send_direct_ccc_cmd()
1134 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; in svc_i3c_master_send_direct_ccc_cmd()
1135 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data, in svc_i3c_master_send_direct_ccc_cmd()
1136 cmd->len = xfer_len; in svc_i3c_master_send_direct_ccc_cmd()
1137 cmd->read_len = read_len; in svc_i3c_master_send_direct_ccc_cmd()
1138 cmd->continued = false; in svc_i3c_master_send_direct_ccc_cmd()
1140 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_send_direct_ccc_cmd()
1141 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_direct_ccc_cmd()
1142 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_send_direct_ccc_cmd()
1144 ret = xfer->ret; in svc_i3c_master_send_direct_ccc_cmd()
1153 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_send_ccc_cmd() local
1154 bool broadcast = cmd->id < 0x80; in svc_i3c_master_send_ccc_cmd()
1157 return svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); in svc_i3c_master_send_ccc_cmd()
1159 return svc_i3c_master_send_direct_ccc_cmd(master, cmd); in svc_i3c_master_send_ccc_cmd()
1167 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_priv_xfers() local
1172 xfer = svc_i3c_master_alloc_xfer(master, nxfers); in svc_i3c_master_priv_xfers()
1174 return -ENOMEM; in svc_i3c_master_priv_xfers()
1176 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_priv_xfers()
1179 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_priv_xfers()
1181 cmd->addr = master->addrs[data->index]; in svc_i3c_master_priv_xfers()
1182 cmd->rnw = xfers[i].rnw; in svc_i3c_master_priv_xfers()
1183 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL; in svc_i3c_master_priv_xfers()
1184 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out; in svc_i3c_master_priv_xfers()
1185 cmd->len = xfers[i].len; in svc_i3c_master_priv_xfers()
1186 cmd->read_len = xfers[i].rnw ? xfers[i].len : 0; in svc_i3c_master_priv_xfers()
1187 cmd->continued = (i + 1) < nxfers; in svc_i3c_master_priv_xfers()
1190 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_priv_xfers()
1191 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_priv_xfers()
1192 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_priv_xfers()
1194 ret = xfer->ret; in svc_i3c_master_priv_xfers()
1205 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_i2c_xfers() local
1210 xfer = svc_i3c_master_alloc_xfer(master, nxfers); in svc_i3c_master_i2c_xfers()
1212 return -ENOMEM; in svc_i3c_master_i2c_xfers()
1214 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; in svc_i3c_master_i2c_xfers()
1217 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_i2c_xfers()
1219 cmd->addr = master->addrs[data->index]; in svc_i3c_master_i2c_xfers()
1220 cmd->rnw = xfers[i].flags & I2C_M_RD; in svc_i3c_master_i2c_xfers()
1221 cmd->in = cmd->rnw ? xfers[i].buf : NULL; in svc_i3c_master_i2c_xfers()
1222 cmd->out = cmd->rnw ? NULL : xfers[i].buf; in svc_i3c_master_i2c_xfers()
1223 cmd->len = xfers[i].len; in svc_i3c_master_i2c_xfers()
1224 cmd->read_len = cmd->rnw ? xfers[i].len : 0; in svc_i3c_master_i2c_xfers()
1225 cmd->continued = (i + 1 < nxfers); in svc_i3c_master_i2c_xfers()
1228 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_i2c_xfers()
1229 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_i2c_xfers()
1230 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_i2c_xfers()
1232 ret = xfer->ret; in svc_i3c_master_i2c_xfers()
1242 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_request_ibi() local
1247 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { in svc_i3c_master_request_ibi()
1248 dev_err(master->dev, "IBI max payload %d should be < %d\n", in svc_i3c_master_request_ibi()
1249 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); in svc_i3c_master_request_ibi()
1250 return -ERANGE; in svc_i3c_master_request_ibi()
1253 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); in svc_i3c_master_request_ibi()
1254 if (IS_ERR(data->ibi_pool)) in svc_i3c_master_request_ibi()
1255 return PTR_ERR(data->ibi_pool); in svc_i3c_master_request_ibi()
1257 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1258 for (i = 0; i < master->ibi.num_slots; i++) { in svc_i3c_master_request_ibi()
1259 if (!master->ibi.slots[i]) { in svc_i3c_master_request_ibi()
1260 data->ibi = i; in svc_i3c_master_request_ibi()
1261 master->ibi.slots[i] = dev; in svc_i3c_master_request_ibi()
1265 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1267 if (i < master->ibi.num_slots) in svc_i3c_master_request_ibi()
1270 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_request_ibi()
1271 data->ibi_pool = NULL; in svc_i3c_master_request_ibi()
1273 return -ENOSPC; in svc_i3c_master_request_ibi()
1279 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_free_ibi() local
1283 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1284 master->ibi.slots[data->ibi] = NULL; in svc_i3c_master_free_ibi()
1285 data->ibi = -1; in svc_i3c_master_free_ibi()
1286 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1288 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_free_ibi()
1295 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_enable_ibi()
1302 return i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_disable_ibi()
1310 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); in svc_i3c_master_recycle_ibi_slot()
1333 static void svc_i3c_master_reset(struct svc_i3c_master *master) in svc_i3c_master_reset() argument
1338 writel(readl(master->regs + SVC_I3C_MERRWARN), in svc_i3c_master_reset()
1339 master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_reset()
1347 writel(reg, master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_reset()
1349 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_reset()
1354 struct device *dev = &pdev->dev; in svc_i3c_master_probe()
1355 struct svc_i3c_master *master; in svc_i3c_master_probe() local
1358 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); in svc_i3c_master_probe()
1359 if (!master) in svc_i3c_master_probe()
1360 return -ENOMEM; in svc_i3c_master_probe()
1362 master->regs = devm_platform_ioremap_resource(pdev, 0); in svc_i3c_master_probe()
1363 if (IS_ERR(master->regs)) in svc_i3c_master_probe()
1364 return PTR_ERR(master->regs); in svc_i3c_master_probe()
1366 master->pclk = devm_clk_get(dev, "pclk"); in svc_i3c_master_probe()
1367 if (IS_ERR(master->pclk)) in svc_i3c_master_probe()
1368 return PTR_ERR(master->pclk); in svc_i3c_master_probe()
1370 master->fclk = devm_clk_get(dev, "fast_clk"); in svc_i3c_master_probe()
1371 if (IS_ERR(master->fclk)) in svc_i3c_master_probe()
1372 return PTR_ERR(master->fclk); in svc_i3c_master_probe()
1374 master->sclk = devm_clk_get(dev, "slow_clk"); in svc_i3c_master_probe()
1375 if (IS_ERR(master->sclk)) in svc_i3c_master_probe()
1376 return PTR_ERR(master->sclk); in svc_i3c_master_probe()
1378 master->irq = platform_get_irq(pdev, 0); in svc_i3c_master_probe()
1379 if (master->irq <= 0) in svc_i3c_master_probe()
1380 return -ENOENT; in svc_i3c_master_probe()
1382 master->dev = dev; in svc_i3c_master_probe()
1384 svc_i3c_master_reset(master); in svc_i3c_master_probe()
1386 ret = clk_prepare_enable(master->pclk); in svc_i3c_master_probe()
1390 ret = clk_prepare_enable(master->fclk); in svc_i3c_master_probe()
1394 ret = clk_prepare_enable(master->sclk); in svc_i3c_master_probe()
1398 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work); in svc_i3c_master_probe()
1399 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work); in svc_i3c_master_probe()
1400 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, in svc_i3c_master_probe()
1401 IRQF_NO_SUSPEND, "svc-i3c-irq", master); in svc_i3c_master_probe()
1405 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); in svc_i3c_master_probe()
1407 spin_lock_init(&master->xferqueue.lock); in svc_i3c_master_probe()
1408 INIT_LIST_HEAD(&master->xferqueue.list); in svc_i3c_master_probe()
1410 spin_lock_init(&master->ibi.lock); in svc_i3c_master_probe()
1411 master->ibi.num_slots = SVC_I3C_MAX_DEVS; in svc_i3c_master_probe()
1412 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, in svc_i3c_master_probe()
1413 sizeof(*master->ibi.slots), in svc_i3c_master_probe()
1415 if (!master->ibi.slots) { in svc_i3c_master_probe()
1416 ret = -ENOMEM; in svc_i3c_master_probe()
1420 platform_set_drvdata(pdev, master); in svc_i3c_master_probe()
1422 /* Register the master */ in svc_i3c_master_probe()
1423 ret = i3c_master_register(&master->base, &pdev->dev, in svc_i3c_master_probe()
1431 clk_disable_unprepare(master->sclk); in svc_i3c_master_probe()
1434 clk_disable_unprepare(master->fclk); in svc_i3c_master_probe()
1437 clk_disable_unprepare(master->pclk); in svc_i3c_master_probe()
1444 struct svc_i3c_master *master = platform_get_drvdata(pdev); in svc_i3c_master_remove() local
1447 ret = i3c_master_unregister(&master->base); in svc_i3c_master_remove()
1451 clk_disable_unprepare(master->pclk); in svc_i3c_master_remove()
1452 clk_disable_unprepare(master->fclk); in svc_i3c_master_remove()
1453 clk_disable_unprepare(master->sclk); in svc_i3c_master_remove()
1459 { .compatible = "silvaco,i3c-master" },
1467 .name = "silvaco-i3c-master",
1475 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");