Lines Matching refs:enabled_irqs
136 u32 enabled_irqs; member
204 pio->enabled_irqs = STAT_ALL_ERRORS; in hci_pio_init()
379 pio->enabled_irqs |= STAT_RX_THLD; in hci_pio_queue_data()
389 pio->enabled_irqs |= STAT_TX_THLD; in hci_pio_queue_data()
516 pio->enabled_irqs &= ~STAT_RX_THLD; in hci_pio_process_resp()
557 pio->enabled_irqs |= STAT_RESP_READY; in hci_pio_queue_resp()
612 pio->enabled_irqs |= STAT_CMD_QUEUE_READY; in hci_pio_queue_xfer()
613 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); in hci_pio_queue_xfer()
989 DBG("(in) status: %#x/%#x", status, pio->enabled_irqs); in hci_pio_irq_handler()
990 status &= pio->enabled_irqs | STAT_LATENCY_WARNINGS; in hci_pio_irq_handler()
1001 pio->enabled_irqs &= ~STAT_RX_THLD; in hci_pio_irq_handler()
1004 pio->enabled_irqs &= ~STAT_TX_THLD; in hci_pio_irq_handler()
1007 pio->enabled_irqs &= ~STAT_RESP_READY; in hci_pio_irq_handler()
1023 pio->enabled_irqs &= ~STAT_CMD_QUEUE_READY; in hci_pio_irq_handler()
1025 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); in hci_pio_irq_handler()