1 // SPDX-License-Identifier: GPL-2.0-only
3  * i2c-xiic.c
4  * Copyright (c) 2002-2007 Xilinx Inc.
5  * Copyright (c) 2009-2010 Intel Corporation
25 #include <linux/interrupt.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48  * struct xiic_i2c - Internal representation of the XIIC I2C bus
50  * @base: Memory base of the HW registers
59  * @endianness: big/little-endian byte order
60  * @clk: Pointer to AXI4-lite input clock
66 	void __iomem *base;  member
87  * base offset to access LSB (IBM style) of the word
113 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08	/* 1=Dir: mstr <-- slave  */
119 /* Interrupt Status Register masks    Interrupt occurs when...       */
148  * The following constants define the register offsets for the Interrupt
151  * interrupt controller registers
153 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
154 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
155 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
164  * The following constant is used for the device global interrupt enable
170 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
171 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
177  * For the register read and write functions, a little-endian and big-endian
180  * accessed. This requires an offset of 3 [2] from the base address for
181  * big-endian systems.
186 	if (i2c->endianness == LITTLE)  in xiic_setreg8()
187 		iowrite8(value, i2c->base + reg);  in xiic_setreg8()
189 		iowrite8(value, i2c->base + reg + 3);  in xiic_setreg8()
196 	if (i2c->endianness == LITTLE)  in xiic_getreg8()
197 		ret = ioread8(i2c->base + reg);  in xiic_getreg8()
199 		ret = ioread8(i2c->base + reg + 3);  in xiic_getreg8()
205 	if (i2c->endianness == LITTLE)  in xiic_setreg16()
206 		iowrite16(value, i2c->base + reg);  in xiic_setreg16()
208 		iowrite16be(value, i2c->base + reg + 2);  in xiic_setreg16()
213 	if (i2c->endianness == LITTLE)  in xiic_setreg32()
214 		iowrite32(value, i2c->base + reg);  in xiic_setreg32()
216 		iowrite32be(value, i2c->base + reg);  in xiic_setreg32()
223 	if (i2c->endianness == LITTLE)  in xiic_getreg32()
224 		ret = ioread32(i2c->base + reg);  in xiic_getreg32()
226 		ret = ioread32be(i2c->base + reg);  in xiic_getreg32()
265 			dev_err(i2c->dev, "Failed to clear rx fifo\n");  in xiic_clear_rx_fifo()
266 			return -ETIMEDOUT;  in xiic_clear_rx_fifo()
280 	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);  in xiic_reinit()
319 	dev_dbg(i2c->adap.dev.parent,  in xiic_read_rx()
329 		i2c->rx_msg->buf[i2c->rx_pos++] =  in xiic_read_rx()
334 		IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);  in xiic_read_rx()
340 	return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;  in xiic_tx_fifo_space()
350 	dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",  in xiic_fill_tx_fifo()
353 	while (len--) {  in xiic_fill_tx_fifo()
354 		u16 data = i2c->tx_msg->buf[i2c->tx_pos++];  in xiic_fill_tx_fifo()
355 		if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {  in xiic_fill_tx_fifo()
356 			/* last message in transfer -> STOP */  in xiic_fill_tx_fifo()
358 			dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);  in xiic_fill_tx_fifo()
366 	i2c->tx_msg = NULL;  in xiic_wakeup()
367 	i2c->rx_msg = NULL;  in xiic_wakeup()
368 	i2c->nmsgs = 0;  in xiic_wakeup()
369 	i2c->state = code;  in xiic_wakeup()
370 	wake_up(&i2c->wait);  in xiic_wakeup()
379 	/* Get the interrupt Status from the IPIF. There is no clearing of  in xiic_process()
384 	mutex_lock(&i2c->lock);  in xiic_process()
389 	dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",  in xiic_process()
391 	dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",  in xiic_process()
393 		i2c->tx_msg, i2c->nmsgs);  in xiic_process()
396 	/* Service requesting interrupt */  in xiic_process()
406 		dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);  in xiic_process()
414 		if (i2c->rx_msg)  in xiic_process()
416 		if (i2c->tx_msg)  in xiic_process()
423 		if (!i2c->rx_msg) {  in xiic_process()
424 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
433 			i2c->rx_msg = NULL;  in xiic_process()
438 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
440 				__func__, i2c->nmsgs);  in xiic_process()
444 			 * receiving the bus not busy interrupt  in xiic_process()
446 			if (i2c->nmsgs > 1) {  in xiic_process()
447 				i2c->nmsgs--;  in xiic_process()
448 				i2c->tx_msg++;  in xiic_process()
449 				dev_dbg(i2c->adap.dev.parent,  in xiic_process()
460 		/* The bus is not busy, disable BusNotBusy interrupt */  in xiic_process()
463 		if (!i2c->tx_msg)  in xiic_process()
466 		if ((i2c->nmsgs == 1) && !i2c->rx_msg &&  in xiic_process()
478 		if (!i2c->tx_msg) {  in xiic_process()
479 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
488 			dev_dbg(i2c->adap.dev.parent,  in xiic_process()
490 				__func__, i2c->nmsgs);  in xiic_process()
491 			if (i2c->nmsgs > 1) {  in xiic_process()
492 				i2c->nmsgs--;  in xiic_process()
493 				i2c->tx_msg++;  in xiic_process()
498 				dev_dbg(i2c->adap.dev.parent,  in xiic_process()
502 		} else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))  in xiic_process()
509 	dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);  in xiic_process()
512 	mutex_unlock(&i2c->lock);  in xiic_process()
520 	return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;  in xiic_bus_busy()
528 	if (i2c->tx_msg)  in xiic_busy()
529 		return -EBUSY;  in xiic_busy()
536 	if (i2c->singlemaster) {  in xiic_busy()
545 	while (err && tries--) {  in xiic_busy()
556 	struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;  in xiic_start_recv()
559 	/* Clear and enable Rx full interrupt. */  in xiic_start_recv()
568 	rx_watermark = msg->len;  in xiic_start_recv()
571 	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);  in xiic_start_recv()
574 	if (!(msg->flags & I2C_M_NOSTART))  in xiic_start_recv()
582 		msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));  in xiic_start_recv()
585 	if (i2c->nmsgs == 1)  in xiic_start_recv()
590 	i2c->tx_pos = msg->len;  in xiic_start_recv()
595 	struct i2c_msg *msg = i2c->tx_msg;  in xiic_start_send()
599 	dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",  in xiic_start_send()
600 		__func__, msg, msg->len);  in xiic_start_send()
601 	dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",  in xiic_start_send()
605 	if (!(msg->flags & I2C_M_NOSTART)) {  in xiic_start_send()
609 		if ((i2c->nmsgs == 1) && msg->len == 0)  in xiic_start_send()
610 			/* no data and last message -> add STOP */  in xiic_start_send()
632 	dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);  in xiic_isr()
647 	dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",  in __xiic_start_xfer()
648 		__func__, i2c->tx_msg, fifo_space);  in __xiic_start_xfer()
650 	if (!i2c->tx_msg)  in __xiic_start_xfer()
653 	i2c->rx_pos = 0;  in __xiic_start_xfer()
654 	i2c->tx_pos = 0;  in __xiic_start_xfer()
655 	i2c->state = STATE_START;  in __xiic_start_xfer()
656 	while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {  in __xiic_start_xfer()
658 			i2c->nmsgs--;  in __xiic_start_xfer()
659 			i2c->tx_msg++;  in __xiic_start_xfer()
660 			i2c->tx_pos = 0;  in __xiic_start_xfer()
664 		if (i2c->tx_msg->flags & I2C_M_RD) {  in __xiic_start_xfer()
680 	 * put into the FIFO, also enable the half empty interrupt  in __xiic_start_xfer()
682 	if (i2c->nmsgs > 1 || xiic_tx_space(i2c))  in __xiic_start_xfer()
690 	mutex_lock(&i2c->lock);  in xiic_start_xfer()
696 	mutex_unlock(&i2c->lock);  in xiic_start_xfer()
706 	dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,  in xiic_xfer()
709 	err = pm_runtime_resume_and_get(i2c->dev);  in xiic_xfer()
717 	i2c->tx_msg = msgs;  in xiic_xfer()
718 	i2c->nmsgs = num;  in xiic_xfer()
722 		dev_err(adap->dev.parent, "Error xiic_start_xfer\n");  in xiic_xfer()
726 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||  in xiic_xfer()
727 		(i2c->state == STATE_DONE), HZ)) {  in xiic_xfer()
728 		err = (i2c->state == STATE_DONE) ? num : -EIO;  in xiic_xfer()
731 		i2c->tx_msg = NULL;  in xiic_xfer()
732 		i2c->rx_msg = NULL;  in xiic_xfer()
733 		i2c->nmsgs = 0;  in xiic_xfer()
734 		err = -ETIMEDOUT;  in xiic_xfer()
738 	pm_runtime_mark_last_busy(i2c->dev);  in xiic_xfer()
739 	pm_runtime_put_autosuspend(i2c->dev);  in xiic_xfer()
775 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);  in xiic_i2c_probe()
777 		return -ENOMEM;  in xiic_i2c_probe()
780 	i2c->base = devm_ioremap_resource(&pdev->dev, res);  in xiic_i2c_probe()
781 	if (IS_ERR(i2c->base))  in xiic_i2c_probe()
782 		return PTR_ERR(i2c->base);  in xiic_i2c_probe()
788 	pdata = dev_get_platdata(&pdev->dev);  in xiic_i2c_probe()
792 	i2c->adap = xiic_adapter;  in xiic_i2c_probe()
793 	i2c_set_adapdata(&i2c->adap, i2c);  in xiic_i2c_probe()
794 	i2c->adap.dev.parent = &pdev->dev;  in xiic_i2c_probe()
795 	i2c->adap.dev.of_node = pdev->dev.of_node;  in xiic_i2c_probe()
797 	mutex_init(&i2c->lock);  in xiic_i2c_probe()
798 	init_waitqueue_head(&i2c->wait);  in xiic_i2c_probe()
800 	i2c->clk = devm_clk_get(&pdev->dev, NULL);  in xiic_i2c_probe()
801 	if (IS_ERR(i2c->clk))  in xiic_i2c_probe()
802 		return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),  in xiic_i2c_probe()
805 	ret = clk_prepare_enable(i2c->clk);  in xiic_i2c_probe()
807 		dev_err(&pdev->dev, "Unable to enable clock.\n");  in xiic_i2c_probe()
810 	i2c->dev = &pdev->dev;  in xiic_i2c_probe()
811 	pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);  in xiic_i2c_probe()
812 	pm_runtime_use_autosuspend(i2c->dev);  in xiic_i2c_probe()
813 	pm_runtime_set_active(i2c->dev);  in xiic_i2c_probe()
814 	pm_runtime_enable(i2c->dev);  in xiic_i2c_probe()
815 	ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,  in xiic_i2c_probe()
817 					pdev->name, i2c);  in xiic_i2c_probe()
820 		dev_err(&pdev->dev, "Cannot claim IRQ\n");  in xiic_i2c_probe()
824 	i2c->singlemaster =  in xiic_i2c_probe()
825 		of_property_read_bool(pdev->dev.of_node, "single-master");  in xiic_i2c_probe()
832 	i2c->endianness = LITTLE;  in xiic_i2c_probe()
837 		i2c->endianness = BIG;  in xiic_i2c_probe()
841 		dev_err(&pdev->dev, "Cannot xiic_reinit\n");  in xiic_i2c_probe()
846 	ret = i2c_add_adapter(&i2c->adap);  in xiic_i2c_probe()
854 		for (i = 0; i < pdata->num_devices; i++)  in xiic_i2c_probe()
855 			i2c_new_client_device(&i2c->adap, pdata->devices + i);  in xiic_i2c_probe()
861 	pm_runtime_set_suspended(&pdev->dev);  in xiic_i2c_probe()
862 	pm_runtime_disable(&pdev->dev);  in xiic_i2c_probe()
863 	clk_disable_unprepare(i2c->clk);  in xiic_i2c_probe()
873 	i2c_del_adapter(&i2c->adap);  in xiic_i2c_remove()
875 	ret = pm_runtime_resume_and_get(i2c->dev);  in xiic_i2c_remove()
880 	pm_runtime_put_sync(i2c->dev);  in xiic_i2c_remove()
881 	clk_disable_unprepare(i2c->clk);  in xiic_i2c_remove()
882 	pm_runtime_disable(&pdev->dev);  in xiic_i2c_remove()
883 	pm_runtime_set_suspended(&pdev->dev);  in xiic_i2c_remove()
884 	pm_runtime_dont_use_autosuspend(&pdev->dev);  in xiic_i2c_remove()
891 	{ .compatible = "xlnx,xps-iic-2.00.a", },
901 	clk_disable(i2c->clk);  in xiic_i2c_runtime_suspend()
911 	ret = clk_enable(i2c->clk);  in xiic_i2c_runtime_resume()
936 MODULE_AUTHOR("info@mocean-labs.com");