42 #define STM32F7_I2C_CR2				0x04  macro
795 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
805 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
825 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
828 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
885 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
953 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
969 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1119 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1131 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1203 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1283 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1301 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1447 			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1449 			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1452 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_isr_event()
1548 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_isr_event()
1883 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);  in stm32f7_i2c_reg_slave()
2357 	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_backup()
2389 	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_restore()