41 #define STM32F7_I2C_CR1				0x00  macro
425 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_irq()
717 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_dma_req()
746 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
749 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
753 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
755 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
758 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
837 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_release_bus()
884 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
952 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
970 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1118 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1132 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1202 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1286 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1291 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1311 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1804 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1807 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1888 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_reg_slave()
1999 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);  in stm32f7_i2c_enable_smbus_host()
2010 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_host()
2034 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);  in stm32f7_i2c_enable_smbus_alert()
2046 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_alert()
2356 	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_backup()
2378 	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2380 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()
2385 		       i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2387 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()