Lines Matching +full:stm32mp15 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
14 * This driver is based on i2c-stm32f4.c
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
52 /* STM32F7 I2C control 1 */
83 /* STM32F7 I2C control 2 */
100 /* STM32F7 I2C Own Address 1 */
113 /* STM32F7 I2C Own Address 2 */
123 /* STM32F7 I2C Interrupt Status */
142 /* STM32F7 I2C Interrupt Clear */
151 /* STM32F7 I2C Timing */
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
201 * struct stm32f7_i2c_spec - private i2c specification timing
202 * @rate: I2C bus speed (Hz)
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
224 * @speed_freq: I2C speed frequency (Hz)
225 * @clock_src: I2C clock source frequency (Hz)
239 * struct stm32f7_i2c_timings - private I2C output parameters
257 * struct stm32f7_i2c_msg - client specific data
258 * @addr: 8-bit or 10-bit slave addr, including r/w bit
262 * @stop: last I2C msg to be sent, i.e. STOP to be generated
263 * @smbus: boolean to know if the I2C IP is used in SMBus mode
266 * SMBus block read and SMBus block write - block read process call protocols
269 * This buffer has to be 32-bit aligned to be compliant with memory address
285 * struct stm32f7_i2c_alert - SMBus alert specific data
286 * @setup: platform data for the smbus_alert i2c client
287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
296 * struct stm32f7_i2c_dev - private data of the controller
297 * @adap: I2C adapter for this controller
300 * @complete: completion of I2C message
301 * @clk: hw i2c clock
302 * @bus_rate: I2C clock frequency of the controller
304 * @msg_num: number of I2C messages to be executed
306 * @f7_msg: customized i2c msg for driver usage
307 * @setup: I2C timing input setup
308 * @timing: I2C computed timings
309 * @slave: list of slave devices registered on the I2C bus
311 * @backup_regs: backup of i2c controller registers (for suspend/resume)
313 * @master_mode: boolean to know in which mode the I2C is running (master or
323 * @host_notify_client: SMBus host-notify client
363 * All these values are coming from I2C Specification, Version 6.0, 4th of
367 * and Fast-mode Plus I2C-bus devices
425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
436 return ERR_PTR(-EINVAL); in stm32f7_get_specs()
447 setup->clock_src); in stm32f7_i2c_compute_timing()
449 setup->speed_freq); in stm32f7_i2c_compute_timing()
462 specs = stm32f7_get_specs(setup->speed_freq); in stm32f7_i2c_compute_timing()
463 if (specs == ERR_PTR(-EINVAL)) { in stm32f7_i2c_compute_timing()
464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", in stm32f7_i2c_compute_timing()
465 setup->speed_freq); in stm32f7_i2c_compute_timing()
466 return -EINVAL; in stm32f7_i2c_compute_timing()
469 if ((setup->rise_time > specs->rise_max) || in stm32f7_i2c_compute_timing()
470 (setup->fall_time > specs->fall_max)) { in stm32f7_i2c_compute_timing()
471 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
473 setup->rise_time, specs->rise_max, in stm32f7_i2c_compute_timing()
474 setup->fall_time, specs->fall_max); in stm32f7_i2c_compute_timing()
475 return -EINVAL; in stm32f7_i2c_compute_timing()
478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); in stm32f7_i2c_compute_timing()
479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { in stm32f7_i2c_compute_timing()
480 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); in stm32f7_i2c_compute_timing()
483 return -EINVAL; in stm32f7_i2c_compute_timing()
488 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
491 (i2c_dev->analog_filter ? in stm32f7_i2c_compute_timing()
493 dnf_delay = i2c_dev->dnf * i2cclk; in stm32f7_i2c_compute_timing()
495 sdadel_min = specs->hddat_min + setup->fall_time - in stm32f7_i2c_compute_timing()
496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; in stm32f7_i2c_compute_timing()
498 sdadel_max = specs->vddat_max - setup->rise_time - in stm32f7_i2c_compute_timing()
499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; in stm32f7_i2c_compute_timing()
501 scldel_min = setup->rise_time + specs->sudat_min; in stm32f7_i2c_compute_timing()
508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", in stm32f7_i2c_compute_timing()
528 ret = -ENOMEM; in stm32f7_i2c_compute_timing()
532 v->presc = p; in stm32f7_i2c_compute_timing()
533 v->scldel = l; in stm32f7_i2c_compute_timing()
534 v->sdadel = a; in stm32f7_i2c_compute_timing()
537 list_add_tail(&v->node, in stm32f7_i2c_compute_timing()
549 dev_err(i2c_dev->dev, "no Prescaler solution\n"); in stm32f7_i2c_compute_timing()
550 ret = -EPERM; in stm32f7_i2c_compute_timing()
556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); in stm32f7_i2c_compute_timing()
557 clk_min = NSEC_PER_SEC / setup->speed_freq; in stm32f7_i2c_compute_timing()
562 * - SCL Low Period has to be higher than SCL Clock Low Period in stm32f7_i2c_compute_timing()
563 * defined by I2C Specification. I2C Clock has to be lower than in stm32f7_i2c_compute_timing()
564 * (SCL Low Period - Analog/Digital filters) / 4. in stm32f7_i2c_compute_timing()
565 * - SCL High Period has to be lower than SCL Clock High Period in stm32f7_i2c_compute_timing()
566 * defined by I2C Specification in stm32f7_i2c_compute_timing()
567 * - I2C Clock has to be lower than SCL High Period in stm32f7_i2c_compute_timing()
570 u32 prescaler = (v->presc + 1) * i2cclk; in stm32f7_i2c_compute_timing()
575 if ((tscl_l < specs->l_min) || in stm32f7_i2c_compute_timing()
577 ((tscl_l - af_delay_min - dnf_delay) / 4))) { in stm32f7_i2c_compute_timing()
584 setup->rise_time + setup->fall_time; in stm32f7_i2c_compute_timing()
587 (tscl_h >= specs->h_min) && in stm32f7_i2c_compute_timing()
589 int clk_error = tscl - i2cbus; in stm32f7_i2c_compute_timing()
592 clk_error = -clk_error; in stm32f7_i2c_compute_timing()
596 v->scll = l; in stm32f7_i2c_compute_timing()
597 v->sclh = h; in stm32f7_i2c_compute_timing()
606 dev_err(i2c_dev->dev, "no solution at all\n"); in stm32f7_i2c_compute_timing()
607 ret = -EPERM; in stm32f7_i2c_compute_timing()
611 output->presc = s->presc; in stm32f7_i2c_compute_timing()
612 output->scldel = s->scldel; in stm32f7_i2c_compute_timing()
613 output->sdadel = s->sdadel; in stm32f7_i2c_compute_timing()
614 output->scll = s->scll; in stm32f7_i2c_compute_timing()
615 output->sclh = s->sclh; in stm32f7_i2c_compute_timing()
617 dev_dbg(i2c_dev->dev, in stm32f7_i2c_compute_timing()
619 output->presc, in stm32f7_i2c_compute_timing()
620 output->scldel, output->sdadel, in stm32f7_i2c_compute_timing()
621 output->scll, output->sclh); in stm32f7_i2c_compute_timing()
626 list_del(&v->node); in stm32f7_i2c_compute_timing()
637 while (--i) in stm32f7_get_lower_rate()
650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in stm32f7_i2c_setup_timing()
651 t->scl_rise_ns = i2c_dev->setup.rise_time; in stm32f7_i2c_setup_timing()
652 t->scl_fall_ns = i2c_dev->setup.fall_time; in stm32f7_i2c_setup_timing()
654 i2c_parse_fw_timings(i2c_dev->dev, t, false); in stm32f7_i2c_setup_timing()
656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { in stm32f7_i2c_setup_timing()
657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", in stm32f7_i2c_setup_timing()
658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); in stm32f7_i2c_setup_timing()
659 return -EINVAL; in stm32f7_i2c_setup_timing()
662 setup->speed_freq = t->bus_freq_hz; in stm32f7_i2c_setup_timing()
663 i2c_dev->setup.rise_time = t->scl_rise_ns; in stm32f7_i2c_setup_timing()
664 i2c_dev->setup.fall_time = t->scl_fall_ns; in stm32f7_i2c_setup_timing()
665 i2c_dev->dnf_dt = t->digital_filter_width_ns; in stm32f7_i2c_setup_timing()
666 setup->clock_src = clk_get_rate(i2c_dev->clk); in stm32f7_i2c_setup_timing()
668 if (!setup->clock_src) { in stm32f7_i2c_setup_timing()
669 dev_err(i2c_dev->dev, "clock rate is 0\n"); in stm32f7_i2c_setup_timing()
670 return -EINVAL; in stm32f7_i2c_setup_timing()
673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) in stm32f7_i2c_setup_timing()
674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; in stm32f7_i2c_setup_timing()
678 &i2c_dev->timing); in stm32f7_i2c_setup_timing()
680 dev_err(i2c_dev->dev, in stm32f7_i2c_setup_timing()
681 "failed to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) in stm32f7_i2c_setup_timing()
684 setup->speed_freq = in stm32f7_i2c_setup_timing()
685 stm32f7_get_lower_rate(setup->speed_freq); in stm32f7_i2c_setup_timing()
686 dev_warn(i2c_dev->dev, in stm32f7_i2c_setup_timing()
687 "downgrade I2C Speed Freq to (%i)\n", in stm32f7_i2c_setup_timing()
688 setup->speed_freq); in stm32f7_i2c_setup_timing()
693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, in stm32f7_i2c_setup_timing()
698 "i2c-analog-filter"); in stm32f7_i2c_setup_timing()
700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", in stm32f7_i2c_setup_timing()
701 setup->speed_freq, setup->clock_src); in stm32f7_i2c_setup_timing()
702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", in stm32f7_i2c_setup_timing()
703 setup->rise_time, setup->fall_time); in stm32f7_i2c_setup_timing()
704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", in stm32f7_i2c_setup_timing()
705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); in stm32f7_i2c_setup_timing()
707 i2c_dev->bus_rate = setup->speed_freq; in stm32f7_i2c_setup_timing()
714 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_dma_req()
723 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_dma_callback()
724 struct device *dev = dma->chan_using->device->dev; in stm32f7_i2c_dma_callback()
727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); in stm32f7_i2c_dma_callback()
728 complete(&dma->dma_complete); in stm32f7_i2c_dma_callback()
733 struct stm32f7_i2c_timings *t = &i2c_dev->timing; in stm32f7_i2c_hw_config()
737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); in stm32f7_i2c_hw_config()
738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); in stm32f7_i2c_hw_config()
739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); in stm32f7_i2c_hw_config()
740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); in stm32f7_i2c_hw_config()
741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); in stm32f7_i2c_hw_config()
742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_hw_config()
745 if (i2c_dev->analog_filter) in stm32f7_i2c_hw_config()
746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); in stm32f7_i2c_hw_config()
758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_write_tx_data()
765 void __iomem *base = i2c_dev->base; in stm32f7_i2c_write_tx_data()
767 if (f7_msg->count) { in stm32f7_i2c_write_tx_data()
768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); in stm32f7_i2c_write_tx_data()
769 f7_msg->count--; in stm32f7_i2c_write_tx_data()
775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_read_rx_data()
776 void __iomem *base = i2c_dev->base; in stm32f7_i2c_read_rx_data()
778 if (f7_msg->count) { in stm32f7_i2c_read_rx_data()
779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); in stm32f7_i2c_read_rx_data()
780 f7_msg->count--; in stm32f7_i2c_read_rx_data()
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_reload()
792 if (i2c_dev->use_dma) in stm32f7_i2c_reload()
793 f7_msg->count -= STM32F7_I2C_MAX_LEN; in stm32f7_i2c_reload()
795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_reload()
802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_reload()
805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_reload()
823 val = f7_msg->buf - sizeof(u8); in stm32f7_i2c_smbus_reload()
824 f7_msg->count = *val; in stm32f7_i2c_smbus_reload()
825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_reload()
828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
835 dev_info(i2c_dev->dev, "Trying to recover bus\n"); in stm32f7_i2c_release_bus()
837 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
850 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, in stm32f7_i2c_wait_free_bus()
857 dev_info(i2c_dev->dev, "bus busy\n"); in stm32f7_i2c_wait_free_bus()
859 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_wait_free_bus()
861 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); in stm32f7_i2c_wait_free_bus()
865 return -EBUSY; in stm32f7_i2c_wait_free_bus()
871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer_msg()
872 void __iomem *base = i2c_dev->base; in stm32f7_i2c_xfer_msg()
876 f7_msg->addr = msg->addr; in stm32f7_i2c_xfer_msg()
877 f7_msg->buf = msg->buf; in stm32f7_i2c_xfer_msg()
878 f7_msg->count = msg->len; in stm32f7_i2c_xfer_msg()
879 f7_msg->result = 0; in stm32f7_i2c_xfer_msg()
880 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); in stm32f7_i2c_xfer_msg()
882 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_xfer_msg()
889 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
894 if (msg->flags & I2C_M_TEN) { in stm32f7_i2c_xfer_msg()
896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); in stm32f7_i2c_xfer_msg()
900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_xfer_msg()
905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_xfer_msg()
909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_xfer_msg()
921 i2c_dev->use_dma = false; in stm32f7_i2c_xfer_msg()
922 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_xfer_msg()
923 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_xfer_msg()
924 msg->flags & I2C_M_RD, in stm32f7_i2c_xfer_msg()
925 f7_msg->count, f7_msg->buf, in stm32f7_i2c_xfer_msg()
929 i2c_dev->use_dma = true; in stm32f7_i2c_xfer_msg()
931 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_xfer_msg()
934 if (!i2c_dev->use_dma) { in stm32f7_i2c_xfer_msg()
935 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
940 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
949 i2c_dev->master_mode = true; in stm32f7_i2c_xfer_msg()
960 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer_msg()
961 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer_msg()
962 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_xfer_msg()
966 f7_msg->result = 0; in stm32f7_i2c_smbus_xfer_msg()
967 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_smbus_xfer_msg()
974 if (f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
979 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_smbus_xfer_msg()
981 f7_msg->smbus_buf[0] = command; in stm32f7_i2c_smbus_xfer_msg()
982 switch (f7_msg->size) { in stm32f7_i2c_smbus_xfer_msg()
984 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
985 f7_msg->count = 0; in stm32f7_i2c_smbus_xfer_msg()
988 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
989 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
992 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
993 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
994 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
997 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
998 f7_msg->count = 2; in stm32f7_i2c_smbus_xfer_msg()
999 f7_msg->smbus_buf[1] = data->byte; in stm32f7_i2c_smbus_xfer_msg()
1003 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1004 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1005 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1008 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1009 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1010 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1011 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1015 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
1016 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1017 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
1020 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || in stm32f7_i2c_smbus_xfer_msg()
1022 !data->block[0]) { in stm32f7_i2c_smbus_xfer_msg()
1024 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1025 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1027 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1028 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1029 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1033 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1034 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
1035 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
1036 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
1038 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1041 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
1042 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { in stm32f7_i2c_smbus_xfer_msg()
1044 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
1045 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
1047 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
1048 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
1049 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
1051 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
1054 /* Rely on emulated i2c transfer (through master_xfer) */ in stm32f7_i2c_smbus_xfer_msg()
1055 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1057 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); in stm32f7_i2c_smbus_xfer_msg()
1058 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
1061 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_xfer_msg()
1064 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { in stm32f7_i2c_smbus_xfer_msg()
1067 if (!f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
1068 f7_msg->count++; in stm32f7_i2c_smbus_xfer_msg()
1076 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_xfer_msg()
1087 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_xfer_msg()
1088 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_smbus_xfer_msg()
1089 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_xfer_msg()
1091 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_xfer_msg()
1095 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_xfer_msg()
1097 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_xfer_msg()
1100 if (!i2c_dev->use_dma) { in stm32f7_i2c_smbus_xfer_msg()
1115 i2c_dev->master_mode = true; in stm32f7_i2c_smbus_xfer_msg()
1126 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_rep_start()
1127 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_rep_start()
1137 switch (f7_msg->size) { in stm32f7_i2c_smbus_rep_start()
1139 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1143 f7_msg->count = 2; in stm32f7_i2c_smbus_rep_start()
1147 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1152 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_rep_start()
1153 f7_msg->stop = true; in stm32f7_i2c_smbus_rep_start()
1157 f7_msg->count++; in stm32f7_i2c_smbus_rep_start()
1161 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_rep_start()
1177 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_rep_start()
1178 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && in stm32f7_i2c_smbus_rep_start()
1179 f7_msg->size != I2C_SMBUS_BLOCK_DATA && in stm32f7_i2c_smbus_rep_start()
1180 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { in stm32f7_i2c_smbus_rep_start()
1181 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_rep_start()
1183 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_rep_start()
1188 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_rep_start()
1190 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_rep_start()
1193 if (!i2c_dev->use_dma) in stm32f7_i2c_smbus_rep_start()
1208 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_check_pec()
1211 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); in stm32f7_i2c_smbus_check_pec()
1213 switch (f7_msg->size) { in stm32f7_i2c_smbus_check_pec()
1216 received_pec = f7_msg->smbus_buf[1]; in stm32f7_i2c_smbus_check_pec()
1220 received_pec = f7_msg->smbus_buf[2]; in stm32f7_i2c_smbus_check_pec()
1224 count = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_check_pec()
1225 received_pec = f7_msg->smbus_buf[count]; in stm32f7_i2c_smbus_check_pec()
1228 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); in stm32f7_i2c_smbus_check_pec()
1229 return -EINVAL; in stm32f7_i2c_smbus_check_pec()
1233 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", in stm32f7_i2c_smbus_check_pec()
1235 return -EBADMSG; in stm32f7_i2c_smbus_check_pec()
1248 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_is_addr_match()
1250 * For 10-bit addr, addcode = 11110XY with in stm32f7_i2c_is_addr_match()
1254 addr = slave->addr >> 8; in stm32f7_i2c_is_addr_match()
1259 addr = slave->addr & 0x7f; in stm32f7_i2c_is_addr_match()
1269 struct i2c_client *slave = i2c_dev->slave_running; in stm32f7_i2c_slave_start()
1270 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_start()
1274 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_start()
1275 /* Notify i2c slave that new read transfer is starting */ in stm32f7_i2c_slave_start()
1279 * Disable slave TX config in case of I2C combined message in stm32f7_i2c_slave_start()
1280 * (I2C Write followed by I2C Read) in stm32f7_i2c_slave_start()
1296 /* Notify i2c slave that new write transfer is starting */ in stm32f7_i2c_slave_start()
1317 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_addr()
1321 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_addr()
1326 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { in stm32f7_i2c_slave_addr()
1327 i2c_dev->slave_running = i2c_dev->slave[i]; in stm32f7_i2c_slave_addr()
1328 i2c_dev->slave_dir = dir; in stm32f7_i2c_slave_addr()
1330 /* Start I2C slave processing */ in stm32f7_i2c_slave_addr()
1347 if (i2c_dev->slave[i] == slave) { in stm32f7_i2c_get_slave_id()
1353 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); in stm32f7_i2c_get_slave_id()
1355 return -ENODEV; in stm32f7_i2c_get_slave_id()
1361 struct device *dev = i2c_dev->dev; in stm32f7_i2c_get_free_slave_id()
1366 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address in stm32f7_i2c_get_free_slave_id()
1367 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only in stm32f7_i2c_get_free_slave_id()
1369 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { in stm32f7_i2c_get_free_slave_id()
1370 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) in stm32f7_i2c_get_free_slave_id()
1376 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { in stm32f7_i2c_get_free_slave_id()
1378 (slave->flags & I2C_CLIENT_TEN)) in stm32f7_i2c_get_free_slave_id()
1380 if (!i2c_dev->slave[i]) { in stm32f7_i2c_get_free_slave_id()
1387 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); in stm32f7_i2c_get_free_slave_id()
1389 return -EINVAL; in stm32f7_i2c_get_free_slave_id()
1397 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_registered()
1410 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_busy()
1419 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_isr_event()
1424 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_isr_event()
1428 i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1442 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); in stm32f7_i2c_slave_isr_event()
1443 ret = i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1447 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1449 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1458 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); in stm32f7_i2c_slave_isr_event()
1467 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_isr_event()
1479 /* Notify i2c slave that a STOP flag has been detected */ in stm32f7_i2c_slave_isr_event()
1480 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); in stm32f7_i2c_slave_isr_event()
1482 i2c_dev->slave_running = NULL; in stm32f7_i2c_slave_isr_event()
1495 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event()
1496 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_event()
1501 if (!i2c_dev->master_mode) { in stm32f7_i2c_isr_event()
1506 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event()
1518 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", in stm32f7_i2c_isr_event()
1519 __func__, f7_msg->addr); in stm32f7_i2c_isr_event()
1521 f7_msg->result = -ENXIO; in stm32f7_i2c_isr_event()
1536 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_event()
1539 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event()
1540 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event()
1546 if (f7_msg->stop) { in stm32f7_i2c_isr_event()
1549 } else if (i2c_dev->use_dma) { in stm32f7_i2c_isr_event()
1551 } else if (f7_msg->smbus) { in stm32f7_i2c_isr_event()
1554 i2c_dev->msg_id++; in stm32f7_i2c_isr_event()
1555 i2c_dev->msg++; in stm32f7_i2c_isr_event()
1556 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event()
1561 if (f7_msg->smbus) in stm32f7_i2c_isr_event()
1573 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event_thread()
1574 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_event_thread()
1582 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); in stm32f7_i2c_isr_event_thread()
1584 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); in stm32f7_i2c_isr_event_thread()
1586 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_isr_event_thread()
1587 f7_msg->result = -ETIMEDOUT; in stm32f7_i2c_isr_event_thread()
1590 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event_thread()
1593 if (f7_msg->smbus) { in stm32f7_i2c_isr_event_thread()
1596 i2c_dev->msg_id++; in stm32f7_i2c_isr_event_thread()
1597 i2c_dev->msg++; in stm32f7_i2c_isr_event_thread()
1598 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event_thread()
1601 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event_thread()
1602 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event_thread()
1611 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_error()
1612 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_error()
1613 struct device *dev = i2c_dev->dev; in stm32f7_i2c_isr_error()
1614 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_error()
1617 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_error()
1622 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1624 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_isr_error()
1625 f7_msg->result = -EIO; in stm32f7_i2c_isr_error()
1631 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1633 f7_msg->result = -EAGAIN; in stm32f7_i2c_isr_error()
1638 __func__, f7_msg->addr); in stm32f7_i2c_isr_error()
1640 f7_msg->result = -EINVAL; in stm32f7_i2c_isr_error()
1646 i2c_handle_smbus_alert(i2c_dev->alert->ara); in stm32f7_i2c_isr_error()
1650 if (!i2c_dev->slave_running) { in stm32f7_i2c_isr_error()
1661 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_error()
1663 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_isr_error()
1666 i2c_dev->master_mode = false; in stm32f7_i2c_isr_error()
1667 complete(&i2c_dev->complete); in stm32f7_i2c_isr_error()
1676 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer()
1677 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_xfer()
1681 i2c_dev->msg = msgs; in stm32f7_i2c_xfer()
1682 i2c_dev->msg_num = num; in stm32f7_i2c_xfer()
1683 i2c_dev->msg_id = 0; in stm32f7_i2c_xfer()
1684 f7_msg->smbus = false; in stm32f7_i2c_xfer()
1686 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_xfer()
1696 time_left = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_xfer()
1697 i2c_dev->adap.timeout); in stm32f7_i2c_xfer()
1698 ret = f7_msg->result; in stm32f7_i2c_xfer()
1701 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", in stm32f7_i2c_xfer()
1702 i2c_dev->msg->addr); in stm32f7_i2c_xfer()
1703 if (i2c_dev->use_dma) in stm32f7_i2c_xfer()
1704 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_xfer()
1705 ret = -ETIMEDOUT; in stm32f7_i2c_xfer()
1709 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_xfer()
1710 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_xfer()
1721 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer()
1722 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_smbus_xfer()
1723 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer()
1727 f7_msg->addr = addr; in stm32f7_i2c_smbus_xfer()
1728 f7_msg->size = size; in stm32f7_i2c_smbus_xfer()
1729 f7_msg->read_write = read_write; in stm32f7_i2c_smbus_xfer()
1730 f7_msg->smbus = true; in stm32f7_i2c_smbus_xfer()
1744 timeout = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_smbus_xfer()
1745 i2c_dev->adap.timeout); in stm32f7_i2c_smbus_xfer()
1746 ret = f7_msg->result; in stm32f7_i2c_smbus_xfer()
1751 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); in stm32f7_i2c_smbus_xfer()
1752 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1753 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1754 ret = -ETIMEDOUT; in stm32f7_i2c_smbus_xfer()
1769 data->byte = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_xfer()
1773 data->word = f7_msg->smbus_buf[0] | in stm32f7_i2c_smbus_xfer()
1774 (f7_msg->smbus_buf[1] << 8); in stm32f7_i2c_smbus_xfer()
1778 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) in stm32f7_i2c_smbus_xfer()
1779 data->block[i] = f7_msg->smbus_buf[i]; in stm32f7_i2c_smbus_xfer()
1783 ret = -EINVAL; in stm32f7_i2c_smbus_xfer()
1796 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_wakeup()
1799 if (!i2c_dev->wakeup_src) in stm32f7_i2c_enable_wakeup()
1803 device_set_wakeup_enable(i2c_dev->dev, true); in stm32f7_i2c_enable_wakeup()
1806 device_set_wakeup_enable(i2c_dev->dev, false); in stm32f7_i2c_enable_wakeup()
1813 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_reg_slave()
1814 void __iomem *base = i2c_dev->base; in stm32f7_i2c_reg_slave()
1815 struct device *dev = i2c_dev->dev; in stm32f7_i2c_reg_slave()
1819 if (slave->flags & I2C_CLIENT_PEC) { in stm32f7_i2c_reg_slave()
1821 return -EINVAL; in stm32f7_i2c_reg_slave()
1826 return -EBUSY; in stm32f7_i2c_reg_slave()
1843 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1848 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1850 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1851 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); in stm32f7_i2c_reg_slave()
1854 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); in stm32f7_i2c_reg_slave()
1857 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1858 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1863 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1865 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1866 ret = -EOPNOTSUPP; in stm32f7_i2c_reg_slave()
1870 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); in stm32f7_i2c_reg_slave()
1872 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1873 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1877 dev_err(dev, "I2C slave id not supported\n"); in stm32f7_i2c_reg_slave()
1878 ret = -ENODEV; in stm32f7_i2c_reg_slave()
1885 /* Enable Address match interrupt, error interrupt and enable I2C */ in stm32f7_i2c_reg_slave()
1903 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_unreg_slave()
1904 void __iomem *base = i2c_dev->base; in stm32f7_i2c_unreg_slave()
1912 WARN_ON(!i2c_dev->slave[id]); in stm32f7_i2c_unreg_slave()
1914 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1926 i2c_dev->slave[id] = NULL; in stm32f7_i2c_unreg_slave()
1933 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1934 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_unreg_slave()
1944 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || in stm32f7_i2c_write_fm_plus_bits()
1945 IS_ERR_OR_NULL(i2c_dev->regmap)) in stm32f7_i2c_write_fm_plus_bits()
1949 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) in stm32f7_i2c_write_fm_plus_bits()
1950 ret = regmap_update_bits(i2c_dev->regmap, in stm32f7_i2c_write_fm_plus_bits()
1951 i2c_dev->fmp_sreg, in stm32f7_i2c_write_fm_plus_bits()
1952 i2c_dev->fmp_mask, in stm32f7_i2c_write_fm_plus_bits()
1953 enable ? i2c_dev->fmp_mask : 0); in stm32f7_i2c_write_fm_plus_bits()
1955 ret = regmap_write(i2c_dev->regmap, in stm32f7_i2c_write_fm_plus_bits()
1956 enable ? i2c_dev->fmp_sreg : in stm32f7_i2c_write_fm_plus_bits()
1957 i2c_dev->fmp_creg, in stm32f7_i2c_write_fm_plus_bits()
1958 i2c_dev->fmp_mask); in stm32f7_i2c_write_fm_plus_bits()
1966 struct device_node *np = pdev->dev.of_node; in stm32f7_i2c_setup_fm_plus_bits()
1969 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); in stm32f7_i2c_setup_fm_plus_bits()
1970 if (IS_ERR(i2c_dev->regmap)) in stm32f7_i2c_setup_fm_plus_bits()
1974 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, in stm32f7_i2c_setup_fm_plus_bits()
1975 &i2c_dev->fmp_sreg); in stm32f7_i2c_setup_fm_plus_bits()
1979 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + in stm32f7_i2c_setup_fm_plus_bits()
1980 i2c_dev->setup.fmp_clr_offset; in stm32f7_i2c_setup_fm_plus_bits()
1982 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, in stm32f7_i2c_setup_fm_plus_bits()
1983 &i2c_dev->fmp_mask); in stm32f7_i2c_setup_fm_plus_bits()
1988 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_host()
1989 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_host()
1996 i2c_dev->host_notify_client = client; in stm32f7_i2c_enable_smbus_host()
2006 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_host()
2008 if (i2c_dev->host_notify_client) { in stm32f7_i2c_disable_smbus_host()
2012 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); in stm32f7_i2c_disable_smbus_host()
2019 struct i2c_adapter *adap = &i2c_dev->adap; in stm32f7_i2c_enable_smbus_alert()
2020 struct device *dev = i2c_dev->dev; in stm32f7_i2c_enable_smbus_alert()
2021 void __iomem *base = i2c_dev->base; in stm32f7_i2c_enable_smbus_alert()
2025 return -ENOMEM; in stm32f7_i2c_enable_smbus_alert()
2027 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); in stm32f7_i2c_enable_smbus_alert()
2028 if (IS_ERR(alert->ara)) in stm32f7_i2c_enable_smbus_alert()
2029 return PTR_ERR(alert->ara); in stm32f7_i2c_enable_smbus_alert()
2031 i2c_dev->alert = alert; in stm32f7_i2c_enable_smbus_alert()
2041 struct stm32f7_i2c_alert *alert = i2c_dev->alert; in stm32f7_i2c_disable_smbus_alert()
2042 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_smbus_alert()
2048 i2c_unregister_device(alert->ara); in stm32f7_i2c_disable_smbus_alert()
2063 if (i2c_dev->smbus_mode) in stm32f7_i2c_func()
2087 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in stm32f7_i2c_probe()
2089 return -ENOMEM; in stm32f7_i2c_probe()
2091 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32f7_i2c_probe()
2092 if (IS_ERR(i2c_dev->base)) in stm32f7_i2c_probe()
2093 return PTR_ERR(i2c_dev->base); in stm32f7_i2c_probe()
2094 phy_addr = (dma_addr_t)res->start; in stm32f7_i2c_probe()
2098 return irq_event ? : -ENOENT; in stm32f7_i2c_probe()
2102 return irq_error ? : -ENOENT; in stm32f7_i2c_probe()
2104 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, in stm32f7_i2c_probe()
2105 "wakeup-source"); in stm32f7_i2c_probe()
2107 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
2108 if (IS_ERR(i2c_dev->clk)) in stm32f7_i2c_probe()
2109 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), in stm32f7_i2c_probe()
2112 ret = clk_prepare_enable(i2c_dev->clk); in stm32f7_i2c_probe()
2114 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); in stm32f7_i2c_probe()
2118 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
2120 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32f7_i2c_probe()
2128 i2c_dev->dev = &pdev->dev; in stm32f7_i2c_probe()
2130 ret = devm_request_threaded_irq(&pdev->dev, irq_event, in stm32f7_i2c_probe()
2134 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2136 dev_err(&pdev->dev, "Failed to request irq event %i\n", in stm32f7_i2c_probe()
2141 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, in stm32f7_i2c_probe()
2142 pdev->name, i2c_dev); in stm32f7_i2c_probe()
2144 dev_err(&pdev->dev, "Failed to request irq error %i\n", in stm32f7_i2c_probe()
2149 setup = of_device_get_match_data(&pdev->dev); in stm32f7_i2c_probe()
2151 dev_err(&pdev->dev, "Can't get device data\n"); in stm32f7_i2c_probe()
2152 ret = -ENODEV; in stm32f7_i2c_probe()
2155 i2c_dev->setup = *setup; in stm32f7_i2c_probe()
2157 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); in stm32f7_i2c_probe()
2162 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { in stm32f7_i2c_probe()
2171 adap = &i2c_dev->adap; in stm32f7_i2c_probe()
2173 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", in stm32f7_i2c_probe()
2174 &res->start); in stm32f7_i2c_probe()
2175 adap->owner = THIS_MODULE; in stm32f7_i2c_probe()
2176 adap->timeout = 2 * HZ; in stm32f7_i2c_probe()
2177 adap->retries = 3; in stm32f7_i2c_probe()
2178 adap->algo = &stm32f7_i2c_algo; in stm32f7_i2c_probe()
2179 adap->dev.parent = &pdev->dev; in stm32f7_i2c_probe()
2180 adap->dev.of_node = pdev->dev.of_node; in stm32f7_i2c_probe()
2182 init_completion(&i2c_dev->complete); in stm32f7_i2c_probe()
2185 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, in stm32f7_i2c_probe()
2188 if (IS_ERR(i2c_dev->dma)) { in stm32f7_i2c_probe()
2189 ret = PTR_ERR(i2c_dev->dma); in stm32f7_i2c_probe()
2191 if (ret != -ENODEV) in stm32f7_i2c_probe()
2193 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); in stm32f7_i2c_probe()
2194 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2197 if (i2c_dev->wakeup_src) { in stm32f7_i2c_probe()
2198 device_set_wakeup_capable(i2c_dev->dev, true); in stm32f7_i2c_probe()
2200 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); in stm32f7_i2c_probe()
2202 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); in stm32f7_i2c_probe()
2209 pm_runtime_set_autosuspend_delay(i2c_dev->dev, in stm32f7_i2c_probe()
2211 pm_runtime_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2212 pm_runtime_set_active(i2c_dev->dev); in stm32f7_i2c_probe()
2213 pm_runtime_enable(i2c_dev->dev); in stm32f7_i2c_probe()
2215 pm_runtime_get_noresume(&pdev->dev); in stm32f7_i2c_probe()
2219 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); in stm32f7_i2c_probe()
2225 if (i2c_dev->smbus_mode) { in stm32f7_i2c_probe()
2228 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2229 "failed to enable SMBus Host-Notify protocol (%d)\n", in stm32f7_i2c_probe()
2235 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { in stm32f7_i2c_probe()
2238 dev_err(i2c_dev->dev, in stm32f7_i2c_probe()
2245 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); in stm32f7_i2c_probe()
2247 pm_runtime_mark_last_busy(i2c_dev->dev); in stm32f7_i2c_probe()
2248 pm_runtime_put_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2259 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_probe()
2260 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_probe()
2261 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_probe()
2262 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_probe()
2264 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2265 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_probe()
2268 if (i2c_dev->wakeup_src) in stm32f7_i2c_probe()
2269 device_set_wakeup_capable(i2c_dev->dev, false); in stm32f7_i2c_probe()
2271 if (i2c_dev->dma) { in stm32f7_i2c_probe()
2272 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_probe()
2273 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
2280 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_probe()
2292 i2c_del_adapter(&i2c_dev->adap); in stm32f7_i2c_remove()
2293 pm_runtime_get_sync(i2c_dev->dev); in stm32f7_i2c_remove()
2295 if (i2c_dev->wakeup_src) { in stm32f7_i2c_remove()
2296 dev_pm_clear_wake_irq(i2c_dev->dev); in stm32f7_i2c_remove()
2301 device_init_wakeup(i2c_dev->dev, false); in stm32f7_i2c_remove()
2304 pm_runtime_put_noidle(i2c_dev->dev); in stm32f7_i2c_remove()
2305 pm_runtime_disable(i2c_dev->dev); in stm32f7_i2c_remove()
2306 pm_runtime_set_suspended(i2c_dev->dev); in stm32f7_i2c_remove()
2307 pm_runtime_dont_use_autosuspend(i2c_dev->dev); in stm32f7_i2c_remove()
2309 if (i2c_dev->dma) { in stm32f7_i2c_remove()
2310 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_remove()
2311 i2c_dev->dma = NULL; in stm32f7_i2c_remove()
2316 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_remove()
2326 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_runtime_suspend()
2337 ret = clk_prepare_enable(i2c_dev->clk); in stm32f7_i2c_runtime_resume()
2350 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_backup()
2352 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2356 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_backup()
2357 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_backup()
2358 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_backup()
2359 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_backup()
2360 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_backup()
2363 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_backup()
2372 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; in stm32f7_i2c_regs_restore()
2374 ret = pm_runtime_resume_and_get(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2378 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2380 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2383 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_regs_restore()
2384 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, in stm32f7_i2c_regs_restore()
2385 i2c_dev->base + STM32F7_I2C_CR1); in stm32f7_i2c_regs_restore()
2386 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) in stm32f7_i2c_regs_restore()
2387 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_regs_restore()
2389 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_regs_restore()
2390 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_regs_restore()
2391 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_regs_restore()
2394 pm_runtime_put_sync(i2c_dev->dev); in stm32f7_i2c_regs_restore()
2404 i2c_mark_adapter_suspended(&i2c_dev->adap); in stm32f7_i2c_suspend()
2409 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_suspend()
2436 i2c_mark_adapter_resumed(&i2c_dev->adap); in stm32f7_i2c_resume()
2448 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2449 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2456 .name = "stm32f7-i2c",
2467 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");