Lines Matching +full:400 +full:mhz
120 * @parent_rate: I2C clock parent rate in MHz
162 * a minimum value of 2 MHz and a maximum value of 46 MHz due in stm32f4_i2c_set_periph_clk_freq()
173 * To be as close as possible to 400 kHz, the parent clk in stm32f4_i2c_set_periph_clk_freq()
174 * frequency should be between a minimum value of 6 MHz and a in stm32f4_i2c_set_periph_clk_freq()
175 * maximum value of 46 MHz due to hardware limitation in stm32f4_i2c_set_periph_clk_freq()
213 * is not higher than 46 MHz . As a result trise is at most 4 bits wide in stm32f4_i2c_set_rise_time()
237 * For example with parent rate = 2 MHz: in stm32f4_i2c_set_speed_mode()
243 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()
250 * frequencies we are not able to reach 400 kHz. in stm32f4_i2c_set_speed_mode()
254 * So, CCR = I2C parent rate / (400 kHz * 3) in stm32f4_i2c_set_speed_mode()
256 * For example with parent rate = 6 MHz: in stm32f4_i2c_set_speed_mode()
260 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached in stm32f4_i2c_set_speed_mode()
263 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()