1 // SPDX-License-Identifier: GPL-2.0
3  * drivers/i2c/busses/i2c-mt7621.c
9  * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
47 #define SM0CTL1_PGLEN(x)	((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)  argument
57 #define TIMEOUT_MS		1000
60 	void __iomem *base;  member
74 	ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,  in mtk_i2c_wait_idle()
76 					 10, TIMEOUT_MS * 1000);  in mtk_i2c_wait_idle()
78 		dev_dbg(i2c->dev, "idle err(%d)\n", ret);  in mtk_i2c_wait_idle()
87 	ret = device_reset(i2c->adap.dev.parent);  in mtk_i2c_reset()
89 		dev_err(i2c->dev, "I2C reset failed!\n");  in mtk_i2c_reset()
93 	 * configure open-drain mode, this bit needs to be cleared.  in mtk_i2c_reset()
95 	iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |  in mtk_i2c_reset()
96 		  SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);  in mtk_i2c_reset()
97 	iowrite32(0, i2c->base + REG_SM0CFG2_REG);  in mtk_i2c_reset()
102 	dev_dbg(i2c->dev,  in mtk_i2c_dump_reg()
103 		"SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",  in mtk_i2c_dump_reg()
104 		ioread32(i2c->base + REG_SM0CFG2_REG),  in mtk_i2c_dump_reg()
105 		ioread32(i2c->base + REG_SM0CTL0_REG),  in mtk_i2c_dump_reg()
106 		ioread32(i2c->base + REG_SM0CTL1_REG),  in mtk_i2c_dump_reg()
107 		ioread32(i2c->base + REG_SM0D0_REG),  in mtk_i2c_dump_reg()
108 		ioread32(i2c->base + REG_SM0D1_REG));  in mtk_i2c_dump_reg()
113 	u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);  in mtk_i2c_check_ack()
116 	return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;  in mtk_i2c_check_ack()
121 	iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);  in mtk_i2c_master_start()
127 	iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);  in mtk_i2c_master_stop()
134 		  i2c->base + REG_SM0CTL1_REG);  in mtk_i2c_master_cmd()
164 		if (pmsg->flags & I2C_M_TEN) {  in mtk_i2c_master_xfer()
166 			addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);  in mtk_i2c_master_xfer()
167 			addr |= (pmsg->addr & 0xff) << 8;  in mtk_i2c_master_xfer()
168 			if (pmsg->flags & I2C_M_RD)  in mtk_i2c_master_xfer()
170 			iowrite32(addr, i2c->base + REG_SM0D0_REG);  in mtk_i2c_master_xfer()
177 			iowrite32(addr, i2c->base + REG_SM0D0_REG);  in mtk_i2c_master_xfer()
184 		if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {  in mtk_i2c_master_xfer()
191 		for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {  in mtk_i2c_master_xfer()
194 			if (pmsg->flags & I2C_M_RD) {  in mtk_i2c_master_xfer()
198 				memcpy(data, &pmsg->buf[j], page_len);  in mtk_i2c_master_xfer()
199 				iowrite32(data[0], i2c->base + REG_SM0D0_REG);  in mtk_i2c_master_xfer()
200 				iowrite32(data[1], i2c->base + REG_SM0D1_REG);  in mtk_i2c_master_xfer()
208 			if (pmsg->flags & I2C_M_RD) {  in mtk_i2c_master_xfer()
209 				data[0] = ioread32(i2c->base + REG_SM0D0_REG);  in mtk_i2c_master_xfer()
210 				data[1] = ioread32(i2c->base + REG_SM0D1_REG);  in mtk_i2c_master_xfer()
211 				memcpy(&pmsg->buf[j], data, page_len);  in mtk_i2c_master_xfer()
213 				if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {  in mtk_i2c_master_xfer()
216 								- 1);  in mtk_i2c_master_xfer()
235 	return -ENXIO;  in mtk_i2c_master_xfer()
254 	{ .compatible = "mediatek,mt7621-i2c" },
262 	i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;  in mtk_i2c_init()
263 	if (i2c->clk_div < 99)  in mtk_i2c_init()
264 		i2c->clk_div = 99;  in mtk_i2c_init()
265 	if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)  in mtk_i2c_init()
266 		i2c->clk_div = SM0CTL0_CLK_DIV_MAX;  in mtk_i2c_init()
280 	i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);  in mtk_i2c_probe()
282 		return -ENOMEM;  in mtk_i2c_probe()
284 	i2c->base = devm_ioremap_resource(&pdev->dev, res);  in mtk_i2c_probe()
285 	if (IS_ERR(i2c->base))  in mtk_i2c_probe()
286 		return PTR_ERR(i2c->base);  in mtk_i2c_probe()
288 	i2c->clk = devm_clk_get(&pdev->dev, NULL);  in mtk_i2c_probe()
289 	if (IS_ERR(i2c->clk)) {  in mtk_i2c_probe()
290 		dev_err(&pdev->dev, "no clock defined\n");  in mtk_i2c_probe()
291 		return PTR_ERR(i2c->clk);  in mtk_i2c_probe()
293 	ret = clk_prepare_enable(i2c->clk);  in mtk_i2c_probe()
295 		dev_err(&pdev->dev, "Unable to enable clock\n");  in mtk_i2c_probe()
299 	i2c->dev = &pdev->dev;  in mtk_i2c_probe()
301 	if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",  in mtk_i2c_probe()
302 				 &i2c->bus_freq))  in mtk_i2c_probe()
303 		i2c->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;  in mtk_i2c_probe()
305 	if (i2c->bus_freq == 0) {  in mtk_i2c_probe()
306 		dev_warn(i2c->dev, "clock-frequency 0 not supported\n");  in mtk_i2c_probe()
307 		return -EINVAL;  in mtk_i2c_probe()
310 	adap = &i2c->adap;  in mtk_i2c_probe()
311 	adap->owner = THIS_MODULE;  in mtk_i2c_probe()
312 	adap->algo = &mtk_i2c_algo;  in mtk_i2c_probe()
313 	adap->retries = 3;  in mtk_i2c_probe()
314 	adap->dev.parent = &pdev->dev;  in mtk_i2c_probe()
316 	adap->dev.of_node = pdev->dev.of_node;  in mtk_i2c_probe()
317 	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));  in mtk_i2c_probe()
327 	dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);  in mtk_i2c_probe()
336 	clk_disable_unprepare(i2c->clk);  in mtk_i2c_remove()
337 	i2c_del_adapter(&i2c->adap);  in mtk_i2c_remove()
346 		.name	= "i2c-mt7621",
356 MODULE_ALIAS("platform:MT7621-I2C");