Lines Matching +full:num +full:- +full:transfer +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
34 * Special bits are available for both modes of operation to set commands
35 * and for checking transfer status
64 /* I2C_CTL Register bits */
71 /* I2C_FIFO_CTL Register bits */
77 /* I2C_TRAILING_CTL Register bits */
80 /* I2C_INT_EN Register bits */
85 /* I2C_INT_STAT Register bits */
106 /* I2C_FIFO_STAT Register bits */
114 /* I2C_CONF Register bits */
119 /* I2C_AUTO_CONF Register bits */
124 /* I2C_TIMEOUT Register bits */
128 /* I2C_MANUAL_CMD register bits */
132 /* I2C_TRANS_STATUS register bits */
136 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
143 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
161 /* I2C_ADDR register bits */
200 /* Version of HS-I2C Hardware */
205 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
235 .compatible = "samsung,exynos5-hsi2c",
238 .compatible = "samsung,exynos5250-hsi2c",
241 .compatible = "samsung,exynos5260-hsi2c",
244 .compatible = "samsung,exynos7-hsi2c",
252 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
253 i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_clr_pend_irq()
263 * Returns 0 on success, -EINVAL if the cycle length cannot
278 unsigned int clkin = clk_get_rate(i2c->clk); in exynos5_i2c_set_timing()
279 unsigned int op_clk = hs_timings ? i2c->op_clock : in exynos5_i2c_set_timing()
280 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ : in exynos5_i2c_set_timing()
281 i2c->op_clock; in exynos5_i2c_set_timing()
299 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; in exynos5_i2c_set_timing()
300 temp = clkin / op_clk - 8 - t_ftl_cycle; in exynos5_i2c_set_timing()
301 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) in exynos5_i2c_set_timing()
302 temp -= t_ftl_cycle; in exynos5_i2c_set_timing()
304 clk_cycle = temp / (div + 1) - 2; in exynos5_i2c_set_timing()
306 dev_err(i2c->dev, "%s clock set-up failed\n", in exynos5_i2c_set_timing()
308 return -EINVAL; in exynos5_i2c_set_timing()
325 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", in exynos5_i2c_set_timing()
327 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", in exynos5_i2c_set_timing()
329 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", in exynos5_i2c_set_timing()
331 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); in exynos5_i2c_set_timing()
334 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing()
335 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing()
336 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
338 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing()
339 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing()
340 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
342 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing()
352 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_hsi2c_clock_setup()
364 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
365 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
369 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
372 i2c->regs + HSI2C_CTL); in exynos5_i2c_init()
373 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); in exynos5_i2c_init()
375 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) { in exynos5_i2c_init()
376 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), in exynos5_i2c_init()
377 i2c->regs + HSI2C_ADDR); in exynos5_i2c_init()
381 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
389 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
391 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
393 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
395 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
417 i2c->state = -EINVAL; in exynos5_i2c_irq()
419 spin_lock(&i2c->lock); in exynos5_i2c_irq()
421 int_status = readl(i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
422 writel(int_status, i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
424 /* handle interrupt related to the transfer status */ in exynos5_i2c_irq()
425 if (i2c->variant->hw == I2C_TYPE_EXYNOS7) { in exynos5_i2c_irq()
427 i2c->trans_done = 1; in exynos5_i2c_irq()
428 i2c->state = 0; in exynos5_i2c_irq()
430 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
431 i2c->state = -EAGAIN; in exynos5_i2c_irq()
434 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
435 i2c->state = -ENXIO; in exynos5_i2c_irq()
438 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
439 i2c->state = -ENXIO; in exynos5_i2c_irq()
442 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
443 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
447 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_irq()
449 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
450 i2c->state = -ENXIO; in exynos5_i2c_irq()
453 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
454 i2c->state = -ENXIO; in exynos5_i2c_irq()
457 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
458 i2c->state = -EAGAIN; in exynos5_i2c_irq()
461 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
462 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
465 i2c->trans_done = 1; in exynos5_i2c_irq()
466 i2c->state = 0; in exynos5_i2c_irq()
470 if ((i2c->msg->flags & I2C_M_RD) && (int_status & in exynos5_i2c_irq()
472 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
474 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); in exynos5_i2c_irq()
478 readl(i2c->regs + HSI2C_RX_DATA); in exynos5_i2c_irq()
479 i2c->msg->buf[i2c->msg_ptr++] = byte; in exynos5_i2c_irq()
480 len--; in exynos5_i2c_irq()
482 i2c->state = 0; in exynos5_i2c_irq()
484 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
487 len = i2c->variant->fifo_depth - fifo_level; in exynos5_i2c_irq()
488 if (len > (i2c->msg->len - i2c->msg_ptr)) { in exynos5_i2c_irq()
489 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
492 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
493 len = i2c->msg->len - i2c->msg_ptr; in exynos5_i2c_irq()
497 byte = i2c->msg->buf[i2c->msg_ptr++]; in exynos5_i2c_irq()
498 writel(byte, i2c->regs + HSI2C_TX_DATA); in exynos5_i2c_irq()
499 len--; in exynos5_i2c_irq()
501 i2c->state = 0; in exynos5_i2c_irq()
505 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || in exynos5_i2c_irq()
506 (i2c->state < 0)) { in exynos5_i2c_irq()
507 writel(0, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
509 complete(&i2c->msg_complete); in exynos5_i2c_irq()
512 spin_unlock(&i2c->lock); in exynos5_i2c_irq()
523 * Returns -EBUSY if the bus cannot be bought to idle
533 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_wait_bus_idle()
540 return -EBUSY; in exynos5_i2c_wait_bus_idle()
547 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; in exynos5_i2c_bus_recover()
548 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
549 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
550 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
555 * bits + one pulse for NACK). in exynos5_i2c_bus_recover()
557 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
559 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
562 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; in exynos5_i2c_bus_recover()
563 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
564 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
565 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
572 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) in exynos5_i2c_bus_check()
582 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_bus_check()
597 * stop: Enables stop after transfer if set. Set for last transfer of
614 if (i2c->variant->hw == I2C_TYPE_EXYNOS7) in exynos5_i2c_message_start()
619 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
623 if (i2c->msg->flags & I2C_M_RD) { in exynos5_i2c_message_start()
628 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
629 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
637 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
638 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
644 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); in exynos5_i2c_message_start()
646 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_i2c_message_start()
647 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)); in exynos5_i2c_message_start()
649 writel(i2c_addr, i2c->regs + HSI2C_ADDR); in exynos5_i2c_message_start()
651 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); in exynos5_i2c_message_start()
652 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
657 * Enable interrupts before starting the transfer so that we don't in exynos5_i2c_message_start()
660 spin_lock_irqsave(&i2c->lock, flags); in exynos5_i2c_message_start()
661 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_message_start()
665 i2c_auto_conf |= i2c->msg->len; in exynos5_i2c_message_start()
667 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); in exynos5_i2c_message_start()
668 spin_unlock_irqrestore(&i2c->lock, flags); in exynos5_i2c_message_start()
677 i2c->msg = msgs; in exynos5_i2c_xfer_msg()
678 i2c->msg_ptr = 0; in exynos5_i2c_xfer_msg()
679 i2c->trans_done = 0; in exynos5_i2c_xfer_msg()
681 reinit_completion(&i2c->msg_complete); in exynos5_i2c_xfer_msg()
685 timeout = wait_for_completion_timeout(&i2c->msg_complete, in exynos5_i2c_xfer_msg()
688 ret = -ETIMEDOUT; in exynos5_i2c_xfer_msg()
690 ret = i2c->state; in exynos5_i2c_xfer_msg()
701 if (ret == -ETIMEDOUT) in exynos5_i2c_xfer_msg()
702 dev_warn(i2c->dev, "%s timeout\n", in exynos5_i2c_xfer_msg()
703 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); in exynos5_i2c_xfer_msg()
711 struct i2c_msg *msgs, int num) in exynos5_i2c_xfer() argument
713 struct exynos5_i2c *i2c = adap->algo_data; in exynos5_i2c_xfer()
716 ret = clk_enable(i2c->clk); in exynos5_i2c_xfer()
720 for (i = 0; i < num; ++i) { in exynos5_i2c_xfer()
721 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num); in exynos5_i2c_xfer()
726 clk_disable(i2c->clk); in exynos5_i2c_xfer()
728 return ret ?: num; in exynos5_i2c_xfer()
743 struct device_node *np = pdev->dev.of_node; in exynos5_i2c_probe()
747 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); in exynos5_i2c_probe()
749 return -ENOMEM; in exynos5_i2c_probe()
751 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) in exynos5_i2c_probe()
752 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; in exynos5_i2c_probe()
754 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); in exynos5_i2c_probe()
755 i2c->adap.owner = THIS_MODULE; in exynos5_i2c_probe()
756 i2c->adap.algo = &exynos5_i2c_algorithm; in exynos5_i2c_probe()
757 i2c->adap.retries = 3; in exynos5_i2c_probe()
759 i2c->dev = &pdev->dev; in exynos5_i2c_probe()
760 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); in exynos5_i2c_probe()
761 if (IS_ERR(i2c->clk)) { in exynos5_i2c_probe()
762 dev_err(&pdev->dev, "cannot get clock\n"); in exynos5_i2c_probe()
763 return -ENOENT; in exynos5_i2c_probe()
766 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_probe()
770 i2c->regs = devm_platform_ioremap_resource(pdev, 0); in exynos5_i2c_probe()
771 if (IS_ERR(i2c->regs)) { in exynos5_i2c_probe()
772 ret = PTR_ERR(i2c->regs); in exynos5_i2c_probe()
776 i2c->adap.dev.of_node = np; in exynos5_i2c_probe()
777 i2c->adap.algo_data = i2c; in exynos5_i2c_probe()
778 i2c->adap.dev.parent = &pdev->dev; in exynos5_i2c_probe()
780 /* Clear pending interrupts from u-boot or misc causes */ in exynos5_i2c_probe()
783 spin_lock_init(&i2c->lock); in exynos5_i2c_probe()
784 init_completion(&i2c->msg_complete); in exynos5_i2c_probe()
786 i2c->irq = ret = platform_get_irq(pdev, 0); in exynos5_i2c_probe()
790 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, in exynos5_i2c_probe()
791 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c); in exynos5_i2c_probe()
793 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); in exynos5_i2c_probe()
797 i2c->variant = of_device_get_match_data(&pdev->dev); in exynos5_i2c_probe()
805 ret = i2c_add_adapter(&i2c->adap); in exynos5_i2c_probe()
811 clk_disable(i2c->clk); in exynos5_i2c_probe()
816 clk_disable_unprepare(i2c->clk); in exynos5_i2c_probe()
824 i2c_del_adapter(&i2c->adap); in exynos5_i2c_remove()
826 clk_unprepare(i2c->clk); in exynos5_i2c_remove()
836 i2c_mark_adapter_suspended(&i2c->adap); in exynos5_i2c_suspend_noirq()
837 clk_unprepare(i2c->clk); in exynos5_i2c_suspend_noirq()
847 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_resume_noirq()
853 clk_disable_unprepare(i2c->clk); in exynos5_i2c_resume_noirq()
858 clk_disable(i2c->clk); in exynos5_i2c_resume_noirq()
859 i2c_mark_adapter_resumed(&i2c->adap); in exynos5_i2c_resume_noirq()
874 .name = "exynos5-hsi2c",
882 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");