53 	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);  in i2c_dw_set_timings_master()
248 	regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);  in i2c_dw_xfer_init()
251 	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);  in i2c_dw_xfer_init()
337 						regmap_read(dev->map, DW_IC_DATA_CMD, &val);  in amd_i2c_dw_xfer_quirk()
406 		regmap_read(dev->map, DW_IC_TXFLR, &flr);  in i2c_dw_xfer_msg()
409 		regmap_read(dev->map, DW_IC_RXFLR, &flr);  in i2c_dw_xfer_msg()
522 		regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);  in i2c_dw_read()
527 			regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);  in i2c_dw_read()
675 	regmap_read(dev->map, DW_IC_INTR_STAT, &stat);  in i2c_dw_read_clear_intrbits()
685 		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);  in i2c_dw_read_clear_intrbits()
687 		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);  in i2c_dw_read_clear_intrbits()
689 		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);  in i2c_dw_read_clear_intrbits()
691 		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);  in i2c_dw_read_clear_intrbits()
697 		regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);  in i2c_dw_read_clear_intrbits()
698 		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);  in i2c_dw_read_clear_intrbits()
701 		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);  in i2c_dw_read_clear_intrbits()
703 		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);  in i2c_dw_read_clear_intrbits()
705 		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);  in i2c_dw_read_clear_intrbits()
707 		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);  in i2c_dw_read_clear_intrbits()
709 		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);  in i2c_dw_read_clear_intrbits()
752 		regmap_read(dev->map, DW_IC_INTR_MASK, &stat);  in i2c_dw_irq_handler_master()
765 	regmap_read(dev->map, DW_IC_ENABLE, &enabled);  in i2c_dw_isr()
766 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);  in i2c_dw_isr()