Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
27 ('D' << 16))
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
73 # define V3D_CTSEMA BIT(12)
74 # define V3D_CTRTSD BIT(8)
75 # define V3D_CTRUN BIT(5)
76 # define V3D_CTSUBS BIT(4)
77 # define V3D_CTERR BIT(3)
78 # define V3D_CTMODE BIT(0)
97 # define V3D_BMOOM BIT(8)
98 # define V3D_RMBUSY BIT(3)
99 # define V3D_RMACTIVE BIT(2)
100 # define V3D_BMBUSY BIT(1)
101 # define V3D_BMACTIVE BIT(0)
121 # define V3D_PCTRE_EN BIT(31)
144 # define PV_CONTROL_CLR_AT_START BIT(14)
145 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146 # define PV_CONTROL_WAIT_HSTART BIT(12)
154 # define PV_CONTROL_FIFO_CLR BIT(1)
155 # define PV_CONTROL_EN BIT(0)
160 # define PV_VCONTROL_ODD_FIRST BIT(5)
161 # define PV_VCONTROL_INTERLACE BIT(4)
162 # define PV_VCONTROL_DSI BIT(3)
163 # define PV_VCONTROL_COMMAND BIT(2)
164 # define PV_VCONTROL_CONTINUOUS BIT(1)
165 # define PV_VCONTROL_VIDEN BIT(0)
170 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
171 # define PV_HORZA_HBP_SHIFT 16
176 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
177 # define PV_HORZB_HFP_SHIFT 16
182 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
183 # define PV_VERTA_VBP_SHIFT 16
188 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
189 # define PV_VERTB_VFP_SHIFT 16
198 # define PV_INT_VID_IDLE BIT(9)
199 # define PV_INT_VFP_END BIT(8)
200 # define PV_INT_VFP_START BIT(7)
201 # define PV_INT_VACT_START BIT(6)
202 # define PV_INT_VBP_START BIT(5)
203 # define PV_INT_VSYNC_START BIT(4)
204 # define PV_INT_HFP_START BIT(3)
205 # define PV_INT_HACT_START BIT(2)
206 # define PV_INT_HBP_START BIT(1)
207 # define PV_INT_HSYNC_START BIT(0)
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
230 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
231 /* Enables Display 0 end-of-line-N contribution to
234 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
236 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
238 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
239 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
240 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
244 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
246 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
256 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
258 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
262 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
266 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
270 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
272 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
278 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
280 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
282 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
286 # define SCALER_DISPSTAT_IRQDMA BIT(4)
288 * corresponding interrupt bit is enabled in DISPCTRL.
290 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
292 # define SCALER_DISPSTAT_IRQSCL BIT(0)
314 (x) * (SCALER_DISPLIST1 - \
321 (x) * (SCALER_DISPLACT1 - \
325 # define SCALER_DISPCTRLX_ENABLE BIT(31)
326 # define SCALER_DISPCTRLX_RESET BIT(30)
330 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
334 # define SCALER_DISPCTRLX_ONECTX BIT(28)
335 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
336 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
340 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
347 # define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
348 # define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
352 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
362 # define SCALER_DISPBKGND_AUTOHS BIT(31)
363 # define SCALER_DISPBKGND_INTERLACE BIT(30)
364 # define SCALER_DISPBKGND_GAMMA BIT(29)
371 # define SCALER_DISPBKGND_FILL BIT(24)
380 # define SCALER_DISPSTATX_FULL BIT(29)
381 # define SCALER_DISPSTATX_EMPTY BIT(28)
389 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
392 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
393 # define SCALER_DISPBASEX_TOP_SHIFT 16
395 * channel. Must be 4-pixel aligned.
403 (x) * (SCALER_DISPBKGND1 - \
407 (x) * (SCALER_DISPSTAT1 - \
411 (x) * (SCALER_DISPBASE1 - \
415 (x) * (SCALER_DISPCTRL1 - \
422 # define SCALER_GAMADDR_AUTOINC BIT(31)
426 # define SCALER_GAMADDR_SRAMENB BIT(30)
429 /* Clamps R to [16,235] and G/B to [16,240]. */
430 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
440 /* Offsets are 8-bit 2s-complement. */
441 # define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
442 # define SCALER_OLEDOFFS_RED_SHIFT 16
479 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
480 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
482 # define SCALER_DISPSLAVE_EOL BIT(26)
484 # define SCALER_DISPSLAVE_EMPTY BIT(25)
486 # define SCALER_DISPSLAVE_VALID BIT(24)
496 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
497 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
499 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
501 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
502 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
506 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
507 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
508 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
509 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
513 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
515 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
519 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)
520 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16
549 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
554 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
556 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
560 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
564 # define VC4_HDMI_HORZA_VPOS BIT(14)
565 # define VC4_HDMI_HORZA_HPOS BIT(13)
570 /* Horizontal pack porch (htotal - hsync_end). */
573 /* Horizontal sync pulse (hsync_end - hsync_start). */
576 /* Horizontal front porch (hsync_start - hdisplay). */
580 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
581 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
582 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
583 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
584 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
585 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
586 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
587 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
588 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
589 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
592 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
593 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
594 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
595 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
596 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
598 /* Vertical sync pulse (vsync_end - vsync_start). */
601 /* Vertical front porch (vsync_start - vdisplay). */
611 /* Vertical pack porch (vtotal - vsync_end). */
616 # define VC4_HDMI_CEC_TX_EOM BIT(31)
621 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
622 # define VC4_HDMI_CEC_RX_EOM BIT(29)
623 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
630 * If disabled, maximum 16 bytes will be received (including header),
634 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
635 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
637 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
641 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
642 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
643 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
647 /* Divides off of HSM clock to generate CEC bit clock. */
648 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
652 /* Set these fields to how many bit clock cycles get to that many
659 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
668 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
669 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
677 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
678 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
684 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
685 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
686 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
687 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
688 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
689 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
690 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
696 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
698 # define VC4_HDMI_CPU_CEC BIT(6)
699 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
702 # define VC4_HD_CECRXD BIT(9)
704 # define VC4_HD_CECOVR BIT(8)
707 # define VC4_HD_M_SW_RST BIT(2)
708 # define VC4_HD_M_ENABLE BIT(0)
713 # define VC4_HD_MAI_CTL_DLATE BIT(15)
714 # define VC4_HD_MAI_CTL_BUSY BIT(14)
715 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
716 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
717 # define VC4_HD_MAI_CTL_FULL BIT(11)
718 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
719 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
720 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
723 # define VC4_HD_MAI_CTL_PAREN BIT(8)
726 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
727 /* Underflow error status bit, write 1 to clear. */
728 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
729 /* Overflow error status bit, write 1 to clear. */
730 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
731 /* Single-shot reset bit. Read value is undefined. */
732 # define VC4_HD_MAI_CTL_RESET BIT(0)
736 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
737 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
751 # define VC4_HD_VID_CTL_ENABLE BIT(31)
752 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
753 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
754 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
755 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
756 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
757 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
758 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
768 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
774 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
775 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
777 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
785 /* 16bpp */
804 HVS_PIXEL_FORMAT_RGBA1010102 = 16,
826 #define SCALER_CTL0_END BIT(31)
827 #define SCALER_CTL0_VALID BIT(30)
839 #define SCALER_CTL0_ALPHA_MASK BIT(19)
840 #define SCALER_CTL0_HFLIP BIT(16)
841 #define SCALER_CTL0_VFLIP BIT(15)
860 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
862 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
880 #define SCALER_CTL0_UNITY BIT(4)
881 #define SCALER5_CTL0_UNITY BIT(15)
897 #define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
898 #define SCALER5_POS0_START_Y_SHIFT 16
903 #define SCALER5_POS0_VFLIP BIT(31)
904 #define SCALER5_POS0_HFLIP BIT(15)
913 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
915 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
917 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
922 #define SCALER5_CTL2_GAMMA BIT(16)
927 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
928 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
933 #define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
934 #define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
945 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
946 #define SCALER_POS2_ALPHA_MIX BIT(28)
948 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
949 #define SCALER_POS2_HEIGHT_SHIFT 16
954 #define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
955 #define SCALER5_POS2_HEIGHT_SHIFT 16
962 * 0x2: 2, 0x3: -1}
968 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
969 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
970 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
973 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1009 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1020 #define SCALER_PPF_NOINTERP BIT(31)
1024 #define SCALER_PPF_AGC BIT(30)
1032 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1039 #define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1040 #define SCALER_TILE_SKIP_0_SHIFT 16
1048 /* PITCH0 fields for T-tiled. */
1049 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1050 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1051 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1052 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)