Lines Matching +full:bcm2835 +full:- +full:dsi1
1 // SPDX-License-Identifier: GPL-2.0-only
7 * DOC: VC4 DSI0/DSI1 module
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
497 /* Whether we're on bcm2835's DSI0 or DSI1. */
564 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
571 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
575 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
577 tx = chan->device->device_prep_dma_memcpy(chan, in dsi_dma_workaround_write()
578 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
579 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
586 cookie = tx->tx_submit(tx); in dsi_dma_workaround_write()
597 #define DSI_READ(offset) readl(dsi->regs + (offset))
600 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
602 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
603 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
682 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
685 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
686 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
687 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
690 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
691 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
692 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
695 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
696 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
697 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
709 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
728 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
757 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_disable()
758 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
761 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
762 if (iter->funcs->disable) in vc4_dsi_encoder_disable()
763 iter->funcs->disable(iter); in vc4_dsi_encoder_disable()
768 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
769 if (iter->funcs->post_disable) in vc4_dsi_encoder_disable()
770 iter->funcs->post_disable(iter); in vc4_dsi_encoder_disable()
773 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
774 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
775 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
780 /* Extends the mode's blank intervals to handle BCM2835's integer-only
790 * higher-than-expected clock rate to the panel, but that's what the
798 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_mode_fixup()
799 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
801 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_encoder_mode_fixup()
802 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
810 divider--; in vc4_dsi_encoder_mode_fixup()
819 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
821 adjusted_mode->clock = pixel_clock_hz / 1000; in vc4_dsi_encoder_mode_fixup()
824 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / in vc4_dsi_encoder_mode_fixup()
825 mode->clock; in vc4_dsi_encoder_mode_fixup()
826 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; in vc4_dsi_encoder_mode_fixup()
827 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; in vc4_dsi_encoder_mode_fixup()
834 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in vc4_dsi_encoder_enable()
836 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_enable()
837 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
844 unsigned long pixel_clock_hz = mode->clock * 1000; in vc4_dsi_encoder_enable()
851 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_encoder_enable()
856 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
857 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_encoder_enable()
858 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
865 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
866 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
868 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
885 if (dsi->variant->port == 0) { in vc4_dsi_encoder_enable()
889 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
892 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
910 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
912 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
914 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
927 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
933 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
939 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
949 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
955 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
1000 /* T_INIT is how long STOP is driven after power-up to in vc4_dsi_encoder_enable()
1001 * indicate to the slave (also coming out of power-up) that in vc4_dsi_encoder_enable()
1004 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and in vc4_dsi_encoder_enable()
1025 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1026 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1027 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1029 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1031 (dsi->variant->port == 0 ? in vc4_dsi_encoder_enable()
1032 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_encoder_enable()
1033 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_encoder_enable()
1057 if (dsi->variant->port == 0) in vc4_dsi_encoder_enable()
1063 if (dsi->variant->port == 0) { in vc4_dsi_encoder_enable()
1072 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1073 if (iter->funcs->pre_enable) in vc4_dsi_encoder_enable()
1074 iter->funcs->pre_enable(iter); in vc4_dsi_encoder_enable()
1077 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1079 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1081 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1092 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1093 if (iter->funcs->enable) in vc4_dsi_encoder_enable()
1094 iter->funcs->enable(iter); in vc4_dsi_encoder_enable()
1098 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
1099 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_encoder_enable()
1100 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
1111 bool is_long = mipi_dsi_packet_format_is_long(msg->type); in vc4_dsi_host_transfer()
1122 * The command FIFO takes byte-oriented data, but is of in vc4_dsi_host_transfer()
1136 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / in vc4_dsi_host_transfer()
1145 if (msg->rx_len) { in vc4_dsi_host_transfer()
1165 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in vc4_dsi_host_transfer()
1185 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1186 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1188 if (msg->rx_len) { in vc4_dsi_host_transfer()
1200 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1202 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1203 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1205 ret = -ETIMEDOUT; in vc4_dsi_host_transfer()
1207 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1215 if (ret == 0 && msg->rx_len) { in vc4_dsi_host_transfer()
1217 u8 *msg_rx = msg->rx_buf; in vc4_dsi_host_transfer()
1223 if (rxlen != msg->rx_len) { in vc4_dsi_host_transfer()
1225 rxlen, (int)msg->rx_len); in vc4_dsi_host_transfer()
1226 ret = -ENXIO; in vc4_dsi_host_transfer()
1230 for (i = 0; i < msg->rx_len; i++) in vc4_dsi_host_transfer()
1237 if (msg->rx_len > 1) { in vc4_dsi_host_transfer()
1267 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1268 dsi->channel = device->channel; in vc4_dsi_host_attach()
1269 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1271 switch (device->format) { in vc4_dsi_host_attach()
1273 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1274 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1277 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1278 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1281 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1282 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1285 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1286 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1289 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1290 dsi->format); in vc4_dsi_host_attach()
1294 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1295 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1300 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1302 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_host_attach()
1350 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1351 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1352 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1363 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1414 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1417 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1418 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1426 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1427 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1433 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1434 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1445 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1446 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1450 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1451 return -ENOMEM; in vc4_dsi_init_phy_clocks()
1452 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1455 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1461 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1472 fix->mult = 1; in vc4_dsi_init_phy_clocks()
1473 fix->div = phy_clocks[i].div; in vc4_dsi_init_phy_clocks()
1474 fix->hw.init = &init; in vc4_dsi_init_phy_clocks()
1482 ret = devm_clk_hw_register(dev, &fix->hw); in vc4_dsi_init_phy_clocks()
1486 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1489 return of_clk_add_hw_provider(dev->of_node, in vc4_dsi_init_phy_clocks()
1491 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1507 return -ENODEV; in vc4_dsi_bind()
1509 dsi->variant = match->data; in vc4_dsi_bind()
1514 return -ENOMEM; in vc4_dsi_bind()
1516 INIT_LIST_HEAD(&dsi->bridge_chain); in vc4_dsi_bind()
1517 vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1; in vc4_dsi_bind()
1518 vc4_dsi_encoder->dsi = dsi; in vc4_dsi_bind()
1519 dsi->encoder = &vc4_dsi_encoder->base.base; in vc4_dsi_bind()
1521 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1522 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1523 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1525 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1526 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1527 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1532 return -ENODEV; in vc4_dsi_bind()
1535 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to in vc4_dsi_bind()
1539 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1540 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1541 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1543 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1545 return -ENOMEM; in vc4_dsi_bind()
1550 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1551 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1552 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1553 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1563 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1567 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1568 /* At startup enable error-reporting interrupts and nothing else. */ in vc4_dsi_bind()
1573 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1583 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1588 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1589 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1590 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1591 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1596 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1597 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1598 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1599 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1604 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1605 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1606 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1607 if (ret != -EPROBE_DEFER) in vc4_dsi_bind()
1612 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, in vc4_dsi_bind()
1613 &panel, &dsi->bridge); in vc4_dsi_bind()
1615 /* If the bridge or panel pointed by dev->of_node is not in vc4_dsi_bind()
1621 if (ret == -ENODEV) in vc4_dsi_bind()
1628 dsi->bridge = devm_drm_panel_bridge_add_typed(dev, panel, in vc4_dsi_bind()
1630 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1631 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1635 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1645 drm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI); in vc4_dsi_bind()
1646 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); in vc4_dsi_bind()
1648 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL, 0); in vc4_dsi_bind()
1656 list_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain); in vc4_dsi_bind()
1658 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_bind()
1670 if (dsi->bridge) in vc4_dsi_unbind()
1677 list_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain); in vc4_dsi_unbind()
1678 drm_encoder_cleanup(dsi->encoder); in vc4_dsi_unbind()
1688 struct device *dev = &pdev->dev; in vc4_dsi_dev_probe()
1693 return -ENOMEM; in vc4_dsi_dev_probe()
1696 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1697 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1698 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1699 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1706 struct device *dev = &pdev->dev; in vc4_dsi_dev_remove()
1709 component_del(&pdev->dev, &vc4_dsi_ops); in vc4_dsi_dev_remove()
1710 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()