268 	ret |= VC4_SET_FIELD((level >> 6),  in vc4_crtc_get_fifo_full_level_bits()
271 	return ret | VC4_SET_FIELD(level & 0x3f,  in vc4_crtc_get_fifo_full_level_bits()
345 		   VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,  in vc4_crtc_config_pv()
347 		   VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,  in vc4_crtc_config_pv()
351 		   VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,  in vc4_crtc_config_pv()
353 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,  in vc4_crtc_config_pv()
357 		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,  in vc4_crtc_config_pv()
359 		   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,  in vc4_crtc_config_pv()
362 		   VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,  in vc4_crtc_config_pv()
364 		   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));  in vc4_crtc_config_pv()
368 			   VC4_SET_FIELD(mode->crtc_vtotal -  in vc4_crtc_config_pv()
371 			   VC4_SET_FIELD(mode->crtc_vsync_end -  in vc4_crtc_config_pv()
375 			   VC4_SET_FIELD(mode->crtc_vsync_start -  in vc4_crtc_config_pv()
378 			   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));  in vc4_crtc_config_pv()
389 			   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,  in vc4_crtc_config_pv()
403 			   VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,  in vc4_crtc_config_pv()
408 		   VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |  in vc4_crtc_config_pv()
409 		   VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |  in vc4_crtc_config_pv()
413 		   VC4_SET_FIELD(vc4_encoder->clock_select,  in vc4_crtc_config_pv()