22 /* Enum for each of the V3D queues. */
77 	/* Short representation (e.g. 33, 41) of the V3D tech version
100 	/* virtual address bits from V3D to the MMU. */
103 	/* Number of V3D cores. */
162 v3d_has_csd(struct v3d_dev *v3d)  in v3d_has_csd()  argument
164 	return v3d->ver >= 41;  in v3d_has_csd()
167 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)  argument
171 	struct v3d_dev *v3d;  member
201 	/* v3d seqno for signaled() test */
212 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
213 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
215 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
216 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
218 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
219 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
221 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
222 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
229 	struct v3d_dev *v3d;  member
242 	/* v3d fence to be signaled by IRQ handler when the job is complete. */
369 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
383 void v3d_reset(struct v3d_dev *v3d);
384 void v3d_invalidate_caches(struct v3d_dev *v3d);
385 void v3d_clean_caches(struct v3d_dev *v3d);
388 int v3d_irq_init(struct v3d_dev *v3d);
389 void v3d_irq_enable(struct v3d_dev *v3d);
390 void v3d_irq_disable(struct v3d_dev *v3d);
391 void v3d_irq_reset(struct v3d_dev *v3d);
396 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
401 int v3d_sched_init(struct v3d_dev *v3d);
402 void v3d_sched_fini(struct v3d_dev *v3d);
407 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
408 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,