Lines Matching +full:tegra210 +full:- +full:pmc
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <soc/tegra/pmc.h>
37 stats->frames = 0; in tegra_dc_stats_reset()
38 stats->vblank = 0; in tegra_dc_stats_reset()
39 stats->underflow = 0; in tegra_dc_stats_reset()
40 stats->overflow = 0; in tegra_dc_stats_reset()
59 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
60 return plane->offset + offset; in tegra_plane_offset()
64 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
65 return plane->offset + offset; in tegra_plane_offset()
69 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
70 return plane->offset + offset; in tegra_plane_offset()
73 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
75 return plane->offset + offset; in tegra_plane_offset()
81 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
87 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
92 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
97 if (it.node == dev->of_node) in tegra_dc_has_output()
104 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
146 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()
147 inf.full -= dfixed_const(1); in compute_dda_inc()
175 /* disable blending for non-overlapping case */ in tegra_plane_setup_blending_legacy()
179 state = to_tegra_plane_state(plane->base.state); in tegra_plane_setup_blending_legacy()
181 if (state->opaque) { in tegra_plane_setup_blending_legacy()
183 * Since custom fix-weight blending isn't utilized and weight in tegra_plane_setup_blending_legacy()
200 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
202 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
203 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
225 if (state->blending[i].alpha && in tegra_plane_setup_blending_legacy()
226 state->blending[i].top) in tegra_plane_setup_blending_legacy()
230 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
232 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
233 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
243 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
244 state->blending[0].top) in tegra_plane_setup_blending_legacy()
247 if (state->blending[1].alpha && in tegra_plane_setup_blending_legacy()
248 state->blending[1].top) in tegra_plane_setup_blending_legacy()
254 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
267 if (!state->blending[0].top && state->blending[1].top) { in tegra_plane_setup_blending_legacy()
303 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); in tegra_plane_setup_blending()
311 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering()
313 if (window->src.w == window->dst.w) in tegra_plane_use_horizontal_filtering()
316 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
326 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering()
328 if (window->src.h == window->dst.h) in tegra_plane_use_vertical_filtering()
331 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
334 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
344 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window()
352 yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL); in tegra_dc_setup_window()
354 bpp = window->bits_per_pixel / 8; in tegra_dc_setup_window()
358 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
359 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
361 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); in tegra_dc_setup_window()
364 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); in tegra_dc_setup_window()
367 h_offset = window->src.x * bpp; in tegra_dc_setup_window()
368 v_offset = window->src.y; in tegra_dc_setup_window()
369 h_size = window->src.w * bpp; in tegra_dc_setup_window()
370 v_size = window->src.h; in tegra_dc_setup_window()
372 if (window->reflect_x) in tegra_dc_setup_window()
373 h_offset += (window->src.w - 1) * bpp; in tegra_dc_setup_window()
375 if (window->reflect_y) in tegra_dc_setup_window()
376 v_offset += window->src.h - 1; in tegra_dc_setup_window()
388 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); in tegra_dc_setup_window()
389 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); in tegra_dc_setup_window()
394 h_dda = compute_initial_dda(window->src.x); in tegra_dc_setup_window()
395 v_dda = compute_initial_dda(window->src.y); in tegra_dc_setup_window()
403 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
406 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
407 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
408 value = window->stride[1] << 16 | window->stride[0]; in tegra_dc_setup_window()
411 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
417 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
418 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
420 switch (window->tiling.mode) { in tegra_dc_setup_window()
437 switch (window->tiling.mode) { in tegra_dc_setup_window()
450 * No need to handle this here because ->atomic_check in tegra_dc_setup_window()
473 } else if (window->bits_per_pixel < 24) { in tegra_dc_setup_window()
477 if (window->reflect_x) in tegra_dc_setup_window()
480 if (window->reflect_y) in tegra_dc_setup_window()
485 * Enable horizontal 6-tap filter and set filtering in tegra_dc_setup_window()
512 * Enable vertical 2-tap filter and set filtering in tegra_dc_setup_window()
515 for (i = 0, k = 128; i < 16; i++, k -= 8) in tegra_dc_setup_window()
523 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
536 /* non-native formats */
616 unsigned int rotation = new_plane_state->rotation; in tegra_plane_atomic_check()
617 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check()
619 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check()
622 plane_state->peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
623 plane_state->avg_memory_bandwidth = 0; in tegra_plane_atomic_check()
626 if (!new_plane_state->crtc) { in tegra_plane_atomic_check()
627 plane_state->total_peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
631 err = tegra_plane_format(new_plane_state->fb->format->format, in tegra_plane_atomic_check()
632 &plane_state->format, in tegra_plane_atomic_check()
633 &plane_state->swap); in tegra_plane_atomic_check()
643 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
649 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
653 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
654 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
656 return -EINVAL; in tegra_plane_atomic_check()
665 if (tegra_fb_is_bottom_up(new_plane_state->fb)) in tegra_plane_atomic_check()
671 plane_state->reflect_x = true; in tegra_plane_atomic_check()
673 plane_state->reflect_x = false; in tegra_plane_atomic_check()
676 plane_state->reflect_y = true; in tegra_plane_atomic_check()
678 plane_state->reflect_y = false; in tegra_plane_atomic_check()
685 if (new_plane_state->fb->format->num_planes > 2) { in tegra_plane_atomic_check()
686 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { in tegra_plane_atomic_check()
687 DRM_ERROR("unsupported UV-plane configuration\n"); in tegra_plane_atomic_check()
688 return -EINVAL; in tegra_plane_atomic_check()
708 if (!old_state || !old_state->crtc) in tegra_plane_atomic_disable()
722 struct drm_framebuffer *fb = new_state->fb; in tegra_plane_atomic_update()
728 if (!new_state->crtc || !new_state->fb) in tegra_plane_atomic_update()
731 if (!new_state->visible) in tegra_plane_atomic_update()
735 window.src.x = new_state->src.x1 >> 16; in tegra_plane_atomic_update()
736 window.src.y = new_state->src.y1 >> 16; in tegra_plane_atomic_update()
737 window.src.w = drm_rect_width(&new_state->src) >> 16; in tegra_plane_atomic_update()
738 window.src.h = drm_rect_height(&new_state->src) >> 16; in tegra_plane_atomic_update()
739 window.dst.x = new_state->dst.x1; in tegra_plane_atomic_update()
740 window.dst.y = new_state->dst.y1; in tegra_plane_atomic_update()
741 window.dst.w = drm_rect_width(&new_state->dst); in tegra_plane_atomic_update()
742 window.dst.h = drm_rect_height(&new_state->dst); in tegra_plane_atomic_update()
743 window.bits_per_pixel = fb->format->cpp[0] * 8; in tegra_plane_atomic_update()
744 window.reflect_x = tegra_plane_state->reflect_x; in tegra_plane_atomic_update()
745 window.reflect_y = tegra_plane_state->reflect_y; in tegra_plane_atomic_update()
748 window.zpos = new_state->normalized_zpos; in tegra_plane_atomic_update()
749 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
750 window.format = tegra_plane_state->format; in tegra_plane_atomic_update()
751 window.swap = tegra_plane_state->swap; in tegra_plane_atomic_update()
753 for (i = 0; i < fb->format->num_planes; i++) { in tegra_plane_atomic_update()
754 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; in tegra_plane_atomic_update()
759 * function, so it's safe to ignore the V-plane pitch here. in tegra_plane_atomic_update()
762 window.stride[i] = fb->pitches[i]; in tegra_plane_atomic_update()
790 return 1 << drm->mode_config.num_crtc; in tegra_plane_get_possible_crtcs()
806 return ERR_PTR(-ENOMEM); in tegra_primary_plane_create()
809 plane->offset = 0xa00; in tegra_primary_plane_create()
810 plane->index = 0; in tegra_primary_plane_create()
811 plane->dc = dc; in tegra_primary_plane_create()
813 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
814 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
815 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
823 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_primary_plane_create()
831 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_primary_plane_create()
832 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_primary_plane_create()
834 err = drm_plane_create_rotation_property(&plane->base, in tegra_primary_plane_create()
841 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
844 return &plane->base; in tegra_primary_plane_create()
864 plane_state->peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
865 plane_state->avg_memory_bandwidth = 0; in tegra_cursor_atomic_check()
868 if (!new_plane_state->crtc) { in tegra_cursor_atomic_check()
869 plane_state->total_peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
874 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || in tegra_cursor_atomic_check()
875 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) in tegra_cursor_atomic_check()
876 return -EINVAL; in tegra_cursor_atomic_check()
879 if (new_plane_state->src_w != new_plane_state->src_h) in tegra_cursor_atomic_check()
880 return -EINVAL; in tegra_cursor_atomic_check()
882 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && in tegra_cursor_atomic_check()
883 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) in tegra_cursor_atomic_check()
884 return -EINVAL; in tegra_cursor_atomic_check()
899 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_update()
900 struct tegra_drm *tegra = plane->dev->dev_private; in tegra_cursor_atomic_update()
902 u64 dma_mask = *dc->dev->dma_mask; in tegra_cursor_atomic_update()
908 if (!new_state->crtc || !new_state->fb) in tegra_cursor_atomic_update()
915 if (!dc->soc->has_nvdisplay) in tegra_cursor_atomic_update()
918 switch (new_state->crtc_w) { in tegra_cursor_atomic_update()
937 new_state->crtc_w, new_state->crtc_h); in tegra_cursor_atomic_update()
941 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; in tegra_cursor_atomic_update()
945 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); in tegra_cursor_atomic_update()
958 if (dc->soc->has_nvdisplay) in tegra_cursor_atomic_update()
969 if (dc->soc->has_nvdisplay) { in tegra_cursor_atomic_update()
972 x = new_state->dst.x1; in tegra_cursor_atomic_update()
973 y = new_state->dst.y1; in tegra_cursor_atomic_update()
975 drm_rect_fp_to_int(&src, &new_state->src); in tegra_cursor_atomic_update()
977 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); in tegra_cursor_atomic_update()
980 value = (drm_rect_height(&src) & tegra->vmask) << 16 | in tegra_cursor_atomic_update()
981 (drm_rect_width(&src) & tegra->hmask); in tegra_cursor_atomic_update()
984 x = new_state->crtc_x; in tegra_cursor_atomic_update()
985 y = new_state->crtc_y; in tegra_cursor_atomic_update()
989 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); in tegra_cursor_atomic_update()
1002 if (!old_state || !old_state->crtc) in tegra_cursor_atomic_disable()
1005 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1036 return ERR_PTR(-ENOMEM); in tegra_dc_cursor_plane_create()
1043 * need to special-casing the cursor plane. in tegra_dc_cursor_plane_create()
1045 plane->index = 6; in tegra_dc_cursor_plane_create()
1046 plane->dc = dc; in tegra_dc_cursor_plane_create()
1048 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1062 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_cursor_plane_create()
1071 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); in tegra_dc_cursor_plane_create()
1072 drm_plane_create_zpos_immutable_property(&plane->base, 255); in tegra_dc_cursor_plane_create()
1074 return &plane->base; in tegra_dc_cursor_plane_create()
1084 /* non-native formats */
1167 return ERR_PTR(-ENOMEM); in tegra_dc_overlay_plane_create()
1169 plane->offset = 0xa00 + 0x200 * index; in tegra_dc_overlay_plane_create()
1170 plane->index = index; in tegra_dc_overlay_plane_create()
1171 plane->dc = dc; in tegra_dc_overlay_plane_create()
1173 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1174 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1187 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_overlay_plane_create()
1196 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_dc_overlay_plane_create()
1197 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_dc_overlay_plane_create()
1199 err = drm_plane_create_rotation_property(&plane->base, in tegra_dc_overlay_plane_create()
1206 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1209 return &plane->base; in tegra_dc_overlay_plane_create()
1218 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1219 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1221 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1222 for (j = 0; j < wgrp->num_windows; j++) { in tegra_dc_add_shared_planes()
1223 unsigned int index = wgrp->windows[j]; in tegra_dc_add_shared_planes()
1226 wgrp->index, in tegra_dc_add_shared_planes()
1236 plane->type = DRM_PLANE_TYPE_PRIMARY; in tegra_dc_add_shared_planes()
1258 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1269 while (i--) in tegra_dc_add_planes()
1289 if (crtc->state) in tegra_crtc_reset()
1290 tegra_crtc_atomic_destroy_state(crtc, crtc->state); in tegra_crtc_reset()
1292 __drm_atomic_helper_crtc_reset(crtc, &state->base); in tegra_crtc_reset()
1298 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_duplicate_state()
1305 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); in tegra_crtc_atomic_duplicate_state()
1306 copy->clk = state->clk; in tegra_crtc_atomic_duplicate_state()
1307 copy->pclk = state->pclk; in tegra_crtc_atomic_duplicate_state()
1308 copy->div = state->div; in tegra_crtc_atomic_duplicate_state()
1309 copy->planes = state->planes; in tegra_crtc_atomic_duplicate_state()
1311 return ©->base; in tegra_crtc_atomic_duplicate_state()
1540 struct drm_info_node *node = s->private; in tegra_dc_show_regs()
1541 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs()
1545 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1547 if (!dc->base.state->active) { in tegra_dc_show_regs()
1548 err = -EBUSY; in tegra_dc_show_regs()
1555 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, in tegra_dc_show_regs()
1560 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1566 struct drm_info_node *node = s->private; in tegra_dc_show_crc()
1567 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc()
1571 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1573 if (!dc->base.state->active) { in tegra_dc_show_crc()
1574 err = -EBUSY; in tegra_dc_show_crc()
1582 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1583 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1591 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1597 struct drm_info_node *node = s->private; in tegra_dc_show_stats()
1598 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats()
1600 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1601 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1602 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1603 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1605 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1606 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1607 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1608 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1622 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_late_register()
1627 root = crtc->debugfs_entry; in tegra_dc_late_register()
1632 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1634 if (!dc->debugfs_files) in tegra_dc_late_register()
1635 return -ENOMEM; in tegra_dc_late_register()
1638 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1640 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1648 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_early_unregister()
1651 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1652 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1653 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1661 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1662 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1665 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1711 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1718 value = ((mode->vsync_end - mode->vsync_start) << 16) | in tegra_dc_set_timings()
1719 ((mode->hsync_end - mode->hsync_start) << 0); in tegra_dc_set_timings()
1722 value = ((mode->vtotal - mode->vsync_end) << 16) | in tegra_dc_set_timings()
1723 ((mode->htotal - mode->hsync_end) << 0); in tegra_dc_set_timings()
1726 value = ((mode->vsync_start - mode->vdisplay) << 16) | in tegra_dc_set_timings()
1727 ((mode->hsync_start - mode->hdisplay) << 0); in tegra_dc_set_timings()
1730 value = (mode->vdisplay << 16) | mode->hdisplay; in tegra_dc_set_timings()
1737 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1746 * 0 on success or a negative error-code on failure.
1755 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1756 return -EINVAL; in tegra_dc_state_setup_clock()
1758 state->clk = clk; in tegra_dc_state_setup_clock()
1759 state->pclk = pclk; in tegra_dc_state_setup_clock()
1760 state->div = div; in tegra_dc_state_setup_clock()
1771 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1773 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1783 if (state->pclk > 0) { in tegra_dc_commit_state()
1784 err = clk_set_rate(state->clk, state->pclk); in tegra_dc_commit_state()
1786 dev_err(dc->dev, in tegra_dc_commit_state()
1788 state->pclk); in tegra_dc_commit_state()
1790 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1792 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1793 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1796 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1797 state->div); in tegra_dc_commit_state()
1798 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); in tegra_dc_commit_state()
1800 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1801 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; in tegra_dc_commit_state()
1838 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1839 return -ETIMEDOUT; in tegra_dc_wait_idle()
1856 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
1861 if (!crtc->state->active) { in tegra_crtc_update_memory_bandwidth()
1862 if (!old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
1873 icc_set_bw(tegra->icc_mem, 0, 0); in tegra_crtc_update_memory_bandwidth()
1874 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
1880 for_each_old_plane_in_state(old_crtc_state->state, plane, in tegra_crtc_update_memory_bandwidth()
1883 new_tegra_state = to_const_tegra_plane_state(plane->state); in tegra_crtc_update_memory_bandwidth()
1891 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
1894 new_avg_bw = new_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
1895 old_avg_bw = old_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
1897 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
1898 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
1901 * See the comment related to !crtc->state->active above, in tegra_crtc_update_memory_bandwidth()
1906 old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
1909 window.src.h = drm_rect_height(&plane->state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
1910 window.dst.h = drm_rect_height(&plane->state->dst); in tegra_crtc_update_memory_bandwidth()
1912 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
1913 old_window.dst.h = drm_rect_height(&old_plane_state->dst); in tegra_crtc_update_memory_bandwidth()
1930 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
1933 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
1935 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
1958 * these bits has the side-effect of stopping the display controller. in tegra_crtc_atomic_disable()
1972 if (dc->rgb) { in tegra_crtc_atomic_disable()
1979 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1982 spin_lock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
1984 if (crtc->state->event) { in tegra_crtc_atomic_disable()
1985 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_disable()
1986 crtc->state->event = NULL; in tegra_crtc_atomic_disable()
1989 spin_unlock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
1991 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
1993 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
1999 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in tegra_crtc_atomic_enable()
2000 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); in tegra_crtc_atomic_enable()
2005 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2007 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2012 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2013 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2015 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2027 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2074 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2086 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2097 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2105 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2122 if (crtc->state->event) { in tegra_crtc_atomic_begin()
2123 spin_lock_irqsave(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2126 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2128 drm_crtc_arm_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2130 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2132 crtc->state->event = NULL; in tegra_crtc_atomic_begin()
2145 value = dc_state->planes << 8 | GENERAL_UPDATE; in tegra_crtc_atomic_flush()
2149 value = dc_state->planes | GENERAL_ACT_REQ; in tegra_crtc_atomic_flush()
2156 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; in tegra_plane_is_cursor()
2157 const struct drm_format_info *fmt = state->fb->format; in tegra_plane_is_cursor()
2158 unsigned int src_w = drm_rect_width(&state->src) >> 16; in tegra_plane_is_cursor()
2159 unsigned int dst_w = drm_rect_width(&state->dst); in tegra_plane_is_cursor()
2161 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) in tegra_plane_is_cursor()
2164 if (soc->supports_cursor) in tegra_plane_is_cursor()
2167 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) in tegra_plane_is_cursor()
2183 if (!plane_state->visible || !plane_state->fb) in tegra_plane_overlap_mask()
2187 * Data-prefetch FIFO will easily help to overcome temporal memory in tegra_plane_overlap_mask()
2194 rect = plane_state->dst; in tegra_plane_overlap_mask()
2196 tegra = to_tegra_plane(other_state->plane); in tegra_plane_overlap_mask()
2198 if (!other_state->visible || !other_state->fb) in tegra_plane_overlap_mask()
2209 if (drm_rect_intersect(&rect, &other_state->dst)) in tegra_plane_overlap_mask()
2210 overlap_mask |= BIT(tegra->index); in tegra_plane_overlap_mask()
2231 * The nv-display uses shared planes. The algorithm below assumes in tegra_crtc_calculate_memory_bandwidth()
2232 * maximum 3 planes per-CRTC, this assumption isn't applicable to in tegra_crtc_calculate_memory_bandwidth()
2233 * the nv-display. Note that T124 support has additional windows, in tegra_crtc_calculate_memory_bandwidth()
2236 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2257 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) in tegra_crtc_calculate_memory_bandwidth()
2258 return -EINVAL; in tegra_crtc_calculate_memory_bandwidth()
2260 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2262 overlap_mask[tegra->index] = mask; in tegra_crtc_calculate_memory_bandwidth()
2272 * fetches from the planes simultaneously during of scan-out process. in tegra_crtc_calculate_memory_bandwidth()
2276 * A-and-B or A-and-C planes overlap. in tegra_crtc_calculate_memory_bandwidth()
2295 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { in tegra_crtc_calculate_memory_bandwidth()
2296 if (i == tegra->index) in tegra_crtc_calculate_memory_bandwidth()
2305 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; in tegra_crtc_calculate_memory_bandwidth()
2306 old_peak_bw = tegra_state->total_peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2323 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; in tegra_crtc_calculate_memory_bandwidth()
2371 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
2373 dc->stats.frames_total++; in tegra_dc_irq()
2374 dc->stats.frames++; in tegra_dc_irq()
2379 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
2381 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2382 dc->stats.vblank_total++; in tegra_dc_irq()
2383 dc->stats.vblank++; in tegra_dc_irq()
2388 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
2390 dc->stats.underflow_total++; in tegra_dc_irq()
2391 dc->stats.underflow++; in tegra_dc_irq()
2396 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2398 dc->stats.overflow_total++; in tegra_dc_irq()
2399 dc->stats.overflow++; in tegra_dc_irq()
2403 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2404 dc->stats.underflow_total++; in tegra_dc_irq()
2405 dc->stats.underflow++; in tegra_dc_irq()
2415 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2418 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2419 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2421 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2430 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_early_init()
2431 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_early_init()
2433 tegra->num_crtcs++; in tegra_dc_early_init()
2440 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_init()
2443 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_init()
2452 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2468 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2469 client->parent = &tegra->hub->client; in tegra_dc_init()
2471 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2472 if (!dc->syncpt) in tegra_dc_init()
2473 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2476 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2477 dev_err(client->dev, "failed to attach to domain: %d\n", err); in tegra_dc_init()
2481 if (dc->soc->wgrps) in tegra_dc_init()
2491 if (dc->soc->supports_cursor) { in tegra_dc_init()
2506 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2511 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2517 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2518 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2521 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2522 drm->mode_config.max_width = drm->mode_config.max_height = 16384; in tegra_dc_init()
2524 drm->mode_config.max_width = drm->mode_config.max_height = 4096; in tegra_dc_init()
2527 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2528 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2532 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2533 dev_name(dc->dev), dc); in tegra_dc_init()
2535 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2544 client->dev->dma_parms = client->host->dma_parms; in tegra_dc_init()
2556 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2570 client->dev->dma_parms = NULL; in tegra_dc_exit()
2572 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2576 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2581 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2588 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_late_exit()
2589 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_late_exit()
2591 tegra->num_crtcs--; in tegra_dc_late_exit()
2599 struct device *dev = client->dev; in tegra_dc_runtime_suspend()
2602 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2608 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2609 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2611 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2620 struct device *dev = client->dev; in tegra_dc_runtime_resume()
2629 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2630 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2631 dc->rst); in tegra_dc_runtime_resume()
2637 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2643 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2653 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2880 .compatible = "nvidia,tegra194-dc",
2883 .compatible = "nvidia,tegra186-dc",
2886 .compatible = "nvidia,tegra210-dc",
2889 .compatible = "nvidia,tegra124-dc",
2892 .compatible = "nvidia,tegra114-dc",
2895 .compatible = "nvidia,tegra30-dc",
2898 .compatible = "nvidia,tegra20-dc",
2912 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2914 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2929 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2938 dc->pipe = value; in tegra_dc_parse_dt()
2948 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2958 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2962 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
2965 return -EPROBE_DEFER; in tegra_dc_couple()
2968 dc->client.parent = &parent->client; in tegra_dc_couple()
2970 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
2978 u64 dma_mask = dma_get_mask(pdev->dev.parent); in tegra_dc_probe()
2982 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); in tegra_dc_probe()
2984 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); in tegra_dc_probe()
2988 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2990 return -ENOMEM; in tegra_dc_probe()
2992 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2994 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2995 dc->dev = &pdev->dev; in tegra_dc_probe()
3005 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3006 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3007 dev_err(&pdev->dev, "failed to get clock\n"); in tegra_dc_probe()
3008 return PTR_ERR(dc->clk); in tegra_dc_probe()
3011 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3012 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3013 dev_err(&pdev->dev, "failed to get reset\n"); in tegra_dc_probe()
3014 return PTR_ERR(dc->rst); in tegra_dc_probe()
3018 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3024 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3030 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3032 if (dc->soc->has_powergate) { in tegra_dc_probe()
3033 if (dc->pipe == 0) in tegra_dc_probe()
3034 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3036 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3038 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3041 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3042 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3043 return PTR_ERR(dc->regs); in tegra_dc_probe()
3045 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3046 if (dc->irq < 0) in tegra_dc_probe()
3047 return -ENXIO; in tegra_dc_probe()
3050 if (err < 0 && err != -ENODEV) { in tegra_dc_probe()
3053 if (err == -EPROBE_DEFER) in tegra_dc_probe()
3056 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", in tegra_dc_probe()
3062 pm_runtime_enable(&pdev->dev); in tegra_dc_probe()
3064 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3065 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3066 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3068 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3070 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dc_probe()
3078 pm_runtime_disable(&pdev->dev); in tegra_dc_probe()
3089 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
3091 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", in tegra_dc_remove()
3098 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); in tegra_dc_remove()
3102 pm_runtime_disable(&pdev->dev); in tegra_dc_remove()
3109 .name = "tegra-dc",