Lines Matching +full:lvds +full:- +full:encoder
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
42 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) in sun4i_tcon_get_connector() argument
47 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
49 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
58 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder) in sun4i_tcon_get_pixel_depth() argument
63 connector = sun4i_tcon_get_connector(encoder); in sun4i_tcon_get_pixel_depth()
65 return -EINVAL; in sun4i_tcon_get_pixel_depth()
67 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
68 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
69 return -EINVAL; in sun4i_tcon_get_pixel_depth()
71 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
80 return -EINVAL; in sun4i_tcon_get_pixel_depth()
90 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
97 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
101 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
118 const struct drm_encoder *encoder) in sun4i_tcon_setup_lvds_phy() argument
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
142 const struct drm_encoder *encoder) in sun6i_tcon_setup_lvds_phy() argument
146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
162 if (sun4i_tcon_get_pixel_depth(encoder) == 18) in sun6i_tcon_setup_lvds_phy()
167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
173 const struct drm_encoder *encoder, in sun4i_tcon_lvds_set_status() argument
177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
180 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
181 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
189 const struct drm_encoder *encoder, in sun4i_tcon_set_status() argument
195 switch (encoder->encoder_type) { in sun4i_tcon_set_status()
208 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); in sun4i_tcon_set_status()
213 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
220 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
250 struct sun4i_drv *drv = drm->dev_private; in sun4i_get_tcon0()
253 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
254 if (tcon->id == 0) in sun4i_get_tcon0()
257 dev_warn(drm->dev, in sun4i_get_tcon0()
264 const struct drm_encoder *encoder) in sun4i_tcon_set_mux() argument
266 int ret = -ENOTSUPP; in sun4i_tcon_set_mux()
268 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
269 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
271 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n", in sun4i_tcon_set_mux()
272 encoder->name, encoder->crtc->name, ret); in sun4i_tcon_set_mux()
278 int delay = mode->vtotal - mode->vdisplay; in sun4i_tcon_get_clk_delay()
280 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon_get_clk_delay()
284 delay -= 2; in sun4i_tcon_get_clk_delay()
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
301 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_common()
302 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_common()
321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
333 if (connector->display_info.bpc == 6) in sun4i_tcon0_mode_set_dithering()
336 if (connector->display_info.num_bus_formats == 1) in sun4i_tcon0_mode_set_dithering()
337 bus_format = connector->display_info.bus_formats[0]; in sun4i_tcon0_mode_set_dithering()
354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
358 const struct drm_encoder *encoder, in sun4i_tcon0_mode_set_cpu() argument
362 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); in sun4i_tcon0_mode_set_cpu()
363 struct mipi_dsi_device *device = dsi->device; in sun4i_tcon0_mode_set_cpu()
364 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); in sun4i_tcon0_mode_set_cpu()
365 u8 lanes = device->lanes; in sun4i_tcon0_mode_set_cpu()
369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_cpu()
377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
398 block_space = mode->htotal * bpp / (tcon_div * lanes); in sun4i_tcon0_mode_set_cpu()
399 block_space -= mode->hdisplay + 40; in sun4i_tcon0_mode_set_cpu()
401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
403 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); in sun4i_tcon0_mode_set_cpu()
405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
406 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); in sun4i_tcon0_mode_set_cpu()
408 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); in sun4i_tcon0_mode_set_cpu()
409 start_delay = start_delay * mode->crtc_htotal * 149; in sun4i_tcon0_mode_set_cpu()
410 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; in sun4i_tcon0_mode_set_cpu()
411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
429 const struct drm_encoder *encoder, in sun4i_tcon0_mode_set_lvds() argument
436 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
438 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
439 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_lvds()
447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
455 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_lvds()
457 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_lvds()
460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
461 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | in sun4i_tcon0_mode_set_lvds()
468 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_lvds()
470 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_lvds()
473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
474 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_lvds()
478 if (sun4i_tcon_get_pixel_depth(encoder) == 24) in sun4i_tcon0_mode_set_lvds()
483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
486 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) in sun4i_tcon0_mode_set_lvds()
489 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) in sun4i_tcon0_mode_set_lvds()
492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
504 const struct drm_encoder *encoder, in sun4i_tcon0_mode_set_rgb() argument
507 struct drm_connector *connector = sun4i_tcon_get_connector(encoder); in sun4i_tcon0_mode_set_rgb()
508 const struct drm_display_info *info = &connector->display_info; in sun4i_tcon0_mode_set_rgb()
513 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
516 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
532 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
534 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_rgb()
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
538 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon0_mode_set_rgb()
545 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
547 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_rgb()
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
551 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_rgb()
555 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
556 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
563 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon0_mode_set_rgb()
566 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon0_mode_set_rgb()
569 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) in sun4i_tcon0_mode_set_rgb()
572 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) in sun4i_tcon0_mode_set_rgb()
575 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
583 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
588 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
598 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
601 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
605 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
610 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon1_mode_set()
614 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
619 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
620 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
621 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
624 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
625 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
626 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
629 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
630 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
631 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
634 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
636 mode->htotal, bp); in sun4i_tcon1_mode_set()
637 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
638 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon1_mode_set()
641 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
643 mode->crtc_vtotal, bp); in sun4i_tcon1_mode_set()
658 vtotal = mode->vtotal; in sun4i_tcon1_mode_set()
659 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) in sun4i_tcon1_mode_set()
663 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
668 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
669 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
671 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
676 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
679 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
682 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
685 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
690 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
693 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
696 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
700 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
706 const struct drm_encoder *encoder, in sun4i_tcon_mode_set() argument
709 switch (encoder->encoder_type) { in sun4i_tcon_mode_set()
712 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); in sun4i_tcon_mode_set()
715 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
718 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); in sun4i_tcon_mode_set()
719 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
724 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
727 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); in sun4i_tcon_mode_set()
737 spin_lock_irqsave(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
738 if (scrtc->event) { in sun4i_tcon_finish_page_flip()
739 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); in sun4i_tcon_finish_page_flip()
740 drm_crtc_vblank_put(&scrtc->crtc); in sun4i_tcon_finish_page_flip()
741 scrtc->event = NULL; in sun4i_tcon_finish_page_flip()
743 spin_unlock_irqrestore(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
749 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
750 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
751 struct sunxi_engine *engine = scrtc->engine; in sun4i_tcon_handler()
754 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
761 drm_crtc_handle_vblank(&scrtc->crtc); in sun4i_tcon_handler()
765 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
771 if (engine->ops->vblank_quirk) in sun4i_tcon_handler()
772 engine->ops->vblank_quirk(engine); in sun4i_tcon_handler()
780 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
781 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
783 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
785 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
787 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
788 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
789 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
791 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
794 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
796 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
797 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
798 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
800 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
809 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
810 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
852 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
854 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
856 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
860 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
861 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
862 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
865 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
866 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
892 struct sunxi_engine *engine = ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
897 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
921 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_find_engine_traverse()
922 if (remote == engine->node) in sun4i_tcon_find_engine_traverse()
936 reg -= 1; in sun4i_tcon_find_engine_traverse()
964 int ret = -EINVAL; in sun4i_tcon_of_get_id_from_port()
995 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_get_engine_by_id()
996 if (engine->id == id) in sun4i_tcon_get_engine_by_id()
999 return ERR_PTR(-EINVAL); in sun4i_tcon_get_engine_by_id()
1007 remote = of_graph_get_remote_node(node, 0, -1); in sun4i_tcon_connected_to_tcon_top()
1027 list_for_each(pos, &drv->tcon_list) in sun4i_tcon_get_index()
1074 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine()
1088 * TCONs than engines (R40) or TCONs with non-consecutive ids. in sun4i_tcon_find_engine()
1116 struct sun4i_drv *drv = drm->dev_private; in sun4i_tcon_bind()
1124 engine = sun4i_tcon_find_engine(drv, dev->of_node); in sun4i_tcon_bind()
1127 return -EPROBE_DEFER; in sun4i_tcon_bind()
1132 return -ENOMEM; in sun4i_tcon_bind()
1134 tcon->drm = drm; in sun4i_tcon_bind()
1135 tcon->dev = dev; in sun4i_tcon_bind()
1136 tcon->id = engine->id; in sun4i_tcon_bind()
1137 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1139 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1140 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1142 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1145 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1160 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1166 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1169 * nodes without the LVDS reset properties. in sun4i_tcon_bind()
1171 * If the property is missing, just disable LVDS, and in sun4i_tcon_bind()
1174 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1175 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1177 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1178 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1180 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1187 * nodes without the LVDS reset properties. in sun4i_tcon_bind()
1189 * If the property is missing, just disable LVDS, and in sun4i_tcon_bind()
1192 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1193 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1194 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1195 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1198 dev_err(dev, "Couldn't get the LVDS PLL\n"); in sun4i_tcon_bind()
1199 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1207 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1208 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); in sun4i_tcon_bind()
1209 dev_warn(dev, "LVDS output disabled\n"); in sun4i_tcon_bind()
1230 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1244 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1245 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1247 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1251 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1253 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1254 * just probe the LVDS connector. Otherwise, just probe RGB as in sun4i_tcon_bind()
1257 remote = of_graph_get_remote_node(dev->of_node, 1, 0); in sun4i_tcon_bind()
1258 if (of_device_is_compatible(remote, "panel-lvds")) in sun4i_tcon_bind()
1262 ret = -EINVAL; in sun4i_tcon_bind()
1271 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1282 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1284 tcon->id); in sun4i_tcon_bind()
1285 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1287 tcon->id); in sun4i_tcon_bind()
1290 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1295 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1300 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1309 list_del(&tcon->list); in sun4i_tcon_unbind()
1310 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1322 struct device_node *node = pdev->dev.of_node; in sun4i_tcon_probe()
1328 quirks = of_device_get_match_data(&pdev->dev); in sun4i_tcon_probe()
1331 if (quirks->has_channel_0) { in sun4i_tcon_probe()
1333 if (ret == -EPROBE_DEFER) in sun4i_tcon_probe()
1337 return component_add(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_probe()
1342 component_del(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_remove()
1349 const struct drm_encoder *encoder) in sun4i_a10_tcon_set_mux() argument
1351 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun4i_a10_tcon_set_mux()
1355 return -EINVAL; in sun4i_a10_tcon_set_mux()
1357 switch (encoder->encoder_type) { in sun4i_a10_tcon_set_mux()
1363 return -EINVAL; in sun4i_a10_tcon_set_mux()
1366 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun4i_a10_tcon_set_mux()
1367 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1373 const struct drm_encoder *encoder) in sun5i_a13_tcon_set_mux() argument
1377 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) in sun5i_a13_tcon_set_mux()
1385 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1389 const struct drm_encoder *encoder) in sun6i_tcon_set_mux() argument
1391 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun6i_tcon_set_mux()
1395 return -EINVAL; in sun6i_tcon_set_mux()
1397 switch (encoder->encoder_type) { in sun6i_tcon_set_mux()
1404 return -EINVAL; in sun6i_tcon_set_mux()
1407 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun6i_tcon_set_mux()
1408 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1414 const struct drm_encoder *encoder) in sun8i_r40_tcon_tv_set_mux() argument
1422 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1424 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1429 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1431 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1436 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1439 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { in sun8i_r40_tcon_tv_set_mux()
1440 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); in sun8i_r40_tcon_tv_set_mux()
1442 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1448 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1450 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1549 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1550 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1551 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1552 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1553 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1554 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1555 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1556 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1557 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1558 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1559 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1560 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1561 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1562 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1563 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1573 .name = "sun4i-tcon",
1579 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");