Lines Matching +full:0 +full:xffff
81 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
82 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
83 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
84 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
88 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
89 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
97 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
98 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
99 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
100 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
101 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
102 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
103 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
104 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
105 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
106 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
107 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
108 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
109 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
117 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
118 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
119 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
120 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
121 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
122 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
123 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
124 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
125 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
126 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
127 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
131 { .base = 0x00, .phy = &rk3036_win0_data,
133 { .base = 0x00, .phy = &rk3036_win1_data,
147 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
148 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0),
149 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4),
150 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8),
154 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
155 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
156 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
157 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
161 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
165 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
166 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
167 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
168 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
169 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
170 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
171 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
187 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
188 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
189 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
190 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
191 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
192 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
193 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
194 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
195 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
196 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
200 { .base = 0x00, .phy = &rk3036_win0_data,
202 { .base = 0x00, .phy = &rk3126_win1_data,
217 0, 0,
219 0,
221 0, 0,
228 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0),
229 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0),
230 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0),
231 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0),
235 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
236 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
237 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14),
238 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8),
239 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7),
240 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6),
241 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0),
245 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
246 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0),
247 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
248 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0),
252 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
253 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
254 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
255 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
256 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
257 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
261 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
262 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
263 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
264 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
272 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0),
273 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1),
274 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12),
275 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0),
276 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0),
277 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0),
278 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0),
279 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0),
280 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0),
281 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16),
282 .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2),
283 .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),
284 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
291 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0),
292 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4),
293 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12),
294 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0),
295 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0),
296 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0),
297 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0),
298 .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2),
299 .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),
300 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
307 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4),
308 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0),
309 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5),
310 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20),
311 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0),
312 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0),
313 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0),
314 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0),
315 .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2),
316 .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),
317 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
321 { .base = 0x00, .phy = &px30_win0_data,
323 { .base = 0x00, .phy = &px30_win1_data,
325 { .base = 0x00, .phy = &px30_win2_data,
341 { .base = 0x00, .phy = &px30_win1_data,
357 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
358 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
359 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
360 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
368 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
369 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4),
370 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19),
371 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
372 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
373 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
374 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
375 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
376 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
377 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
378 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
379 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0),
386 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
387 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7),
388 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23),
389 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
390 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
391 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
392 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
393 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
394 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
395 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
396 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
397 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1),
404 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
405 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10),
406 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27),
407 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
408 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
409 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
410 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
411 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
412 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2),
416 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
417 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
418 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
419 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
423 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
427 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
428 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
429 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
430 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11),
431 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10),
432 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
433 .dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9),
434 .dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31),
435 .data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25),
439 { .base = 0x00, .phy = &rk3066_win0_data,
441 { .base = 0x00, .phy = &rk3066_win1_data,
443 { .base = 0x00, .phy = &rk3066_win2_data,
461 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
462 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
463 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
464 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
478 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
479 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
480 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
481 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
489 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
490 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
491 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
492 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
493 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
494 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
495 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
496 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
497 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
498 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18),
499 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0),
500 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
507 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
508 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
509 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
511 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
512 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
513 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
514 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
515 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19),
516 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1),
517 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29),
521 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
522 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
523 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
524 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
528 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
532 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
533 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
534 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
535 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
536 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27),
537 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
538 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
539 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24),
540 .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
541 .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
542 .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
546 { .base = 0x00, .phy = &rk3188_win0_data,
548 { .base = 0x00, .phy = &rk3188_win1_data,
566 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
567 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
568 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
569 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
583 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
584 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
585 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
586 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
587 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
588 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
589 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
590 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
591 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
592 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
593 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
594 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
595 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
596 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
597 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
598 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
599 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
600 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
601 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
602 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
603 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
608 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
609 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
610 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
611 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
619 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
620 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
621 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
622 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
623 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
624 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
625 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
626 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
627 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
628 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
629 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
630 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
631 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
638 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
639 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
640 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
641 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
642 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
643 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
644 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
645 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
646 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
647 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
651 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
652 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
653 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
654 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
655 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
656 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
660 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
661 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
662 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
663 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
664 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
668 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
669 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
670 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
671 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
672 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
673 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
674 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
675 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
676 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
677 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
678 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
679 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
680 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
690 { .base = 0x00, .phy = &rk3288_win01_data,
692 { .base = 0x40, .phy = &rk3288_win01_data,
694 { .base = 0x00, .phy = &rk3288_win23_data,
696 { .base = 0x50, .phy = &rk3288_win23_data,
710 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
711 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
712 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
713 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
730 0, 0,
732 0,
734 0, 0, 0, 0, 0, 0, 0,
741 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
742 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
743 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
744 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
745 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
753 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
754 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
755 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
756 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
757 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
758 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0),
759 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0),
760 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0),
761 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0),
762 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0),
763 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0),
764 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16),
765 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
766 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0),
767 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0),
774 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
775 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
776 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
777 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
778 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
779 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
780 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
781 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
782 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
783 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
784 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
788 { .base = 0x00, .phy = &rk3368_win01_data,
790 { .base = 0x40, .phy = &rk3368_win01_data,
792 { .base = 0x00, .phy = &rk3368_win23_data,
794 { .base = 0x50, .phy = &rk3368_win23_data,
799 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
800 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
801 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
802 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
803 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
804 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
805 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
806 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
807 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
808 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
809 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
810 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
814 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11),
831 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
832 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
833 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0),
834 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0),
835 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0),
850 .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
851 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
852 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
853 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
854 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
855 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
856 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
857 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
858 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
859 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
860 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
861 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
862 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
863 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
864 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
865 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
870 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
871 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16),
872 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0),
873 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16),
874 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0),
875 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16),
876 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0),
877 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16),
878 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0),
879 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0),
880 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0),
881 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0),
888 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
889 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) },
890 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data,
891 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) },
892 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data },
893 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data },
902 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
903 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
904 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
905 .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
906 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
907 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
908 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
909 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
910 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
911 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
912 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
913 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
914 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
923 { .base = 0x00, .phy = &rk3399_win01_data,
925 { .base = 0x40, .phy = &rk3288_win01_data,
927 { .base = 0x00, .phy = &rk3288_win23_data,
929 { .base = 0x50, .phy = &rk3288_win23_data,
934 .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
935 .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
936 .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
937 .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
938 .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
939 .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
940 .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
958 { .base = 0x00, .phy = &rk3368_win01_data,
960 { .base = 0x00, .phy = &rk3368_win23_data,
965 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
966 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)},
967 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data },
983 { .base = 0x00, .phy = &rk3288_win01_data,
985 { .base = 0x40, .phy = &rk3288_win01_data,
1002 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1003 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
1004 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1005 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
1006 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1007 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1011 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
1012 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
1013 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
1014 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
1015 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
1016 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
1017 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
1018 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
1019 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
1020 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
1021 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
1022 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
1026 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
1030 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22),
1031 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
1032 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
1033 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
1034 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
1035 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
1036 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
1037 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
1038 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
1044 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
1045 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
1046 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0),
1047 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0),
1048 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
1052 { .base = 0xd0, .phy = &rk3368_win01_data,
1054 { .base = 0x1d0, .phy = &rk3368_win01_data,
1056 { .base = 0x2d0, .phy = &rk3368_win01_data,
1119 return 0; in vop_remove()