Lines Matching full:dsi
334 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
336 writel(val, dsi->base + reg); in dsi_write()
339 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) in dsi_read() argument
341 return readl(dsi->base + reg); in dsi_read()
344 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, in dsi_update_bits() argument
347 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); in dsi_update_bits()
350 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
359 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
361 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
364 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
366 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
369 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
375 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
377 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
383 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
385 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
390 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
393 if (dsi->phy) in dw_mipi_dsi_phy_init()
408 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
410 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
412 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
414 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
418 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
420 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
424 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
430 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
432 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
436 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
439 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
440 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
441 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
442 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
450 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
452 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
453 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
455 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
458 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
460 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
463 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
467 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
470 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
475 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
476 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
477 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
478 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
479 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
480 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
481 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
482 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
483 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
484 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
485 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
486 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
488 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
489 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
490 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
491 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
492 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
493 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
494 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
495 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
496 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
497 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
499 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
506 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
509 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
511 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
515 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
516 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
521 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
523 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
531 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
543 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
544 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
546 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
548 dsi->format); in dw_mipi_dsi_get_lane_mbps()
559 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
564 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
567 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
568 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
569 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
574 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
617 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
618 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
619 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
620 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
622 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
714 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
716 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
717 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
718 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
720 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
721 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
722 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
724 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
725 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
726 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
729 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
732 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
733 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
742 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
744 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
760 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
768 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
771 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
772 &dsi->encoder); in dw_mipi_dsi_encoder_enable()
776 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_encoder_enable()
777 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
778 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_encoder_enable()
785 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
787 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
791 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
792 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
793 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
795 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
800 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_disable() local
802 if (dsi->slave) in dw_mipi_dsi_encoder_disable()
803 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_encoder_disable()
804 pm_runtime_put(dsi->dev); in dw_mipi_dsi_encoder_disable()
814 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
817 struct drm_encoder *encoder = &dsi->encoder; in rockchip_dsi_drm_create_encoder()
821 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
835 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
840 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
842 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
851 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
898 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
904 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
909 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
915 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
920 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
924 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
926 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
930 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
931 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
936 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
937 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
941 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
951 * commands over DSI. in dw_mipi_dsi_rockchip_bind()
953 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
955 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
959 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
960 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
961 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
963 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
965 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
971 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); in dw_mipi_dsi_rockchip_bind()
984 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
986 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
989 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
991 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1002 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
1006 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1008 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1009 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1010 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1014 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1015 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1017 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1019 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1024 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1043 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1046 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1050 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1052 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1053 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1054 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1091 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init() local
1094 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1096 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1097 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1098 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1102 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1103 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1105 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1109 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1110 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1114 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1116 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1120 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1121 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1122 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1130 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1132 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1133 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1134 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1141 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit() local
1143 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1145 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1146 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1147 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1155 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure() local
1162 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1163 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1170 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on() local
1173 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1174 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1176 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1178 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1179 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1183 ret = pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1185 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1189 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1191 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1195 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1197 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1201 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1203 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1208 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1209 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1211 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1220 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); in dw_mipi_dsi_dphy_power_on()
1221 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_dphy_power_on()
1223 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); in dw_mipi_dsi_dphy_power_on()
1224 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); in dw_mipi_dsi_dphy_power_on()
1225 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); in dw_mipi_dsi_dphy_power_on()
1228 dw_mipi_dsi_phy_write(dsi, 0x0, 0); in dw_mipi_dsi_dphy_power_on()
1230 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1231 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1236 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1238 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1240 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1242 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1248 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off() local
1251 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1253 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1257 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1258 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1260 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1263 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1264 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1266 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1283 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1290 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1291 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1295 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1296 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1297 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); in dw_mipi_dsi_rockchip_probe()
1298 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1304 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1311 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1312 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1317 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1318 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1319 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1324 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1325 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1326 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1331 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1332 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1333 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1338 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1340 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1348 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1349 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1350 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1351 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1358 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1359 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1360 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1361 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1367 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1368 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1370 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1373 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1374 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1375 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1376 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1377 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1378 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1379 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1381 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1383 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1384 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1386 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1389 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1394 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1395 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1396 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1406 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1412 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1414 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1459 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init() local
1465 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1467 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1469 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1471 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1479 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on() local
1482 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); in rk3399_dphy_tx1rx1_power_on()
1485 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1487 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1490 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1492 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1496 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1498 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1503 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in rk3399_dphy_tx1rx1_power_on()
1507 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1508 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1518 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off() local
1520 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1578 .compatible = "rockchip,px30-mipi-dsi",
1581 .compatible = "rockchip,rk3288-mipi-dsi",
1584 .compatible = "rockchip,rk3399-mipi-dsi",
1596 .name = "dw-mipi-dsi-rockchip",