Lines Matching full:dphy
253 /* optional external dphy */
260 struct phy *dphy; member
280 /* The table is based on 27MHz DPHY pll reference clock. */
560 "DPHY clock frequency is out of range\n"); in dw_mipi_dsi_get_lane_mbps()
622 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
1069 * Nothing to do when used as a dphy. in dw_mipi_dsi_rockchip_dphy_bind()
1081 /* Nothing to do when used as a dphy. */ in dw_mipi_dsi_rockchip_dphy_unbind()
1316 /* try to get a possible external dphy */ in dw_mipi_dsi_rockchip_probe()
1317 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1320 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); in dw_mipi_dsi_rockchip_probe()
1383 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1384 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1386 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1389 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1463 * Assume ISP0 is supplied by the RX0 dphy. in rk3399_dphy_tx1rx1_init()
1506 /* Enable dphy lanes */ in rk3399_dphy_tx1rx1_power_on()