Lines Matching refs:link_width_cntl
2032 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2055 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2056 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2057 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2058 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2059 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2060 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2061 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2063 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2065 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2067 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2068 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2101 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2104 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2106 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2107 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()