Lines Matching +full:vco +full:- +full:offset
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
74 switch (rdev->family) { in radeon_uvd_init()
134 return -EINVAL; in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init()
143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init()
149 r = radeon_ucode_validate(rdev->uvd_fw); in radeon_uvd_init()
153 rdev->uvd.fw_header_present = true; in radeon_uvd_init()
155 family_id = (__force u32)(hdr->ucode_version) & 0xff; in radeon_uvd_init()
156 version_major = (le32_to_cpu((__force __le32)(hdr->ucode_version)) in radeon_uvd_init()
158 version_minor = (le32_to_cpu((__force __le32)(hdr->ucode_version)) in radeon_uvd_init()
168 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
178 r = request_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev); in radeon_uvd_init()
180 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
186 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + in radeon_uvd_init()
188 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
191 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
193 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); in radeon_uvd_init()
197 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_init()
199 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
200 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); in radeon_uvd_init()
204 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, in radeon_uvd_init()
205 &rdev->uvd.gpu_addr); in radeon_uvd_init()
207 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
208 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
209 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); in radeon_uvd_init()
213 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); in radeon_uvd_init()
215 dev_err(rdev->dev, "(%d) UVD map failed\n", r); in radeon_uvd_init()
219 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
221 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()
222 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_init()
223 rdev->uvd.filp[i] = NULL; in radeon_uvd_init()
224 rdev->uvd.img_size[i] = 0; in radeon_uvd_init()
234 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_fini()
237 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_fini()
239 radeon_bo_kunmap(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
240 radeon_bo_unpin(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
241 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
244 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_fini()
246 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); in radeon_uvd_fini()
248 release_firmware(rdev->uvd_fw); in radeon_uvd_fini()
255 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_suspend()
258 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()
259 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); in radeon_uvd_suspend()
275 rdev->uvd.filp[i] = NULL; in radeon_uvd_suspend()
276 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_suspend()
288 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_resume()
289 return -EINVAL; in radeon_uvd_resume()
291 memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); in radeon_uvd_resume()
293 size = radeon_bo_size(rdev->uvd.vcpu_bo); in radeon_uvd_resume()
294 size -= rdev->uvd_fw->size; in radeon_uvd_resume()
296 ptr = rdev->uvd.cpu_addr; in radeon_uvd_resume()
297 ptr += rdev->uvd_fw->size; in radeon_uvd_resume()
309 for (i = 0; i < rbo->placement.num_placement; ++i) { in radeon_uvd_force_into_uvd_segment()
310 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
311 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
319 if (rbo->placement.num_placement > 1) in radeon_uvd_force_into_uvd_segment()
323 rbo->placements[1] = rbo->placements[0]; in radeon_uvd_force_into_uvd_segment()
324 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
325 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
326 rbo->placement.num_placement++; in radeon_uvd_force_into_uvd_segment()
327 rbo->placement.num_busy_placement++; in radeon_uvd_force_into_uvd_segment()
333 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()
334 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); in radeon_uvd_free_handles()
335 if (handle != 0 && rdev->uvd.filp[i] == filp) { in radeon_uvd_free_handles()
350 rdev->uvd.filp[i] = NULL; in radeon_uvd_free_handles()
351 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_free_handles()
425 return -EINVAL; in radeon_uvd_cs_msg_decode()
430 return -EINVAL; in radeon_uvd_cs_msg_decode()
436 return -EINVAL; in radeon_uvd_cs_msg_decode()
456 if (p->rdev->family >= CHIP_PALM) in radeon_uvd_validate_codec()
463 return -EINVAL; in radeon_uvd_validate_codec()
468 unsigned offset, unsigned buf_sizes[]) in radeon_uvd_cs_msg() argument
477 if (offset & 0x3F) { in radeon_uvd_cs_msg()
479 return -EINVAL; in radeon_uvd_cs_msg()
482 f = dma_resv_excl_fence(bo->tbo.base.resv); in radeon_uvd_cs_msg()
497 msg = ptr + offset; in radeon_uvd_cs_msg()
504 return -EINVAL; in radeon_uvd_cs_msg()
518 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
519 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { in radeon_uvd_cs_msg()
521 return -EINVAL; in radeon_uvd_cs_msg()
524 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { in radeon_uvd_cs_msg()
525 p->rdev->uvd.filp[i] = p->filp; in radeon_uvd_cs_msg()
526 p->rdev->uvd.img_size[i] = img_size; in radeon_uvd_cs_msg()
532 return -EINVAL; in radeon_uvd_cs_msg()
544 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
545 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { in radeon_uvd_cs_msg()
546 if (p->rdev->uvd.filp[i] != p->filp) { in radeon_uvd_cs_msg()
548 return -EINVAL; in radeon_uvd_cs_msg()
555 return -ENOENT; in radeon_uvd_cs_msg()
559 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()
560 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); in radeon_uvd_cs_msg()
567 return -EINVAL; in radeon_uvd_cs_msg()
571 return -EINVAL; in radeon_uvd_cs_msg()
580 unsigned idx, cmd, offset; in radeon_uvd_cs_reloc() local
584 relocs_chunk = p->chunk_relocs; in radeon_uvd_cs_reloc()
585 offset = radeon_get_ib_value(p, data0); in radeon_uvd_cs_reloc()
587 if (idx >= relocs_chunk->length_dw) { in radeon_uvd_cs_reloc()
589 idx, relocs_chunk->length_dw); in radeon_uvd_cs_reloc()
590 return -EINVAL; in radeon_uvd_cs_reloc()
593 reloc = &p->relocs[(idx / 4)]; in radeon_uvd_cs_reloc()
594 start = reloc->gpu_offset; in radeon_uvd_cs_reloc()
595 end = start + radeon_bo_size(reloc->robj); in radeon_uvd_cs_reloc()
596 start += offset; in radeon_uvd_cs_reloc()
598 p->ib.ptr[data0] = start & 0xFFFFFFFF; in radeon_uvd_cs_reloc()
599 p->ib.ptr[data1] = start >> 32; in radeon_uvd_cs_reloc()
601 cmd = radeon_get_ib_value(p, p->idx) >> 1; in radeon_uvd_cs_reloc()
605 DRM_ERROR("invalid reloc offset %X!\n", offset); in radeon_uvd_cs_reloc()
606 return -EINVAL; in radeon_uvd_cs_reloc()
608 if ((end - start) < buf_sizes[cmd]) { in radeon_uvd_cs_reloc()
610 (unsigned)(end - start), buf_sizes[cmd]); in radeon_uvd_cs_reloc()
611 return -EINVAL; in radeon_uvd_cs_reloc()
616 return -EINVAL; in radeon_uvd_cs_reloc()
619 if ((start >> 28) != ((end - 1) >> 28)) { in radeon_uvd_cs_reloc()
620 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", in radeon_uvd_cs_reloc()
622 return -EINVAL; in radeon_uvd_cs_reloc()
627 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { in radeon_uvd_cs_reloc()
628 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", in radeon_uvd_cs_reloc()
630 return -EINVAL; in radeon_uvd_cs_reloc()
635 DRM_ERROR("More than one message in a UVD-IB!\n"); in radeon_uvd_cs_reloc()
636 return -EINVAL; in radeon_uvd_cs_reloc()
639 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); in radeon_uvd_cs_reloc()
644 return -EINVAL; in radeon_uvd_cs_reloc()
658 p->idx++; in radeon_uvd_cs_reg()
659 for (i = 0; i <= pkt->count; ++i) { in radeon_uvd_cs_reg()
660 switch (pkt->reg + i*4) { in radeon_uvd_cs_reg()
662 *data0 = p->idx; in radeon_uvd_cs_reg()
665 *data1 = p->idx; in radeon_uvd_cs_reg()
678 pkt->reg + i*4); in radeon_uvd_cs_reg()
679 return -EINVAL; in radeon_uvd_cs_reg()
681 p->idx++; in radeon_uvd_cs_reg()
702 if (p->chunk_ib->length_dw % 16) { in radeon_uvd_cs_parse()
704 p->chunk_ib->length_dw); in radeon_uvd_cs_parse()
705 return -EINVAL; in radeon_uvd_cs_parse()
708 if (p->chunk_relocs == NULL) { in radeon_uvd_cs_parse()
710 return -EINVAL; in radeon_uvd_cs_parse()
715 r = radeon_cs_packet_parse(p, &pkt, p->idx); in radeon_uvd_cs_parse()
726 p->idx += pkt.count + 2; in radeon_uvd_cs_parse()
730 return -EINVAL; in radeon_uvd_cs_parse()
732 } while (p->idx < p->chunk_ib->length_dw); in radeon_uvd_cs_parse()
735 DRM_ERROR("UVD-IBs need a msg command!\n"); in radeon_uvd_cs_parse()
736 return -EINVAL; in radeon_uvd_cs_parse()
783 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_create_msg()
786 uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs); in radeon_uvd_get_create_msg()
787 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_create_msg()
791 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); in radeon_uvd_get_create_msg()
811 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_get_create_msg()
819 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_destroy_msg()
822 uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs); in radeon_uvd_get_destroy_msg()
823 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_destroy_msg()
827 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); in radeon_uvd_get_destroy_msg()
840 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_get_destroy_msg()
845 * radeon_uvd_count_handles - count number of open streams
861 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
862 if (!atomic_read(&rdev->uvd.handles[i])) in radeon_uvd_count_handles()
865 if (rdev->uvd.img_size[i] >= 720*576) in radeon_uvd_count_handles()
878 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_uvd_idle_work_handler()
879 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, in radeon_uvd_idle_work_handler()
880 &rdev->pm.dpm.hd); in radeon_uvd_idle_work_handler()
886 schedule_delayed_work(&rdev->uvd.idle_work, in radeon_uvd_idle_work_handler()
894 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); in radeon_uvd_note_usage()
895 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, in radeon_uvd_note_usage()
898 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_uvd_note_usage()
901 if ((rdev->pm.dpm.sd != sd) || in radeon_uvd_note_usage()
902 (rdev->pm.dpm.hd != hd)) { in radeon_uvd_note_usage()
903 rdev->pm.dpm.sd = sd; in radeon_uvd_note_usage()
904 rdev->pm.dpm.hd = hd; in radeon_uvd_note_usage()
911 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_uvd_note_usage()
942 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
947 * @vco_min: minimum VCO frequency
948 * @vco_max: maximum VCO frequency
949 * @fb_factor: factor to multiply vco freq with
958 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
959 * Returns zero on success -EINVAL on error.
971 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers()
976 /* loop through vco from low to high */ in radeon_uvd_calc_upll_dividers()
991 /* calc vclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
995 break; /* vco is too big, it has to stop */ in radeon_uvd_calc_upll_dividers()
997 /* calc dclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
1001 break; /* vco is too big, it has to stop */ in radeon_uvd_calc_upll_dividers()
1003 /* calc score with current vco freq */ in radeon_uvd_calc_upll_dividers()
1004 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
1006 /* determine if this vco setting is better than current optimal settings */ in radeon_uvd_calc_upll_dividers()
1019 return -EINVAL; in radeon_uvd_calc_upll_dividers()
1050 return -ETIMEDOUT; in radeon_uvd_send_upll_ctlreq()