Lines Matching +full:full +full:- +full:size
109 * r100_wait_for_vblank - vblank wait asic callback.
114 * Wait for vblank on the requested crtc (r1xx-r4xx).
120 if (crtc >= rdev->num_crtc) in r100_wait_for_vblank()
150 * r100_page_flip - pageflip callback.
157 * Does the actual pageflip (r1xx-r4xx).
164 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip()
166 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in r100_page_flip()
172 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
175 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; in r100_page_flip()
176 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8, in r100_page_flip()
177 fb->format->cpp[0] * 8 * 8); in r100_page_flip()
179 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in r100_page_flip()
182 for (i = 0; i < rdev->usec_timeout; i++) { in r100_page_flip()
183 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
189 /* Unlock the lock, so double-buffering can take place inside vblank */ in r100_page_flip()
191 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
196 * r100_page_flip_pending - check if page flip is still pending
201 * Check if the last pagefilp is still pending (r1xx-r4xx).
206 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending()
209 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
214 * r100_pm_get_dynpm_state - look up dynpm power state callback.
219 * current state of the GPU (r1xx-r5xx).
225 rdev->pm.dynpm_can_upclock = true; in r100_pm_get_dynpm_state()
226 rdev->pm.dynpm_can_downclock = true; in r100_pm_get_dynpm_state()
228 switch (rdev->pm.dynpm_planned_action) { in r100_pm_get_dynpm_state()
230 rdev->pm.requested_power_state_index = 0; in r100_pm_get_dynpm_state()
231 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
234 if (rdev->pm.current_power_state_index == 0) { in r100_pm_get_dynpm_state()
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
236 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
238 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
239 for (i = 0; i < rdev->pm.num_power_states; i++) { in r100_pm_get_dynpm_state()
240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
242 else if (i >= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
246 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
251 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
252 rdev->pm.current_power_state_index - 1; in r100_pm_get_dynpm_state()
255 if ((rdev->pm.active_crtc_count > 0) && in r100_pm_get_dynpm_state()
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & in r100_pm_get_dynpm_state()
258 rdev->pm.requested_power_state_index++; in r100_pm_get_dynpm_state()
262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r100_pm_get_dynpm_state()
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
264 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
266 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r100_pm_get_dynpm_state()
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
270 else if (i <= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
274 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
279 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
280 rdev->pm.current_power_state_index + 1; in r100_pm_get_dynpm_state()
284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r100_pm_get_dynpm_state()
285 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
293 rdev->pm.requested_clock_mode_index = 0; in r100_pm_get_dynpm_state()
296 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
297 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r100_pm_get_dynpm_state()
298 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
299 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r100_pm_get_dynpm_state()
300 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
305 * r100_pm_init_profile - Initialize power profiles callback.
310 * (r1xx-r3xx).
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
353 * r100_pm_misc - set additional pm hw parameters callback.
357 * Set non-clock parameters associated with a power state
358 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
362 int requested_index = rdev->pm.requested_power_state_index; in r100_pm_misc()
363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in r100_pm_misc()
364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in r100_pm_misc()
367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in r100_pm_misc()
368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in r100_pm_misc()
369 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
370 if (voltage->active_high) in r100_pm_misc()
371 tmp |= voltage->gpio.mask; in r100_pm_misc()
373 tmp &= ~(voltage->gpio.mask); in r100_pm_misc()
374 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
375 if (voltage->delay) in r100_pm_misc()
376 udelay(voltage->delay); in r100_pm_misc()
378 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
379 if (voltage->active_high) in r100_pm_misc()
380 tmp &= ~voltage->gpio.mask; in r100_pm_misc()
382 tmp |= voltage->gpio.mask; in r100_pm_misc()
383 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
384 if (voltage->delay) in r100_pm_misc()
385 udelay(voltage->delay); in r100_pm_misc()
394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in r100_pm_misc()
396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) in r100_pm_misc()
400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) in r100_pm_misc()
402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) in r100_pm_misc()
407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in r100_pm_misc()
409 if (voltage->delay) { in r100_pm_misc()
411 switch (voltage->delay) { in r100_pm_misc()
430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in r100_pm_misc()
440 if ((rdev->flags & RADEON_IS_PCIE) && in r100_pm_misc()
441 !(rdev->flags & RADEON_IS_IGP) && in r100_pm_misc()
442 rdev->asic->pm.set_pcie_lanes && in r100_pm_misc()
443 (ps->pcie_lanes != in r100_pm_misc()
444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in r100_pm_misc()
446 ps->pcie_lanes); in r100_pm_misc()
447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); in r100_pm_misc()
452 * r100_pm_prepare - pre-power state change callback.
456 * Prepare for a power state change (r1xx-r4xx).
460 struct drm_device *ddev = rdev->ddev; in r100_pm_prepare()
466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_prepare()
468 if (radeon_crtc->enabled) { in r100_pm_prepare()
469 if (radeon_crtc->crtc_id) { in r100_pm_prepare()
483 * r100_pm_finish - post-power state change callback.
487 * Clean up after a power state change (r1xx-r4xx).
491 struct drm_device *ddev = rdev->ddev; in r100_pm_finish()
497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_finish()
499 if (radeon_crtc->enabled) { in r100_pm_finish()
500 if (radeon_crtc->crtc_id) { in r100_pm_finish()
514 * r100_gui_idle - gui idle callback.
518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
531 * r100_hpd_sense - hpd sense callback.
536 * Checks if a digital monitor is connected (r1xx-r4xx).
559 * r100_hpd_set_polarity - hpd set polarity callback.
564 * Set the polarity of the hpd pin (r1xx-r4xx).
595 * r100_hpd_init - hpd setup callback.
599 * Setup the hpd pins used by the card (r1xx-r4xx).
604 struct drm_device *dev = rdev->ddev; in r100_hpd_init()
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_init()
610 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_init()
611 enable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_init()
612 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r100_hpd_init()
618 * r100_hpd_fini - hpd tear down callback.
622 * Tear down the hpd pins used by the card (r1xx-r4xx).
627 struct drm_device *dev = rdev->ddev; in r100_hpd_fini()
631 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_fini()
633 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_fini()
634 disable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_fini()
654 if (rdev->gart.ptr) { in r100_pci_gart_init()
662 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
663 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
664 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
665 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
677 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); in r100_pci_gart_enable()
678 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); in r100_pci_gart_enable()
679 /* set PCI GART page-table base address */ in r100_pci_gart_enable()
680 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
685 (unsigned)(rdev->mc.gtt_size >> 20), in r100_pci_gart_enable()
686 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
687 rdev->gart.ready = true; in r100_pci_gart_enable()
710 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
725 if (!rdev->irq.installed) { in r100_irq_set()
728 return -EINVAL; in r100_irq_set()
730 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r100_irq_set()
733 if (rdev->irq.crtc_vblank_int[0] || in r100_irq_set()
734 atomic_read(&rdev->irq.pflip[0])) { in r100_irq_set()
737 if (rdev->irq.crtc_vblank_int[1] || in r100_irq_set()
738 atomic_read(&rdev->irq.pflip[1])) { in r100_irq_set()
741 if (rdev->irq.hpd[0]) { in r100_irq_set()
744 if (rdev->irq.hpd[1]) { in r100_irq_set()
788 if (rdev->shutdown) { in r100_irq_process()
798 if (rdev->irq.crtc_vblank_int[0]) { in r100_irq_process()
799 drm_handle_vblank(rdev->ddev, 0); in r100_irq_process()
800 rdev->pm.vblank_sync = true; in r100_irq_process()
801 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
803 if (atomic_read(&rdev->irq.pflip[0])) in r100_irq_process()
807 if (rdev->irq.crtc_vblank_int[1]) { in r100_irq_process()
808 drm_handle_vblank(rdev->ddev, 1); in r100_irq_process()
809 rdev->pm.vblank_sync = true; in r100_irq_process()
810 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
812 if (atomic_read(&rdev->irq.pflip[1])) in r100_irq_process()
826 schedule_delayed_work(&rdev->hotplug_work, 0); in r100_irq_process()
827 if (rdev->msi_enabled) { in r100_irq_process()
828 switch (rdev->family) { in r100_irq_process()
852 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
859 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_ring_hdp_flush()
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_ring_hdp_flush()
870 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r100_fence_ring_emit()
883 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
884 radeon_ring_write(ring, fence->seq); in r100_fence_ring_emit()
905 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_copy_blit()
927 return ERR_PTR(-EINVAL); in r100_copy_blit()
934 num_gpu_pages -= cur_pages; in r100_copy_blit()
936 /* pages are in Y direction - height in r100_copy_blit()
937 page width in X direction - width */ in r100_copy_blit()
981 for (i = 0; i < rdev->usec_timeout; i++) { in r100_cp_wait_for_idle()
988 return -1; in r100_cp_wait_for_idle()
1017 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || in r100_cp_init_microcode()
1018 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || in r100_cp_init_microcode()
1019 (rdev->family == CHIP_RS200)) { in r100_cp_init_microcode()
1022 } else if ((rdev->family == CHIP_R200) || in r100_cp_init_microcode()
1023 (rdev->family == CHIP_RV250) || in r100_cp_init_microcode()
1024 (rdev->family == CHIP_RV280) || in r100_cp_init_microcode()
1025 (rdev->family == CHIP_RS300)) { in r100_cp_init_microcode()
1028 } else if ((rdev->family == CHIP_R300) || in r100_cp_init_microcode()
1029 (rdev->family == CHIP_R350) || in r100_cp_init_microcode()
1030 (rdev->family == CHIP_RV350) || in r100_cp_init_microcode()
1031 (rdev->family == CHIP_RV380) || in r100_cp_init_microcode()
1032 (rdev->family == CHIP_RS400) || in r100_cp_init_microcode()
1033 (rdev->family == CHIP_RS480)) { in r100_cp_init_microcode()
1036 } else if ((rdev->family == CHIP_R420) || in r100_cp_init_microcode()
1037 (rdev->family == CHIP_R423) || in r100_cp_init_microcode()
1038 (rdev->family == CHIP_RV410)) { in r100_cp_init_microcode()
1041 } else if ((rdev->family == CHIP_RS690) || in r100_cp_init_microcode()
1042 (rdev->family == CHIP_RS740)) { in r100_cp_init_microcode()
1045 } else if (rdev->family == CHIP_RS600) { in r100_cp_init_microcode()
1048 } else if ((rdev->family == CHIP_RV515) || in r100_cp_init_microcode()
1049 (rdev->family == CHIP_R520) || in r100_cp_init_microcode()
1050 (rdev->family == CHIP_RV530) || in r100_cp_init_microcode()
1051 (rdev->family == CHIP_R580) || in r100_cp_init_microcode()
1052 (rdev->family == CHIP_RV560) || in r100_cp_init_microcode()
1053 (rdev->family == CHIP_RV570)) { in r100_cp_init_microcode()
1058 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r100_cp_init_microcode()
1061 } else if (rdev->me_fw->size % 8) { in r100_cp_init_microcode()
1063 rdev->me_fw->size, fw_name); in r100_cp_init_microcode()
1064 err = -EINVAL; in r100_cp_init_microcode()
1065 release_firmware(rdev->me_fw); in r100_cp_init_microcode()
1066 rdev->me_fw = NULL; in r100_cp_init_microcode()
1076 if (rdev->wb.enabled) in r100_gfx_get_rptr()
1077 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); in r100_gfx_get_rptr()
1093 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_gfx_set_wptr()
1100 int i, size; in r100_cp_load_microcode() local
1106 if (rdev->me_fw) { in r100_cp_load_microcode()
1107 size = rdev->me_fw->size / 4; in r100_cp_load_microcode()
1108 fw_data = (const __be32 *)&rdev->me_fw->data[0]; in r100_cp_load_microcode()
1110 for (i = 0; i < size; i += 2) { in r100_cp_load_microcode()
1121 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_cp_init()
1133 if (!rdev->me_fw) { in r100_cp_init()
1141 /* Align ring size */ in r100_cp_init()
1155 ring->align_mask = 16 - 1; in r100_cp_init()
1162 /* Setup the cp cache like this (cache size is 96 dwords) : in r100_cp_init()
1166 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1167 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1168 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1185 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); in r100_cp_init()
1186 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); in r100_cp_init()
1190 ring->wptr = 0; in r100_cp_init()
1191 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_cp_init()
1195 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1196 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
1198 if (rdev->wb.enabled) in r100_cp_init()
1216 pci_set_master(rdev->pdev); in r100_cp_init()
1218 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_init()
1224 ring->ready = true; in r100_cp_init()
1225 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r100_cp_init()
1227 if (!ring->rptr_save_reg /* not resuming from suspend */ in r100_cp_init()
1229 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r100_cp_init()
1232 ring->rptr_save_reg = 0; in r100_cp_init()
1245 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); in r100_cp_fini()
1246 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_fini()
1253 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r100_cp_disable()
1254 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_cp_disable()
1287 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1289 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_reloc_pitch_offset()
1290 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1292 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1296 return -EINVAL; in r100_reloc_pitch_offset()
1302 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; in r100_reloc_pitch_offset()
1304 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; in r100_reloc_pitch_offset()
1319 ib = p->ib.ptr; in r100_packet3_load_vbpntr()
1320 track = (struct r100_cs_track *)p->track; in r100_packet3_load_vbpntr()
1324 pkt->opcode); in r100_packet3_load_vbpntr()
1326 return -EINVAL; in r100_packet3_load_vbpntr()
1328 track->num_arrays = c; in r100_packet3_load_vbpntr()
1329 for (i = 0; i < (c - 1); i+=2, idx+=3) { in r100_packet3_load_vbpntr()
1333 pkt->opcode); in r100_packet3_load_vbpntr()
1338 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1340 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1341 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1342 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1346 pkt->opcode); in r100_packet3_load_vbpntr()
1350 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1351 track->arrays[i + 1].robj = reloc->robj; in r100_packet3_load_vbpntr()
1352 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1353 track->arrays[i + 1].esize &= 0x7F; in r100_packet3_load_vbpntr()
1359 pkt->opcode); in r100_packet3_load_vbpntr()
1364 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1365 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1366 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1367 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1382 idx = pkt->idx + 1; in r100_cs_parse_packet0()
1383 reg = pkt->reg; in r100_cs_parse_packet0()
1388 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1390 return -EINVAL; in r100_cs_parse_packet0()
1393 if (((reg + (pkt->count << 2)) >> 7) > n) { in r100_cs_parse_packet0()
1394 return -EINVAL; in r100_cs_parse_packet0()
1397 for (i = 0; i <= pkt->count; i++, idx++) { in r100_cs_parse_packet0()
1406 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1418 * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1422 * PACKET0 - VLINE_START_END + value
1423 * PACKET0 - WAIT_UNTIL +_value
1424 * RELOC (P3) - crtc_id in reloc.
1441 ib = p->ib.ptr; in r100_cs_packet_parse_vline()
1444 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); in r100_cs_packet_parse_vline()
1452 return -EINVAL; in r100_cs_packet_parse_vline()
1457 return -EINVAL; in r100_cs_packet_parse_vline()
1461 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); in r100_cs_packet_parse_vline()
1465 h_idx = p->idx - 2; in r100_cs_packet_parse_vline()
1466 p->idx += waitreloc.count + 2; in r100_cs_packet_parse_vline()
1467 p->idx += p3reloc.count + 2; in r100_cs_packet_parse_vline()
1472 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); in r100_cs_packet_parse_vline()
1475 return -ENOENT; in r100_cs_packet_parse_vline()
1478 crtc_id = radeon_crtc->crtc_id; in r100_cs_packet_parse_vline()
1480 if (!crtc->enabled) { in r100_cs_packet_parse_vline()
1481 /* if the CRTC isn't enabled - we need to nop out the wait until */ in r100_cs_packet_parse_vline()
1496 return -EINVAL; in r100_cs_packet_parse_vline()
1571 ib = p->ib.ptr; in r100_packet0_check()
1572 track = (struct r100_cs_track *)p->track; in r100_packet0_check()
1602 track->zb.robj = reloc->robj; in r100_packet0_check()
1603 track->zb.offset = idx_value; in r100_packet0_check()
1604 track->zb_dirty = true; in r100_packet0_check()
1605 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1615 track->cb[0].robj = reloc->robj; in r100_packet0_check()
1616 track->cb[0].offset = idx_value; in r100_packet0_check()
1617 track->cb_dirty = true; in r100_packet0_check()
1618 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1623 i = (reg - RADEON_PP_TXOFFSET_0) / 24; in r100_packet0_check()
1631 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1632 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1634 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1639 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1641 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1642 track->textures[i].robj = reloc->robj; in r100_packet0_check()
1643 track->tex_dirty = true; in r100_packet0_check()
1650 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; in r100_packet0_check()
1658 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1659 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1660 track->textures[0].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1661 track->tex_dirty = true; in r100_packet0_check()
1668 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; in r100_packet0_check()
1676 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1677 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1678 track->textures[1].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1679 track->tex_dirty = true; in r100_packet0_check()
1686 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; in r100_packet0_check()
1694 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1695 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1696 track->textures[2].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1697 track->tex_dirty = true; in r100_packet0_check()
1700 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1701 track->cb_dirty = true; in r100_packet0_check()
1702 track->zb_dirty = true; in r100_packet0_check()
1712 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1713 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1715 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1724 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1725 track->cb_dirty = true; in r100_packet0_check()
1728 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1729 track->zb_dirty = true; in r100_packet0_check()
1738 track->cb[0].cpp = 1; in r100_packet0_check()
1743 track->cb[0].cpp = 2; in r100_packet0_check()
1746 track->cb[0].cpp = 4; in r100_packet0_check()
1751 return -EINVAL; in r100_packet0_check()
1753 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1754 track->cb_dirty = true; in r100_packet0_check()
1755 track->zb_dirty = true; in r100_packet0_check()
1760 track->zb.cpp = 2; in r100_packet0_check()
1768 track->zb.cpp = 4; in r100_packet0_check()
1773 track->zb_dirty = true; in r100_packet0_check()
1783 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1788 for (i = 0; i < track->num_texture; i++) in r100_packet0_check()
1789 track->textures[i].enabled = !!(temp & (1 << i)); in r100_packet0_check()
1790 track->tex_dirty = true; in r100_packet0_check()
1794 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1797 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1802 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; in r100_packet0_check()
1803 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1804 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1805 track->tex_dirty = true; in r100_packet0_check()
1810 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; in r100_packet0_check()
1811 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1812 track->tex_dirty = true; in r100_packet0_check()
1817 i = (reg - RADEON_PP_TXFILTER_0) / 24; in r100_packet0_check()
1818 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1822 track->textures[i].roundup_w = false; in r100_packet0_check()
1825 track->textures[i].roundup_h = false; in r100_packet0_check()
1826 track->tex_dirty = true; in r100_packet0_check()
1831 i = (reg - RADEON_PP_TXFORMAT_0) / 24; in r100_packet0_check()
1833 track->textures[i].use_pitch = true; in r100_packet0_check()
1835 track->textures[i].use_pitch = false; in r100_packet0_check()
1836 …track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH… in r100_packet0_check()
1837 …track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEI… in r100_packet0_check()
1840 track->textures[i].tex_coord_type = 2; in r100_packet0_check()
1845 track->textures[i].cpp = 1; in r100_packet0_check()
1846 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1857 track->textures[i].cpp = 2; in r100_packet0_check()
1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1864 track->textures[i].cpp = 4; in r100_packet0_check()
1865 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1868 track->textures[i].cpp = 1; in r100_packet0_check()
1869 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; in r100_packet0_check()
1873 track->textures[i].cpp = 1; in r100_packet0_check()
1874 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; in r100_packet0_check()
1877 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1878 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1879 track->tex_dirty = true; in r100_packet0_check()
1885 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; in r100_packet0_check()
1887 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); in r100_packet0_check()
1888 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); in r100_packet0_check()
1890 track->tex_dirty = true; in r100_packet0_check()
1894 return -EINVAL; in r100_packet0_check()
1905 idx = pkt->idx + 1; in r100_cs_track_check_pkt3_indx_buffer()
1912 return -EINVAL; in r100_cs_track_check_pkt3_indx_buffer()
1926 ib = p->ib.ptr; in r100_packet3_check()
1927 idx = pkt->idx + 1; in r100_packet3_check()
1928 track = (struct r100_cs_track *)p->track; in r100_packet3_check()
1929 switch (pkt->opcode) { in r100_packet3_check()
1938 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1942 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1943 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); in r100_packet3_check()
1952 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1956 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1957 track->num_arrays = 1; in r100_packet3_check()
1958 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); in r100_packet3_check()
1960 track->arrays[0].robj = reloc->robj; in r100_packet3_check()
1961 track->arrays[0].esize = track->vtx_size; in r100_packet3_check()
1963 track->max_indx = radeon_get_ib_value(p, idx+1); in r100_packet3_check()
1965 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); in r100_packet3_check()
1966 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
1967 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1974 return -EINVAL; in r100_packet3_check()
1976 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); in r100_packet3_check()
1977 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
1978 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
1979 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1983 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
1987 return -EINVAL; in r100_packet3_check()
1989 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
1990 track->immd_dwords = pkt->count; in r100_packet3_check()
1991 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1995 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
1997 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
1998 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2004 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
2005 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2011 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2012 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2018 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2019 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2026 if (p->rdev->hyperz_filp != p->filp) in r100_packet3_check()
2027 return -EINVAL; in r100_packet3_check()
2032 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); in r100_packet3_check()
2033 return -EINVAL; in r100_packet3_check()
2046 return -ENOMEM; in r100_cs_parse()
2047 r100_cs_track_clear(p->rdev, track); in r100_cs_parse()
2048 p->track = track; in r100_cs_parse()
2050 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r100_cs_parse()
2054 p->idx += pkt.count + 2; in r100_cs_parse()
2057 if (p->rdev->family >= CHIP_R200) in r100_cs_parse()
2059 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2060 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2064 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2065 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2076 return -EINVAL; in r100_cs_parse()
2080 } while (p->idx < p->chunk_ib->length_dw); in r100_cs_parse()
2086 DRM_ERROR("pitch %d\n", t->pitch); in r100_cs_track_texture_print()
2087 DRM_ERROR("use_pitch %d\n", t->use_pitch); in r100_cs_track_texture_print()
2088 DRM_ERROR("width %d\n", t->width); in r100_cs_track_texture_print()
2089 DRM_ERROR("width_11 %d\n", t->width_11); in r100_cs_track_texture_print()
2090 DRM_ERROR("height %d\n", t->height); in r100_cs_track_texture_print()
2091 DRM_ERROR("height_11 %d\n", t->height_11); in r100_cs_track_texture_print()
2092 DRM_ERROR("num levels %d\n", t->num_levels); in r100_cs_track_texture_print()
2093 DRM_ERROR("depth %d\n", t->txdepth); in r100_cs_track_texture_print()
2094 DRM_ERROR("bpp %d\n", t->cpp); in r100_cs_track_texture_print()
2095 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); in r100_cs_track_texture_print()
2096 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); in r100_cs_track_texture_print()
2097 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); in r100_cs_track_texture_print()
2098 DRM_ERROR("compress format %d\n", t->compress_format); in r100_cs_track_texture_print()
2123 hblocks = (h + block_height - 1) / block_height; in r100_track_compress_size()
2124 wblocks = (w + block_width - 1) / block_width; in r100_track_compress_size()
2136 unsigned long size; in r100_cs_track_cube() local
2137 unsigned compress_format = track->textures[idx].compress_format; in r100_cs_track_cube()
2140 cube_robj = track->textures[idx].cube_info[face].robj; in r100_cs_track_cube()
2141 w = track->textures[idx].cube_info[face].width; in r100_cs_track_cube()
2142 h = track->textures[idx].cube_info[face].height; in r100_cs_track_cube()
2145 size = r100_track_compress_size(compress_format, w, h); in r100_cs_track_cube()
2147 size = w * h; in r100_cs_track_cube()
2148 size *= track->textures[idx].cpp; in r100_cs_track_cube()
2150 size += track->textures[idx].cube_info[face].offset; in r100_cs_track_cube()
2152 if (size > radeon_bo_size(cube_robj)) { in r100_cs_track_cube()
2153 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", in r100_cs_track_cube()
2154 size, radeon_bo_size(cube_robj)); in r100_cs_track_cube()
2155 r100_cs_track_texture_print(&track->textures[idx]); in r100_cs_track_cube()
2156 return -1; in r100_cs_track_cube()
2166 unsigned long size; in r100_cs_track_texture_check() local
2170 for (u = 0; u < track->num_texture; u++) { in r100_cs_track_texture_check()
2171 if (!track->textures[u].enabled) in r100_cs_track_texture_check()
2173 if (track->textures[u].lookup_disable) in r100_cs_track_texture_check()
2175 robj = track->textures[u].robj; in r100_cs_track_texture_check()
2178 return -EINVAL; in r100_cs_track_texture_check()
2180 size = 0; in r100_cs_track_texture_check()
2181 for (i = 0; i <= track->textures[u].num_levels; i++) { in r100_cs_track_texture_check()
2182 if (track->textures[u].use_pitch) { in r100_cs_track_texture_check()
2183 if (rdev->family < CHIP_R300) in r100_cs_track_texture_check()
2184 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); in r100_cs_track_texture_check()
2186 w = track->textures[u].pitch / (1 << i); in r100_cs_track_texture_check()
2188 w = track->textures[u].width; in r100_cs_track_texture_check()
2189 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2190 w |= track->textures[u].width_11; in r100_cs_track_texture_check()
2192 if (track->textures[u].roundup_w) in r100_cs_track_texture_check()
2195 h = track->textures[u].height; in r100_cs_track_texture_check()
2196 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2197 h |= track->textures[u].height_11; in r100_cs_track_texture_check()
2199 if (track->textures[u].roundup_h) in r100_cs_track_texture_check()
2201 if (track->textures[u].tex_coord_type == 1) { in r100_cs_track_texture_check()
2202 d = (1 << track->textures[u].txdepth) / (1 << i); in r100_cs_track_texture_check()
2208 if (track->textures[u].compress_format) { in r100_cs_track_texture_check()
2210 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; in r100_cs_track_texture_check()
2213 size += w * h * d; in r100_cs_track_texture_check()
2215 size *= track->textures[u].cpp; in r100_cs_track_texture_check()
2217 switch (track->textures[u].tex_coord_type) { in r100_cs_track_texture_check()
2222 if (track->separate_cube) { in r100_cs_track_texture_check()
2227 size *= 6; in r100_cs_track_texture_check()
2231 "%u\n", track->textures[u].tex_coord_type, u); in r100_cs_track_texture_check()
2232 return -EINVAL; in r100_cs_track_texture_check()
2234 if (size > radeon_bo_size(robj)) { in r100_cs_track_texture_check()
2236 "%lu\n", u, size, radeon_bo_size(robj)); in r100_cs_track_texture_check()
2237 r100_cs_track_texture_print(&track->textures[u]); in r100_cs_track_texture_check()
2238 return -EINVAL; in r100_cs_track_texture_check()
2247 unsigned long size; in r100_cs_track_check() local
2250 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; in r100_cs_track_check()
2252 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && in r100_cs_track_check()
2253 !track->blend_read_enable) in r100_cs_track_check()
2257 if (track->cb[i].robj == NULL) { in r100_cs_track_check()
2259 return -EINVAL; in r100_cs_track_check()
2261 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; in r100_cs_track_check()
2262 size += track->cb[i].offset; in r100_cs_track_check()
2263 if (size > radeon_bo_size(track->cb[i].robj)) { in r100_cs_track_check()
2265 "(need %lu have %lu) !\n", i, size, in r100_cs_track_check()
2266 radeon_bo_size(track->cb[i].robj)); in r100_cs_track_check()
2268 i, track->cb[i].pitch, track->cb[i].cpp, in r100_cs_track_check()
2269 track->cb[i].offset, track->maxy); in r100_cs_track_check()
2270 return -EINVAL; in r100_cs_track_check()
2273 track->cb_dirty = false; in r100_cs_track_check()
2275 if (track->zb_dirty && track->z_enabled) { in r100_cs_track_check()
2276 if (track->zb.robj == NULL) { in r100_cs_track_check()
2278 return -EINVAL; in r100_cs_track_check()
2280 size = track->zb.pitch * track->zb.cpp * track->maxy; in r100_cs_track_check()
2281 size += track->zb.offset; in r100_cs_track_check()
2282 if (size > radeon_bo_size(track->zb.robj)) { in r100_cs_track_check()
2284 "(need %lu have %lu) !\n", size, in r100_cs_track_check()
2285 radeon_bo_size(track->zb.robj)); in r100_cs_track_check()
2287 track->zb.pitch, track->zb.cpp, in r100_cs_track_check()
2288 track->zb.offset, track->maxy); in r100_cs_track_check()
2289 return -EINVAL; in r100_cs_track_check()
2292 track->zb_dirty = false; in r100_cs_track_check()
2294 if (track->aa_dirty && track->aaresolve) { in r100_cs_track_check()
2295 if (track->aa.robj == NULL) { in r100_cs_track_check()
2297 return -EINVAL; in r100_cs_track_check()
2300 size = track->aa.pitch * track->cb[0].cpp * track->maxy; in r100_cs_track_check()
2301 size += track->aa.offset; in r100_cs_track_check()
2302 if (size > radeon_bo_size(track->aa.robj)) { in r100_cs_track_check()
2304 "(need %lu have %lu) !\n", i, size, in r100_cs_track_check()
2305 radeon_bo_size(track->aa.robj)); in r100_cs_track_check()
2307 i, track->aa.pitch, track->cb[0].cpp, in r100_cs_track_check()
2308 track->aa.offset, track->maxy); in r100_cs_track_check()
2309 return -EINVAL; in r100_cs_track_check()
2312 track->aa_dirty = false; in r100_cs_track_check()
2314 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; in r100_cs_track_check()
2315 if (track->vap_vf_cntl & (1 << 14)) { in r100_cs_track_check()
2316 nverts = track->vap_alt_nverts; in r100_cs_track_check()
2318 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; in r100_cs_track_check()
2322 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2323 size = track->arrays[i].esize * track->max_indx * 4; in r100_cs_track_check()
2324 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2327 return -EINVAL; in r100_cs_track_check()
2329 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2330 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2332 prim_walk, i, size >> 2, in r100_cs_track_check()
2333 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2335 DRM_ERROR("Max indices %u\n", track->max_indx); in r100_cs_track_check()
2336 return -EINVAL; in r100_cs_track_check()
2341 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2342 size = track->arrays[i].esize * (nverts - 1) * 4; in r100_cs_track_check()
2343 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2346 return -EINVAL; in r100_cs_track_check()
2348 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2349 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2351 prim_walk, i, size >> 2, in r100_cs_track_check()
2352 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2354 return -EINVAL; in r100_cs_track_check()
2359 size = track->vtx_size * nverts; in r100_cs_track_check()
2360 if (size != track->immd_dwords) { in r100_cs_track_check()
2362 track->immd_dwords, size); in r100_cs_track_check()
2364 nverts, track->vtx_size); in r100_cs_track_check()
2365 return -EINVAL; in r100_cs_track_check()
2371 return -EINVAL; in r100_cs_track_check()
2374 if (track->tex_dirty) { in r100_cs_track_check()
2375 track->tex_dirty = false; in r100_cs_track_check()
2385 track->cb_dirty = true; in r100_cs_track_clear()
2386 track->zb_dirty = true; in r100_cs_track_clear()
2387 track->tex_dirty = true; in r100_cs_track_clear()
2388 track->aa_dirty = true; in r100_cs_track_clear()
2390 if (rdev->family < CHIP_R300) { in r100_cs_track_clear()
2391 track->num_cb = 1; in r100_cs_track_clear()
2392 if (rdev->family <= CHIP_RS200) in r100_cs_track_clear()
2393 track->num_texture = 3; in r100_cs_track_clear()
2395 track->num_texture = 6; in r100_cs_track_clear()
2396 track->maxy = 2048; in r100_cs_track_clear()
2397 track->separate_cube = true; in r100_cs_track_clear()
2399 track->num_cb = 4; in r100_cs_track_clear()
2400 track->num_texture = 16; in r100_cs_track_clear()
2401 track->maxy = 4096; in r100_cs_track_clear()
2402 track->separate_cube = false; in r100_cs_track_clear()
2403 track->aaresolve = false; in r100_cs_track_clear()
2404 track->aa.robj = NULL; in r100_cs_track_clear()
2407 for (i = 0; i < track->num_cb; i++) { in r100_cs_track_clear()
2408 track->cb[i].robj = NULL; in r100_cs_track_clear()
2409 track->cb[i].pitch = 8192; in r100_cs_track_clear()
2410 track->cb[i].cpp = 16; in r100_cs_track_clear()
2411 track->cb[i].offset = 0; in r100_cs_track_clear()
2413 track->z_enabled = true; in r100_cs_track_clear()
2414 track->zb.robj = NULL; in r100_cs_track_clear()
2415 track->zb.pitch = 8192; in r100_cs_track_clear()
2416 track->zb.cpp = 4; in r100_cs_track_clear()
2417 track->zb.offset = 0; in r100_cs_track_clear()
2418 track->vtx_size = 0x7F; in r100_cs_track_clear()
2419 track->immd_dwords = 0xFFFFFFFFUL; in r100_cs_track_clear()
2420 track->num_arrays = 11; in r100_cs_track_clear()
2421 track->max_indx = 0x00FFFFFFUL; in r100_cs_track_clear()
2422 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_clear()
2423 track->arrays[i].robj = NULL; in r100_cs_track_clear()
2424 track->arrays[i].esize = 0x7F; in r100_cs_track_clear()
2426 for (i = 0; i < track->num_texture; i++) { in r100_cs_track_clear()
2427 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_cs_track_clear()
2428 track->textures[i].pitch = 16536; in r100_cs_track_clear()
2429 track->textures[i].width = 16536; in r100_cs_track_clear()
2430 track->textures[i].height = 16536; in r100_cs_track_clear()
2431 track->textures[i].width_11 = 1 << 11; in r100_cs_track_clear()
2432 track->textures[i].height_11 = 1 << 11; in r100_cs_track_clear()
2433 track->textures[i].num_levels = 12; in r100_cs_track_clear()
2434 if (rdev->family <= CHIP_RS200) { in r100_cs_track_clear()
2435 track->textures[i].tex_coord_type = 0; in r100_cs_track_clear()
2436 track->textures[i].txdepth = 0; in r100_cs_track_clear()
2438 track->textures[i].txdepth = 16; in r100_cs_track_clear()
2439 track->textures[i].tex_coord_type = 1; in r100_cs_track_clear()
2441 track->textures[i].cpp = 64; in r100_cs_track_clear()
2442 track->textures[i].robj = NULL; in r100_cs_track_clear()
2444 track->textures[i].enabled = false; in r100_cs_track_clear()
2445 track->textures[i].lookup_disable = false; in r100_cs_track_clear()
2446 track->textures[i].roundup_w = true; in r100_cs_track_clear()
2447 track->textures[i].roundup_h = true; in r100_cs_track_clear()
2448 if (track->separate_cube) in r100_cs_track_clear()
2450 track->textures[i].cube_info[face].robj = NULL; in r100_cs_track_clear()
2451 track->textures[i].cube_info[face].width = 16536; in r100_cs_track_clear()
2452 track->textures[i].cube_info[face].height = 16536; in r100_cs_track_clear()
2453 track->textures[i].cube_info[face].offset = 0; in r100_cs_track_clear()
2463 rdev->pll_errata = 0; in r100_errata()
2465 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { in r100_errata()
2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; in r100_errata()
2469 if (rdev->family == CHIP_RV100 || in r100_errata()
2470 rdev->family == CHIP_RS100 || in r100_errata()
2471 rdev->family == CHIP_RS200) { in r100_errata()
2472 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; in r100_errata()
2481 for (i = 0; i < rdev->usec_timeout; i++) { in r100_rbbm_fifo_wait_for_entry()
2488 return -1; in r100_rbbm_fifo_wait_for_entry()
2499 for (i = 0; i < rdev->usec_timeout; i++) { in r100_gui_wait_for_idle()
2506 return -1; in r100_gui_wait_for_idle()
2514 for (i = 0; i < rdev->usec_timeout; i++) { in r100_mc_wait_for_idle()
2522 return -1; in r100_mc_wait_for_idle()
2559 pci_clear_master(rdev->pdev); in r100_bm_disable()
2575 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2584 pci_save_state(rdev->pdev); in r100_asic_reset()
2596 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2604 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2606 pci_restore_state(rdev->pdev); in r100_asic_reset()
2611 dev_err(rdev->dev, "failed to reset GPU\n"); in r100_asic_reset()
2612 ret = -1; in r100_asic_reset()
2614 dev_info(rdev->dev, "GPU reset succeed\n"); in r100_asic_reset()
2638 switch (rdev->pdev->device) { in r100_set_common_regs()
2648 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && in r100_set_common_regs()
2649 ((rdev->pdev->subsystem_device == 0x016c) || in r100_set_common_regs()
2650 (rdev->pdev->subsystem_device == 0x016d) || in r100_set_common_regs()
2651 (rdev->pdev->subsystem_device == 0x016e) || in r100_set_common_regs()
2652 (rdev->pdev->subsystem_device == 0x016f) || in r100_set_common_regs()
2653 (rdev->pdev->subsystem_device == 0x0170) || in r100_set_common_regs()
2654 (rdev->pdev->subsystem_device == 0x017d) || in r100_set_common_regs()
2655 (rdev->pdev->subsystem_device == 0x017e) || in r100_set_common_regs()
2656 (rdev->pdev->subsystem_device == 0x0183) || in r100_set_common_regs()
2657 (rdev->pdev->subsystem_device == 0x018a) || in r100_set_common_regs()
2658 (rdev->pdev->subsystem_device == 0x019a))) in r100_set_common_regs()
2709 rdev->mc.vram_is_ddr = false; in r100_vram_get_type()
2710 if (rdev->flags & RADEON_IS_IGP) in r100_vram_get_type()
2711 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2713 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2714 if ((rdev->family == CHIP_RV100) || in r100_vram_get_type()
2715 (rdev->family == CHIP_RS100) || in r100_vram_get_type()
2716 (rdev->family == CHIP_RS200)) { in r100_vram_get_type()
2719 rdev->mc.vram_width = 32; in r100_vram_get_type()
2721 rdev->mc.vram_width = 64; in r100_vram_get_type()
2723 if (rdev->flags & RADEON_SINGLE_CRTC) { in r100_vram_get_type()
2724 rdev->mc.vram_width /= 4; in r100_vram_get_type()
2725 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2727 } else if (rdev->family <= CHIP_RV280) { in r100_vram_get_type()
2730 rdev->mc.vram_width = 128; in r100_vram_get_type()
2732 rdev->mc.vram_width = 64; in r100_vram_get_type()
2736 rdev->mc.vram_width = 128; in r100_vram_get_type()
2750 if (rdev->family == CHIP_RV280 || in r100_get_accessible_vram()
2751 rdev->family >= CHIP_RV350) { in r100_get_accessible_vram()
2760 * header type... Limit those to one aperture size in r100_get_accessible_vram()
2762 pci_read_config_byte(rdev->pdev, 0xe, &byte); in r100_get_accessible_vram()
2783 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r100_vram_init_sizes()
2784 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r100_vram_init_sizes()
2785 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); in r100_vram_init_sizes()
2787 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) in r100_vram_init_sizes()
2788 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2790 if (rdev->flags & RADEON_IS_IGP) { in r100_vram_init_sizes()
2794 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); in r100_vram_init_sizes()
2795 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2796 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2798 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2802 if (rdev->mc.real_vram_size == 0) { in r100_vram_init_sizes()
2803 rdev->mc.real_vram_size = 8192 * 1024; in r100_vram_init_sizes()
2804 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2806 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - in r100_vram_init_sizes()
2809 if (rdev->mc.aper_size > config_aper_size) in r100_vram_init_sizes()
2810 config_aper_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2812 if (config_aper_size > rdev->mc.real_vram_size) in r100_vram_init_sizes()
2813 rdev->mc.mc_vram_size = config_aper_size; in r100_vram_init_sizes()
2815 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2839 base = rdev->mc.aper_base; in r100_mc_init()
2840 if (rdev->flags & RADEON_IS_IGP) in r100_mc_init()
2842 radeon_vram_location(rdev, &rdev->mc, base); in r100_mc_init()
2843 rdev->mc.gtt_base_align = 0; in r100_mc_init()
2844 if (!(rdev->flags & RADEON_IS_AGP)) in r100_mc_init()
2845 radeon_gtt_location(rdev, &rdev->mc); in r100_mc_init()
2855 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { in r100_pll_errata_after_index()
2866 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { in r100_pll_errata_after_data()
2875 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { in r100_pll_errata_after_data()
2891 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2896 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2904 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2909 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2915 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; in r100_set_safe_registers()
2916 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); in r100_set_safe_registers()
2917 } else if (rdev->family < CHIP_R200) { in r100_set_safe_registers()
2918 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; in r100_set_safe_registers()
2919 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); in r100_set_safe_registers()
2931 struct radeon_device *rdev = (struct radeon_device *)m->private; in r100_debugfs_rbbm_info_show()
2940 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info_show()
2950 struct radeon_device *rdev = (struct radeon_device *)m->private; in r100_debugfs_cp_ring_info_show()
2951 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_debugfs_cp_ring_info_show()
2958 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; in r100_debugfs_cp_ring_info_show()
2962 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); in r100_debugfs_cp_ring_info_show()
2964 if (ring->ready) { in r100_debugfs_cp_ring_info_show()
2966 i = (rdp + j) & ring->ptr_mask; in r100_debugfs_cp_ring_info_show()
2967 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); in r100_debugfs_cp_ring_info_show()
2976 struct radeon_device *rdev = (struct radeon_device *)m->private; in r100_debugfs_cp_csq_fifo_show()
3024 struct radeon_device *rdev = (struct radeon_device *)m->private; in r100_debugfs_mc_info_show()
3060 struct dentry *root = rdev->ddev->primary->debugfs_root; in r100_debugfs_rbbm_init()
3070 struct dentry *root = rdev->ddev->primary->debugfs_root; in r100_debugfs_cp_init()
3082 struct dentry *root = rdev->ddev->primary->debugfs_root; in r100_debugfs_mc_info_init()
3096 if (rdev->family <= CHIP_RS200) { in r100_set_surface_reg()
3106 } else if (rdev->family <= CHIP_RV280) { in r100_set_surface_reg()
3124 if (rdev->family < CHIP_R300) in r100_set_surface_reg()
3130 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); in r100_set_surface_reg()
3133 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); in r100_set_surface_reg()
3215 /* Guess line buffer size to be 8192 pixels */ in r100_bandwidth_update()
3218 if (!rdev->mode_info.mode_config_initialized) in r100_bandwidth_update()
3223 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update()
3225 rdev->mode_info.crtcs[0]->base.primary->fb; in r100_bandwidth_update()
3227 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update()
3228 pixel_bytes1 = fb->format->cpp[0]; in r100_bandwidth_update()
3230 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_bandwidth_update()
3231 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update()
3233 rdev->mode_info.crtcs[1]->base.primary->fb; in r100_bandwidth_update()
3235 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update()
3236 pixel_bytes2 = fb->format->cpp[0]; in r100_bandwidth_update()
3240 min_mem_eff.full = dfixed_const_8(0); in r100_bandwidth_update()
3242 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { in r100_bandwidth_update()
3257 sclk_ff = rdev->pm.sclk; in r100_bandwidth_update()
3258 mclk_ff = rdev->pm.mclk; in r100_bandwidth_update()
3260 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); in r100_bandwidth_update()
3261 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()
3262 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); in r100_bandwidth_update()
3264 pix_clk.full = 0; in r100_bandwidth_update()
3265 pix_clk2.full = 0; in r100_bandwidth_update()
3266 peak_disp_bw.full = 0; in r100_bandwidth_update()
3268 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3269 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3270 pix_clk.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3271 temp_ff.full = dfixed_const(pixel_bytes1); in r100_bandwidth_update()
3272 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3275 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3276 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()
3277 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); in r100_bandwidth_update()
3278 temp_ff.full = dfixed_const(pixel_bytes2); in r100_bandwidth_update()
3279 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); in r100_bandwidth_update()
3282 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); in r100_bandwidth_update()
3283 if (peak_disp_bw.full >= mem_bw.full) { in r100_bandwidth_update()
3290 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ in r100_bandwidth_update()
3294 } else if (rdev->family == CHIP_R300 || in r100_bandwidth_update()
3295 rdev->family == CHIP_R350) { /* r300, r350 */ in r100_bandwidth_update()
3299 } else if (rdev->family == CHIP_RV350 || in r100_bandwidth_update()
3300 rdev->family == CHIP_RV380) { in r100_bandwidth_update()
3305 } else if (rdev->family == CHIP_R420 || in r100_bandwidth_update()
3306 rdev->family == CHIP_R423 || in r100_bandwidth_update()
3307 rdev->family == CHIP_RV410) { in r100_bandwidth_update()
3324 trcd_ff.full = dfixed_const(mem_trcd); in r100_bandwidth_update()
3325 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()
3326 tras_ff.full = dfixed_const(mem_tras); in r100_bandwidth_update()
3331 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3332 if (rdev->family == CHIP_RS480) /* don't think rs400 */ in r100_bandwidth_update()
3339 if (rdev->family == CHIP_RS400 || in r100_bandwidth_update()
3340 rdev->family == CHIP_RS480) { in r100_bandwidth_update()
3341 /* extra cas latency stored in bits 23-25 0-4 clocks */ in r100_bandwidth_update()
3344 tcas_ff.full += dfixed_const(data); in r100_bandwidth_update()
3347 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { in r100_bandwidth_update()
3368 if (rdev->family == CHIP_RV410 || in r100_bandwidth_update()
3369 rdev->family == CHIP_R420 || in r100_bandwidth_update()
3370 rdev->family == CHIP_R423) in r100_bandwidth_update()
3374 tcas_ff.full += trbs_ff.full; in r100_bandwidth_update()
3377 sclk_eff_ff.full = sclk_ff.full; in r100_bandwidth_update()
3379 if (rdev->flags & RADEON_IS_AGP) { in r100_bandwidth_update()
3381 agpmode_ff.full = dfixed_const(radeon_agpmode); in r100_bandwidth_update()
3382 temp_ff.full = dfixed_const_666(16); in r100_bandwidth_update()
3383 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); in r100_bandwidth_update()
3385 /* TODO PCIE lanes may affect this - agpmode == 16?? */ in r100_bandwidth_update()
3388 sclk_delay_ff.full = dfixed_const(250); in r100_bandwidth_update()
3390 if ((rdev->family == CHIP_RV100) || in r100_bandwidth_update()
3391 rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3392 if (rdev->mc.vram_is_ddr) in r100_bandwidth_update()
3393 sclk_delay_ff.full = dfixed_const(41); in r100_bandwidth_update()
3395 sclk_delay_ff.full = dfixed_const(33); in r100_bandwidth_update()
3397 if (rdev->mc.vram_width == 128) in r100_bandwidth_update()
3398 sclk_delay_ff.full = dfixed_const(57); in r100_bandwidth_update()
3400 sclk_delay_ff.full = dfixed_const(41); in r100_bandwidth_update()
3404 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); in r100_bandwidth_update()
3406 if (rdev->mc.vram_is_ddr) { in r100_bandwidth_update()
3407 if (rdev->mc.vram_width == 32) { in r100_bandwidth_update()
3408 k1.full = dfixed_const(40); in r100_bandwidth_update()
3411 k1.full = dfixed_const(20); in r100_bandwidth_update()
3415 k1.full = dfixed_const(40); in r100_bandwidth_update()
3419 temp_ff.full = dfixed_const(2); in r100_bandwidth_update()
3420 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); in r100_bandwidth_update()
3421 temp_ff.full = dfixed_const(c); in r100_bandwidth_update()
3422 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); in r100_bandwidth_update()
3423 temp_ff.full = dfixed_const(4); in r100_bandwidth_update()
3424 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); in r100_bandwidth_update()
3425 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); in r100_bandwidth_update()
3426 mc_latency_mclk.full += k1.full; in r100_bandwidth_update()
3428 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); in r100_bandwidth_update()
3429 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); in r100_bandwidth_update()
3432 HW cursor time assuming worst case of full size colour cursor. in r100_bandwidth_update()
3434 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); in r100_bandwidth_update()
3435 temp_ff.full += trcd_ff.full; in r100_bandwidth_update()
3436 if (temp_ff.full < tras_ff.full) in r100_bandwidth_update()
3437 temp_ff.full = tras_ff.full; in r100_bandwidth_update()
3438 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); in r100_bandwidth_update()
3440 temp_ff.full = dfixed_const(cur_size); in r100_bandwidth_update()
3441 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); in r100_bandwidth_update()
3445 disp_latency_overhead.full = dfixed_const(8); in r100_bandwidth_update()
3446 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); in r100_bandwidth_update()
3447 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; in r100_bandwidth_update()
3448 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; in r100_bandwidth_update()
3450 if (mc_latency_mclk.full > mc_latency_sclk.full) in r100_bandwidth_update()
3451 disp_latency.full = mc_latency_mclk.full; in r100_bandwidth_update()
3453 disp_latency.full = mc_latency_sclk.full; in r100_bandwidth_update()
3466 stop_req = mode1->hdisplay * pixel_bytes1 / 16; in r100_bandwidth_update()
3474 temp_ff.full = dfixed_const((16/pixel_bytes1)); in r100_bandwidth_update()
3475 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3480 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); in r100_bandwidth_update()
3481 crit_point_ff.full += dfixed_const_half(0); in r100_bandwidth_update()
3485 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3490 The critical point should never be above max_stop_req-4. Setting in r100_bandwidth_update()
3493 if (max_stop_req - critical_point < 4) in r100_bandwidth_update()
3496 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3505 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3507 stop_req -= 0x10; in r100_bandwidth_update()
3521 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3522 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3540 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ in r100_bandwidth_update()
3546 stop_req = mode2->hdisplay * pixel_bytes2 / 16; in r100_bandwidth_update()
3554 temp_ff.full = dfixed_const((16/pixel_bytes2)); in r100_bandwidth_update()
3555 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); in r100_bandwidth_update()
3561 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3563 stop_req -= 0x10; in r100_bandwidth_update()
3571 if ((rdev->family == CHIP_RS100) || in r100_bandwidth_update()
3572 (rdev->family == CHIP_RS200)) in r100_bandwidth_update()
3575 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; in r100_bandwidth_update()
3576 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()
3577 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); in r100_bandwidth_update()
3578 if (sclk_ff.full < temp_ff.full) in r100_bandwidth_update()
3579 temp_ff.full = sclk_ff.full; in r100_bandwidth_update()
3581 read_return_rate.full = temp_ff.full; in r100_bandwidth_update()
3584 temp_ff.full = read_return_rate.full - disp_drain_rate.full; in r100_bandwidth_update()
3585 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); in r100_bandwidth_update()
3587 time_disp1_drop_priority.full = 0; in r100_bandwidth_update()
3589 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; in r100_bandwidth_update()
3590 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); in r100_bandwidth_update()
3591 crit_point_ff.full += dfixed_const_half(0); in r100_bandwidth_update()
3595 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3599 if (max_stop_req - critical_point2 < 4) in r100_bandwidth_update()
3604 if (critical_point2 == 0 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3612 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3613 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3641 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3644 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
3669 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ring_test()
3676 if (i < rdev->usec_timeout) { in r100_ring_test()
3681 r = -EINVAL; in r100_ring_test()
3689 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_ring_ib_execute()
3691 if (ring->rptr_save_reg) { in r100_ring_ib_execute()
3692 u32 next_rptr = ring->wptr + 2 + 3; in r100_ring_ib_execute()
3693 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); in r100_ring_ib_execute()
3698 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
3699 radeon_ring_write(ring, ib->length_dw); in r100_ring_ib_execute()
3742 r = -ETIMEDOUT; in r100_ib_test()
3746 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ib_test()
3753 if (i < rdev->usec_timeout) { in r100_ib_test()
3758 r = -EINVAL; in r100_ib_test()
3772 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_mc_stop()
3776 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3777 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3778 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3779 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3780 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3781 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3782 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3786 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3788 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); in r100_mc_stop()
3789 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | in r100_mc_stop()
3792 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | in r100_mc_stop()
3796 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); in r100_mc_stop()
3797 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3798 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | in r100_mc_stop()
3801 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | in r100_mc_stop()
3805 C_000360_CUR2_LOCK & save->CUR2_OFFSET); in r100_mc_stop()
3812 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3813 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3814 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3817 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3818 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); in r100_mc_resume()
3819 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); in r100_mc_resume()
3820 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3821 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); in r100_mc_resume()
3839 if (rdev->flags & RADEON_IS_AGP) { in r100_mc_program()
3841 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r100_mc_program()
3842 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r100_mc_program()
3843 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r100_mc_program()
3844 if (rdev->family > CHIP_RV200) in r100_mc_program()
3846 upper_32_bits(rdev->mc.agp_base) & 0xff); in r100_mc_program()
3850 if (rdev->family > CHIP_RV200) in r100_mc_program()
3855 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); in r100_mc_program()
3858 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r100_mc_program()
3859 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r100_mc_program()
3867 if (radeon_dynclks != -1 && radeon_dynclks) in r100_clock_startup()
3872 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) in r100_clock_startup()
3890 if (rdev->flags & RADEON_IS_PCI) { in r100_startup()
3903 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r100_startup()
3908 if (!rdev->irq.installed) { in r100_startup()
3915 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3919 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r100_startup()
3925 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r100_startup()
3937 if (rdev->flags & RADEON_IS_PCI) in r100_resume()
3943 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r100_resume()
3948 radeon_combios_asic_init(rdev->ddev); in r100_resume()
3954 rdev->accel_working = true; in r100_resume()
3957 rdev->accel_working = false; in r100_resume()
3968 if (rdev->flags & RADEON_IS_PCI) in r100_suspend()
3980 if (rdev->flags & RADEON_IS_PCI) in r100_fini()
3987 kfree(rdev->bios); in r100_fini()
3988 rdev->bios = NULL; in r100_fini()
4034 return -EINVAL; in r100_init()
4036 if (rdev->is_atom_bios) { in r100_init()
4037 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in r100_init()
4038 return -EINVAL; in r100_init()
4046 dev_warn(rdev->dev, in r100_init()
4053 return -EINVAL; in r100_init()
4057 radeon_get_clock_info(rdev->ddev); in r100_init()
4059 if (rdev->flags & RADEON_IS_AGP) { in r100_init()
4073 if (rdev->flags & RADEON_IS_PCI) { in r100_init()
4083 rdev->accel_working = true; in r100_init()
4087 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r100_init()
4092 if (rdev->flags & RADEON_IS_PCI) in r100_init()
4094 rdev->accel_working = false; in r100_init()
4104 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4105 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_rreg_slow()
4106 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_rreg_slow()
4107 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4115 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4116 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_wreg_slow()
4117 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_wreg_slow()
4118 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4123 if (reg < rdev->rio_mem_size) in r100_io_rreg()
4124 return ioread32(rdev->rio_mem + reg); in r100_io_rreg()
4126 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_rreg()
4127 return ioread32(rdev->rio_mem + RADEON_MM_DATA); in r100_io_rreg()
4133 if (reg < rdev->rio_mem_size) in r100_io_wreg()
4134 iowrite32(v, rdev->rio_mem + reg); in r100_io_wreg()
4136 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_wreg()
4137 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); in r100_io_wreg()