Lines Matching refs:pi
174 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
176 return pi; in ci_get_pi()
188 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
198 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
204 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
208 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
212 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
222 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
226 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
228 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
229 pi->caps_cac = false; in ci_initialize_powertune_defaults()
230 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
231 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
232 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
233 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
235 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
236 pi->caps_cac = true; in ci_initialize_powertune_defaults()
238 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
240 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
241 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
242 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
253 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
254 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
255 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
256 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
282 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
283 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
286 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
289 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
290 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
297 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
298 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
300 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
301 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
302 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
303 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
310 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
311 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
315 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
316 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
318 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
325 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
326 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
333 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
334 pi->sram_end); in ci_populate_dw8()
338 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
345 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
352 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
360 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
361 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
362 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
384 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
385 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
392 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
393 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
394 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
401 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
402 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
409 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
410 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
411 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
422 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
424 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
457 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
461 if (pi->caps_power_containment) { in ci_populate_pm_base()
465 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
493 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
494 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
504 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
507 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
516 if (pi->caps_db_ramping) { in ci_do_enable_didt()
525 if (pi->caps_td_ramping) { in ci_do_enable_didt()
534 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
594 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
597 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
598 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
619 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
624 pi->power_containment_features = 0; in ci_enable_power_containment()
625 if (pi->caps_power_containment) { in ci_enable_power_containment()
626 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
631 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
634 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
639 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
642 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
659 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
663 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
666 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
668 pi->power_containment_features = 0; in ci_enable_power_containment()
677 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
681 if (pi->caps_cac) { in ci_enable_smc_cac()
686 pi->cac_enabled = false; in ci_enable_smc_cac()
688 pi->cac_enabled = true; in ci_enable_smc_cac()
690 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
692 pi->cac_enabled = false; in ci_enable_smc_cac()
702 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
705 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
720 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
728 if (pi->caps_power_containment) { in ci_power_control_set_level()
742 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
744 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
747 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
754 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
756 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
775 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
796 pi->battery_state = true; in ci_apply_state_adjust_rules()
798 pi->battery_state = false; in ci_apply_state_adjust_rules()
913 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
916 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
918 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
920 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
921 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
935 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
944 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
997 pi->fan_table_start, in ci_thermal_setup_fan_table()
1000 pi->sram_end); in ci_thermal_setup_fan_table()
1012 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1015 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1034 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1041 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1045 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1082 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1087 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1127 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1130 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1191 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1194 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1196 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1200 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1202 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1260 struct ci_power_info *pi = ci_get_pi(rdev);
1263 pi->soft_regs_start + reg_offset,
1264 value, pi->sram_end);
1271 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1274 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1275 value, pi->sram_end); in ci_write_smc_soft_register()
1280 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1281 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1283 if (pi->caps_fps) { in ci_init_fps_limits()
1296 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1300 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1301 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1304 pi->dpm_table_start + in ci_update_sclk_t()
1307 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1316 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1321 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1322 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1330 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1331 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1332 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1342 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1343 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1344 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1347 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1348 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1349 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1358 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1381 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1397 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1400 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1401 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1402 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1405 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1406 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1407 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1420 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1423 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1426 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1427 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1433 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1434 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1440 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1446 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1450 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1456 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1474 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1480 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1492 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1517 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1528 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1531 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1534 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1535 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1541 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1542 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1553 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1566 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1598 struct ci_power_info *pi = ci_get_pi(rdev);
1610 if (pi->caps_automatic_dc_transition) {
1664 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1666 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1678 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1680 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1692 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1694 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1706 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1708 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1782 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1789 &tmp, pi->sram_end); in ci_process_firmware_header()
1793 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1798 &tmp, pi->sram_end); in ci_process_firmware_header()
1802 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1807 &tmp, pi->sram_end); in ci_process_firmware_header()
1811 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1816 &tmp, pi->sram_end); in ci_process_firmware_header()
1820 pi->fan_table_start = tmp; in ci_process_firmware_header()
1825 &tmp, pi->sram_end); in ci_process_firmware_header()
1829 pi->arb_table_start = tmp; in ci_process_firmware_header()
1836 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1838 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1840 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1842 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1844 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1846 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1848 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1850 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1851 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1852 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1853 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1854 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1855 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1856 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1857 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1858 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1863 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1865 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1929 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1932 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1940 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1985 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
1989 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2059 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2071 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2100 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2103 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2106 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2109 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2112 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2117 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2119 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2121 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2124 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2127 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2130 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2135 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2137 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2139 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2142 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2145 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2148 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2153 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2155 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2185 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2188 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2191 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2194 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2196 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2211 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2214 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2217 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2219 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2231 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2234 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2237 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2240 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2242 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2274 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2277 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2280 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2379 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2383 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2384 &tmp, pi->sram_end); in ci_init_arb_table_index()
2391 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2392 tmp, pi->sram_end); in ci_init_arb_table_index()
2512 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2519 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2520 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2522 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2523 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2532 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2535 pi->sram_end); in ci_do_program_memory_timing_parameters()
2542 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2544 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2554 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2560 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2568 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2593 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2594 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2607 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2608 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2758 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2759 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2760 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2761 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2762 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2763 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2764 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2765 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2766 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2767 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2785 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2791 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2843 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2873 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2883 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2893 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2894 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2895 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2900 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2901 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2904 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2907 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2908 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2911 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2912 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2922 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2956 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2959 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2960 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2961 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2962 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2967 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2968 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2970 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2972 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2994 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
2995 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
2996 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
2997 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3016 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3017 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3019 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3022 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3039 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3041 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3043 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3045 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3047 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3048 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3049 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3057 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3071 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3072 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3089 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3096 pi->ulv.supported = false; in ci_populate_ulv_level()
3100 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3114 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3127 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3129 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3130 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3131 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3132 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3151 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3184 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3202 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3218 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3242 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3243 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3244 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3248 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3256 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3257 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3261 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3263 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3266 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3268 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3269 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3274 pi->sram_end); in ci_populate_all_graphic_levels()
3289 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3290 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3291 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3295 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3305 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3310 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3315 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3316 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3317 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3320 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3322 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3323 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3326 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3331 pi->sram_end); in ci_populate_all_memory_levels()
3359 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3361 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3364 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3365 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3366 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3367 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3368 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3369 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3373 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3377 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3378 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3379 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3381 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3382 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3383 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3384 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3385 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3386 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3387 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3388 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3389 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3390 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3391 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3392 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3394 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3395 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3397 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3398 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3400 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3407 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3425 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3428 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3431 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3434 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3437 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3440 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3443 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3446 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3448 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3450 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3452 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3456 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3459 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3461 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3463 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3465 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3470 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3472 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3474 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3476 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3481 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3483 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3485 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3491 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3493 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3495 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3521 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3522 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3524 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3531 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3542 if (pi->mem_gddr5) in ci_init_smc_table()
3546 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3593 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3594 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3595 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3597 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3598 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3599 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3601 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3602 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3603 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3620 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3622 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3630 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3632 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3656 pi->dpm_table_start + in ci_init_smc_table()
3660 pi->sram_end); in ci_init_smc_table()
3686 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3687 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3717 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3729 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3734 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3781 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3786 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3787 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3790 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3796 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3797 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3800 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3806 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3807 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3810 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3822 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3824 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3826 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3830 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3838 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3845 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3854 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3858 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3864 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3868 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3871 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3874 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3877 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3880 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3886 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3897 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3907 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3911 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3913 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3920 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3922 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3923 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3924 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3927 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3930 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3931 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3932 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3935 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3946 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3956 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3959 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3961 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3968 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3979 struct ci_power_info *pi = ci_get_pi(rdev);
3989 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3992 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3994 if (!pi->caps_samu_dpm)
4001 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4010 struct ci_power_info *pi = ci_get_pi(rdev);
4020 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4023 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4025 if (!pi->caps_acp_dpm)
4032 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4043 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4047 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4049 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4051 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4056 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4082 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4091 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4094 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4116 struct ci_power_info *pi = ci_get_pi(rdev);
4120 pi->smc_state_table.AcpBootLevel = 0;
4124 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4135 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4142 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4143 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4144 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4145 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4146 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4147 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4148 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4149 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4150 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4152 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4153 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4173 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4178 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4179 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4181 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4197 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4198 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4200 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4216 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4217 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4219 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4236 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4237 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4239 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4251 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4252 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4254 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4266 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4267 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4269 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4282 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4303 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4329 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4336 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4590 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4592 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4650 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4653 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4654 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4657 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4658 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4686 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4689 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4690 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4694 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4697 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4698 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4699 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4705 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4708 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4710 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4716 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4719 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4721 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4724 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4727 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4728 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4730 pi->sram_end); in ci_populate_initial_mc_reg_table()
4735 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4737 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4740 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4742 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4745 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4747 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4749 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4750 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4817 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4822 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4825 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4827 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4828 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4835 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4845 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4850 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4858 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4863 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4883 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4904 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4905 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4908 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4909 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4926 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4927 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4940 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4941 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5059 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5066 pi->mem_gddr5 = true; in ci_get_memory_type()
5068 pi->mem_gddr5 = false; in ci_get_memory_type()
5076 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5078 pi->current_rps = *rps; in ci_update_current_ps()
5079 pi->current_ps = *new_ps; in ci_update_current_ps()
5080 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5087 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5089 pi->requested_rps = *rps; in ci_update_requested_ps()
5090 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5091 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5096 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5102 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5109 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5110 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5131 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5137 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5145 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5148 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5150 if (pi->dynamic_ss) in ci_dpm_enable()
5152 if (pi->thermal_protection) in ci_dpm_enable()
5182 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5286 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5296 if (pi->thermal_protection) in ci_dpm_disable()
5317 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5318 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5319 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5323 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5352 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5374 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5442 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5454 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5455 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5458 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5462 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5466 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5467 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5468 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5473 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5474 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5475 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5476 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5481 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5482 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5483 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5484 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5485 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5486 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5487 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5488 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5489 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5492 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5493 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5494 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5495 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5496 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5497 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5498 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5499 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5500 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5645 struct ci_power_info *pi; in ci_dpm_init() local
5650 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5651 if (pi == NULL) in ci_dpm_init()
5653 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5658 pi->sys_pcie_mask = 0; in ci_dpm_init()
5661 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5665 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5668 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5670 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5672 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5673 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5674 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5675 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5677 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5678 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5679 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5680 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5682 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5706 pi->dll_default_on = false; in ci_dpm_init()
5707 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5709 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5710 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5711 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5712 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5713 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5714 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5715 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5716 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5718 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5720 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5721 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5722 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5723 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5728 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5731 pi->caps_sclk_ds = true; in ci_dpm_init()
5733 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5734 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5735 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5736 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5740 pi->caps_fps = false; in ci_dpm_init()
5742 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5744 pi->caps_uvd_dpm = true; in ci_dpm_init()
5745 pi->caps_vce_dpm = true; in ci_dpm_init()
5779 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5780 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5781 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5783 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5784 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5785 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5788 pi->uvd_enabled = false; in ci_dpm_init()
5790 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5839 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5840 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5841 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5843 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5845 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5849 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5851 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5858 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5860 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5865 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5868 pi->pcie_performance_request = in ci_dpm_init()
5871 pi->pcie_performance_request = false; in ci_dpm_init()
5876 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5877 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5878 pi->dynamic_ss = true; in ci_dpm_init()
5880 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5881 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5882 pi->dynamic_ss = true; in ci_dpm_init()
5886 pi->thermal_protection = true; in ci_dpm_init()
5888 pi->thermal_protection = false; in ci_dpm_init()
5890 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5892 pi->uvd_power_gated = false; in ci_dpm_init()
5900 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5908 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5909 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5913 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5953 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5954 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5964 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5965 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()