Lines Matching refs:dpm
174 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
259 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
261 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
263 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
264 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
267 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
268 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
269 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
270 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
271 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
273 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
274 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
314 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
347 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
348 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
349 rdev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
350 rdev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
353 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
396 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
413 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
414 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
648 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
722 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
730 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
782 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
783 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
789 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
800 if (rdev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
801 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
803 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
805 if (rdev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
825 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
826 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
827 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
828 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
876 rdev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
877 rdev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
945 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
952 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
956 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
960 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
961 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
963 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
964 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
969 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
970 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
971 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
978 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
988 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1004 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1023 rdev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1113 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1118 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1175 if (rdev->pm.dpm.fan.ucode_fan_control)
1208 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1240 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1324 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1414 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1600 rdev->pm.dpm.dyn_state.cac_tdp_table;
1959 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
1979 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
2111 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2129 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2147 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2278 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2279 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2285 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2301 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2304 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2305 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2307 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2309 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2312 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2314 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2316 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2322 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2324 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2326 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2329 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2331 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2333 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2557 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2558 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2565 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2566 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2620 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2624 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2626 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2628 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2663 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2667 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2669 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2696 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2700 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2702 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2728 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2732 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2734 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2847 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2849 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2855 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2857 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2863 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2865 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2875 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
2897 (rdev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
3090 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3101 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3105 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3107 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3111 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3192 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3204 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3409 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3411 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3413 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3478 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3488 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3523 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ci_init_smc_table()
3536 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3539 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3750 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3752 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3856 if (rdev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3857 rdev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
3901 if (rdev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
3902 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3904 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3909 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3910 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3950 if (rdev->pm.dpm.ac_power) in ci_enable_vce_dpm()
3951 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3953 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3957 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3958 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
3983 if (rdev->pm.dpm.ac_power)
3984 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3986 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3990 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3991 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4014 if (rdev->pm.dpm.ac_power)
4015 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4017 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4021 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4022 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4048 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4052 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4068 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4295 rdev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4885 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4887 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4889 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4912 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4914 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4916 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4918 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5031 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5033 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5035 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5037 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5039 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5041 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5043 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5045 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5047 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5049 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5051 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5053 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5097 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5132 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_enable()
5287 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_disable()
5433 rdev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5435 rdev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5539 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in ci_parse_power_table()
5542 if (!rdev->pm.dpm.ps) in ci_parse_power_table()
5545 rdev->pm.dpm.num_ps = 0; in ci_parse_power_table()
5557 rdev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5558 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ci_parse_power_table()
5573 &rdev->pm.dpm.ps[i], k, in ci_parse_power_table()
5578 rdev->pm.dpm.num_ps = i + 1; in ci_parse_power_table()
5584 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5591 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5592 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5629 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5630 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5632 kfree(rdev->pm.dpm.ps); in ci_dpm_fini()
5633 kfree(rdev->pm.dpm.priv); in ci_dpm_fini()
5634 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5653 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5751 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5755 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5759 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5760 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5761 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5762 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5763 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5764 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5765 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5766 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5767 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5769 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5770 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5771 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5773 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5774 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5775 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5776 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5795 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5798 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5804 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5807 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5847 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
5853 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
5856 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
5862 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
5895 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5896 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5897 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5898 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()