1156 	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);  in dce4_crtc_do_set_base()  local
1204 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1212 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1220 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1227 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1235 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1243 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1253 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1262 		fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |  in dce4_crtc_do_set_base()
1265 		fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1403 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1476 	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;  in avivo_crtc_do_set_base()  local
1525 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1533 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1541 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1550 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1559 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1570 			fb_swap =  in avivo_crtc_do_set_base()
1576 		fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1623 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()