Lines Matching +full:v1 +full:- +full:v6
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in atombios_overscan_setup()
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in atombios_overscan_setup()
65 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in atombios_overscan_setup()
66 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in atombios_overscan_setup()
68 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in atombios_overscan_setup()
69 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in atombios_overscan_setup()
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_overscan_setup()
85 struct drm_device *dev = crtc->dev; in atombios_scaler_setup()
86 struct radeon_device *rdev = dev->dev_private; in atombios_scaler_setup()
91 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
92 /* fixme - fill in enc_priv for atom dac */ in atombios_scaler_setup()
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in atombios_scaler_setup()
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; in atombios_scaler_setup()
101 tv_std = tv_dac->tv_std; in atombios_scaler_setup()
107 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
142 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_scaler_setup()
162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { in atombios_scaler_setup()
170 struct drm_device *dev = crtc->dev; in atombios_lock_crtc()
171 struct radeon_device *rdev = dev->dev_private; in atombios_lock_crtc()
178 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_lock_crtc()
187 struct drm_device *dev = crtc->dev; in atombios_enable_crtc()
188 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc()
194 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc()
203 struct drm_device *dev = crtc->dev; in atombios_enable_crtc_memreq()
204 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc_memreq()
210 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc_memreq()
229 struct drm_device *dev = crtc->dev; in atombios_blank_crtc()
230 struct radeon_device *rdev = dev->dev_private; in atombios_blank_crtc()
238 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
239 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
242 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_blank_crtc()
248 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
254 struct drm_device *dev = crtc->dev; in atombios_powergate_crtc()
255 struct radeon_device *rdev = dev->dev_private; in atombios_powergate_crtc()
261 args.ucDispPipeId = radeon_crtc->crtc_id; in atombios_powergate_crtc()
264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_powergate_crtc()
269 struct drm_device *dev = crtc->dev; in atombios_crtc_dpms()
270 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_dpms()
275 radeon_crtc->enabled = true; in atombios_crtc_dpms()
280 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
287 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
289 if (radeon_crtc->enabled) in atombios_crtc_dpms()
294 radeon_crtc->enabled = false; in atombios_crtc_dpms()
306 struct drm_device *dev = crtc->dev; in atombios_set_crtc_dtd_timing()
307 struct radeon_device *rdev = dev->dev_private; in atombios_set_crtc_dtd_timing()
313 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
315 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
316 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
318 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
320 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
322 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_set_crtc_dtd_timing()
324 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
326 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_set_crtc_dtd_timing()
327 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
328 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
330 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_set_crtc_dtd_timing()
332 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_set_crtc_dtd_timing()
334 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_set_crtc_dtd_timing()
336 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_set_crtc_dtd_timing()
338 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_set_crtc_dtd_timing()
340 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_set_crtc_dtd_timing()
344 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_set_crtc_dtd_timing()
353 struct drm_device *dev = crtc->dev; in atombios_crtc_set_timing()
354 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_timing()
360 args.usH_Total = cpu_to_le16(mode->crtc_htotal); in atombios_crtc_set_timing()
361 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); in atombios_crtc_set_timing()
362 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); in atombios_crtc_set_timing()
364 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_crtc_set_timing()
365 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); in atombios_crtc_set_timing()
366 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); in atombios_crtc_set_timing()
367 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); in atombios_crtc_set_timing()
369 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_crtc_set_timing()
371 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
372 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
373 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
374 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
376 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_crtc_set_timing()
378 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_crtc_set_timing()
380 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_crtc_set_timing()
382 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_crtc_set_timing()
384 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_crtc_set_timing()
386 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_crtc_set_timing()
390 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_timing()
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; member
459 if (ss->percentage == 0) in atombios_crtc_program_ss()
461 if (ss->type & ATOM_EXTERNAL_SS_MASK) in atombios_crtc_program_ss()
464 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_program_ss()
465 if (rdev->mode_info.crtcs[i] && in atombios_crtc_program_ss()
466 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_program_ss()
468 pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_program_ss()
482 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
496 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
497 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
500 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
501 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
515 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
516 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
519 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
520 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
521 args.v1.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
522 args.v1.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
523 args.v1.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
524 args.v1.ucPpll = pll_id; in atombios_crtc_program_ss()
525 args.v1.ucEnable = enable; in atombios_crtc_program_ss()
527 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
528 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
532 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
533 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
534 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
535 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
536 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
543 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
544 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
545 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; in atombios_crtc_program_ss()
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; in atombios_crtc_program_ss()
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_ss()
553 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; member
561 struct drm_device *dev = crtc->dev; in atombios_adjust_pll()
562 struct radeon_device *rdev = dev->dev_private; in atombios_adjust_pll()
563 struct drm_encoder *encoder = radeon_crtc->encoder; in atombios_adjust_pll()
566 u32 adjusted_clock = mode->clock; in atombios_adjust_pll()
568 u32 dp_clock = mode->clock; in atombios_adjust_pll()
569 u32 clock = mode->clock; in atombios_adjust_pll()
570 int bpc = radeon_crtc->bpc; in atombios_adjust_pll()
571 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); in atombios_adjust_pll()
574 radeon_crtc->pll_flags = 0; in atombios_adjust_pll()
577 if ((rdev->family == CHIP_RS600) || in atombios_adjust_pll()
578 (rdev->family == CHIP_RS690) || in atombios_adjust_pll()
579 (rdev->family == CHIP_RS740)) in atombios_adjust_pll()
580 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
588 if (rdev->family < CHIP_RV770) in atombios_adjust_pll()
589 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
594 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) in atombios_adjust_pll()
595 && !radeon_crtc->ss_enabled) in atombios_adjust_pll()
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) in atombios_adjust_pll()
598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
600 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
602 if (mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
605 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
608 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_adjust_pll()
613 radeon_connector->con_priv; in atombios_adjust_pll()
615 dp_clock = dig_connector->dp_clock; in atombios_adjust_pll()
619 if (radeon_encoder->is_mst_encoder) { in atombios_adjust_pll()
620 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; in atombios_adjust_pll()
621 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; in atombios_adjust_pll()
623 dp_clock = dig_connector->dp_clock; in atombios_adjust_pll()
627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in atombios_adjust_pll()
628 if (radeon_crtc->ss_enabled) { in atombios_adjust_pll()
629 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
630 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
631 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
633 rdev->family != CHIP_RS780 && in atombios_adjust_pll()
634 rdev->family != CHIP_RS880) in atombios_adjust_pll()
635 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
642 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in atombios_adjust_pll()
643 adjusted_clock = mode->clock * 2; in atombios_adjust_pll()
644 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_adjust_pll()
645 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
646 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in atombios_adjust_pll()
647 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
649 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) in atombios_adjust_pll()
650 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
651 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) in atombios_adjust_pll()
652 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
683 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_adjust_pll()
694 args.v1.usPixelClock = cpu_to_le16(clock / 10); in atombios_adjust_pll()
695 args.v1.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
696 args.v1.ucEncodeMode = encoder_mode; in atombios_adjust_pll()
697 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
698 args.v1.ucConfig |= in atombios_adjust_pll()
701 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
703 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; in atombios_adjust_pll()
707 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
710 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
718 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in atombios_adjust_pll()
719 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_adjust_pll()
720 if (dig->coherent_mode) in atombios_adjust_pll()
734 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
740 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
743 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
744 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
745 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
763 PIXEL_CLOCK_PARAMETERS v1; member
767 PIXEL_CLOCK_PARAMETERS_V6 v6; member
783 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_set_disp_eng_pll()
802 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); in atombios_crtc_set_disp_eng_pll()
804 args.v6.ucPpll = ATOM_EXT_PLL1; in atombios_crtc_set_disp_eng_pll()
806 args.v6.ucPpll = ATOM_PPLL0; in atombios_crtc_set_disp_eng_pll()
808 args.v6.ucPpll = ATOM_DCPLL; in atombios_crtc_set_disp_eng_pll()
819 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_disp_eng_pll()
836 struct drm_device *dev = crtc->dev; in atombios_crtc_program_pll()
837 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_program_pll()
844 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_program_pll()
854 args.v1.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
855 args.v1.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
856 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
857 args.v1.ucFracFbDiv = frac_fb_div; in atombios_crtc_program_pll()
858 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll()
859 args.v1.ucPpll = pll_id; in atombios_crtc_program_pll()
860 args.v1.ucCRTC = crtc_id; in atombios_crtc_program_pll()
861 args.v1.ucRefDivSrc = 1; in atombios_crtc_program_pll()
884 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
897 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
920 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); in atombios_crtc_program_pll()
921 args.v6.ucRefDiv = ref_div; in atombios_crtc_program_pll()
922 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
923 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); in atombios_crtc_program_pll()
924 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll()
925 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ in atombios_crtc_program_pll()
926 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
927 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; in atombios_crtc_program_pll()
932 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; in atombios_crtc_program_pll()
935 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; in atombios_crtc_program_pll()
938 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; in atombios_crtc_program_pll()
941 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; in atombios_crtc_program_pll()
945 args.v6.ucTransmitterID = encoder_id; in atombios_crtc_program_pll()
946 args.v6.ucEncoderMode = encoder_mode; in atombios_crtc_program_pll()
947 args.v6.ucPpll = pll_id; in atombios_crtc_program_pll()
959 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_pll()
965 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare_pll()
966 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare_pll()
968 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
969 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
971 radeon_crtc->bpc = 8; in atombios_crtc_prepare_pll()
972 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
974 if (radeon_encoder->is_mst_encoder) { in atombios_crtc_prepare_pll()
976 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_crtc_prepare_pll()
977 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in atombios_crtc_prepare_pll()
978 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_crtc_prepare_pll()
980 radeon_get_connector_for_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
984 radeon_connector->con_priv; in atombios_crtc_prepare_pll()
988 radeon_connector->pixelclock_for_modeset = mode->clock; in atombios_crtc_prepare_pll()
989 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); in atombios_crtc_prepare_pll()
995 dp_clock = dig_connector->dp_clock / 10; in atombios_crtc_prepare_pll()
997 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
998 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1003 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1005 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1007 if (!radeon_crtc->ss_enabled) in atombios_crtc_prepare_pll()
1008 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1010 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1013 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1015 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1019 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
1024 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1026 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1027 dig->lcd_ss_id, in atombios_crtc_prepare_pll()
1028 mode->clock / 10); in atombios_crtc_prepare_pll()
1030 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1032 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1033 dig->lcd_ss_id); in atombios_crtc_prepare_pll()
1037 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1039 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1041 mode->clock / 10); in atombios_crtc_prepare_pll()
1045 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1047 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1049 mode->clock / 10); in atombios_crtc_prepare_pll()
1057 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); in atombios_crtc_prepare_pll()
1065 struct drm_device *dev = crtc->dev; in atombios_crtc_set_pll()
1066 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_pll()
1068 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_set_pll()
1069 u32 pll_clock = mode->clock; in atombios_crtc_set_pll()
1070 u32 clock = mode->clock; in atombios_crtc_set_pll()
1073 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_set_pll()
1078 (radeon_crtc->bpc > 8)) in atombios_crtc_set_pll()
1079 clock = radeon_crtc->adjusted_clock; in atombios_crtc_set_pll()
1081 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
1083 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1086 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1091 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1096 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1097 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1098 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1100 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_crtc_set_pll()
1102 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1105 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1108 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1111 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1112 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1114 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1115 encoder_mode, radeon_encoder->encoder_id, clock, in atombios_crtc_set_pll()
1117 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1119 if (radeon_crtc->ss_enabled) { in atombios_crtc_set_pll()
1124 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1125 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1126 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1127 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1129 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1130 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1131 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1133 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1134 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1135 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1138 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1139 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1148 struct drm_device *dev = crtc->dev; in dce4_crtc_do_set_base()
1149 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_do_set_base()
1162 if (!atomic && !crtc->primary->fb) { in dce4_crtc_do_set_base()
1170 target_fb = crtc->primary->fb; in dce4_crtc_do_set_base()
1175 obj = target_fb->obj[0]; in dce4_crtc_do_set_base()
1187 return -EINVAL; in dce4_crtc_do_set_base()
1194 switch (target_fb->format->format) { in dce4_crtc_do_set_base()
1245 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1255 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1270 &target_fb->format->format); in dce4_crtc_do_set_base()
1271 return -EINVAL; in dce4_crtc_do_set_base()
1278 if (rdev->family >= CHIP_TAHITI) { in dce4_crtc_do_set_base()
1281 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1286 tileb = 8 * 8 * target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1294 target_fb->format->cpp[0] * 8, in dce4_crtc_do_set_base()
1296 return -EINVAL; in dce4_crtc_do_set_base()
1299 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()
1301 switch (target_fb->format->cpp[0] * 8) { in dce4_crtc_do_set_base()
1314 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; in dce4_crtc_do_set_base()
1320 if (rdev->family >= CHIP_CAYMAN) in dce4_crtc_do_set_base()
1321 tmp = rdev->config.cayman.tile_config; in dce4_crtc_do_set_base()
1323 tmp = rdev->config.evergreen.tile_config; in dce4_crtc_do_set_base()
1344 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1351 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1355 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
1358 } else if ((rdev->family == CHIP_TAHITI) || in dce4_crtc_do_set_base()
1359 (rdev->family == CHIP_PITCAIRN)) in dce4_crtc_do_set_base()
1361 else if ((rdev->family == CHIP_VERDE) || in dce4_crtc_do_set_base()
1362 (rdev->family == CHIP_OLAND) || in dce4_crtc_do_set_base()
1363 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ in dce4_crtc_do_set_base()
1366 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1392 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1394 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1396 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1398 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1400 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1402 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1403 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1410 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1417 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1418 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1419 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1420 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1421 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1422 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1424 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1425 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1426 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1428 if (rdev->family >= CHIP_BONAIRE) in dce4_crtc_do_set_base()
1429 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1430 target_fb->height); in dce4_crtc_do_set_base()
1432 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1433 target_fb->height); in dce4_crtc_do_set_base()
1436 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1438 viewport_w = crtc->mode.hdisplay; in dce4_crtc_do_set_base()
1439 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce4_crtc_do_set_base()
1440 if ((rdev->family >= CHIP_BONAIRE) && in dce4_crtc_do_set_base()
1441 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) in dce4_crtc_do_set_base()
1443 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1447 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1449 if (!atomic && fb && fb != crtc->primary->fb) { in dce4_crtc_do_set_base()
1450 rbo = gem_to_radeon_bo(fb->obj[0]); in dce4_crtc_do_set_base()
1469 struct drm_device *dev = crtc->dev; in avivo_crtc_do_set_base()
1470 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_do_set_base()
1482 if (!atomic && !crtc->primary->fb) { in avivo_crtc_do_set_base()
1490 target_fb = crtc->primary->fb; in avivo_crtc_do_set_base()
1492 obj = target_fb->obj[0]; in avivo_crtc_do_set_base()
1507 return -EINVAL; in avivo_crtc_do_set_base()
1513 switch (target_fb->format->format) { in avivo_crtc_do_set_base()
1561 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in avivo_crtc_do_set_base()
1569 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1581 &target_fb->format->format); in avivo_crtc_do_set_base()
1582 return -EINVAL; in avivo_crtc_do_set_base()
1585 if (rdev->family >= CHIP_R600) { in avivo_crtc_do_set_base()
1598 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1606 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1608 if (rdev->family >= CHIP_RV770) { in avivo_crtc_do_set_base()
1609 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1617 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1620 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1621 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1622 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1623 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1626 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1632 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1633 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1634 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1635 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1636 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1637 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1639 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in avivo_crtc_do_set_base()
1640 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1641 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1643 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1644 target_fb->height); in avivo_crtc_do_set_base()
1647 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1649 viewport_w = crtc->mode.hdisplay; in avivo_crtc_do_set_base()
1650 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in avivo_crtc_do_set_base()
1651 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1655 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
1657 if (!atomic && fb && fb != crtc->primary->fb) { in avivo_crtc_do_set_base()
1658 rbo = gem_to_radeon_bo(fb->obj[0]); in avivo_crtc_do_set_base()
1675 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base()
1676 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base()
1690 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base_atomic()
1691 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base_atomic()
1704 struct drm_device *dev = crtc->dev; in radeon_legacy_atom_fixup()
1705 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_atom_fixup()
1709 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1726 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1734 struct drm_device *dev = crtc->dev; in radeon_get_pll_use_mask()
1739 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_pll_use_mask()
1744 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_pll_use_mask()
1745 pll_in_use |= (1 << test_radeon_crtc->pll_id); in radeon_get_pll_use_mask()
1751 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1761 struct drm_device *dev = crtc->dev; in radeon_get_shared_dp_ppll()
1762 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_dp_ppll()
1766 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_dp_ppll()
1770 if (test_radeon_crtc->encoder && in radeon_get_shared_dp_ppll()
1771 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_dp_ppll()
1774 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_dp_ppll()
1777 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_dp_ppll()
1778 return test_radeon_crtc->pll_id; in radeon_get_shared_dp_ppll()
1785 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1789 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1795 struct drm_device *dev = crtc->dev; in radeon_get_shared_nondp_ppll()
1796 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_nondp_ppll()
1801 adjusted_clock = radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1806 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_nondp_ppll()
1810 if (test_radeon_crtc->encoder && in radeon_get_shared_nondp_ppll()
1811 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_nondp_ppll()
1814 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_nondp_ppll()
1817 if (test_radeon_crtc->connector == radeon_crtc->connector) { in radeon_get_shared_nondp_ppll()
1819 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_nondp_ppll()
1820 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1822 /* for non-DP check the clock */ in radeon_get_shared_nondp_ppll()
1823 test_adjusted_clock = test_radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1824 if ((crtc->mode.clock == test_crtc->mode.clock) && in radeon_get_shared_nondp_ppll()
1826 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && in radeon_get_shared_nondp_ppll()
1827 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) in radeon_get_shared_nondp_ppll()
1828 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1835 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1840 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1851 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1853 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1856 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1857 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1860 * - PPLL0 is available to all UNIPHY (DP only)
1861 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1864 * - DCPLL is available to all UNIPHY (DP only)
1865 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1868 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1874 struct drm_device *dev = crtc->dev; in radeon_atom_pick_pll()
1875 struct radeon_device *rdev = dev->dev_private; in radeon_atom_pick_pll()
1877 to_radeon_encoder(radeon_crtc->encoder); in radeon_atom_pick_pll()
1882 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1883 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1899 if ((rdev->family == CHIP_KABINI) || in radeon_atom_pick_pll()
1900 (rdev->family == CHIP_MULLINS)) { in radeon_atom_pick_pll()
1923 radeon_encoder->enc_priv; in radeon_atom_pick_pll()
1925 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && in radeon_atom_pick_pll()
1926 (dig->linkb == false)) in radeon_atom_pick_pll()
1929 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1931 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1956 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1957 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1979 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1980 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
2010 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ in radeon_atom_pick_pll()
2025 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
2033 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2038 rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2040 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2042 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2044 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2055 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_set()
2056 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_mode_set()
2058 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_set()
2061 if (radeon_encoder->active_device & in atombios_crtc_mode_set()
2065 if (!radeon_crtc->adjusted_clock) in atombios_crtc_mode_set()
2066 return -EINVAL; in atombios_crtc_mode_set()
2079 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
2088 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
2098 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_fixup()
2102 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_crtc_mode_fixup()
2103 if (encoder->crtc == crtc) { in atombios_crtc_mode_fixup()
2104 radeon_crtc->encoder = encoder; in atombios_crtc_mode_fixup()
2105 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); in atombios_crtc_mode_fixup()
2109 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { in atombios_crtc_mode_fixup()
2110 radeon_crtc->encoder = NULL; in atombios_crtc_mode_fixup()
2111 radeon_crtc->connector = NULL; in atombios_crtc_mode_fixup()
2114 if (radeon_crtc->encoder) { in atombios_crtc_mode_fixup()
2116 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_fixup()
2118 radeon_crtc->output_csc = radeon_encoder->output_csc; in atombios_crtc_mode_fixup()
2125 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_mode_fixup()
2126 /* if we can't get a PPLL for a non-DP encoder, fail */ in atombios_crtc_mode_fixup()
2127 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && in atombios_crtc_mode_fixup()
2128 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) in atombios_crtc_mode_fixup()
2136 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare()
2137 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare()
2156 struct drm_device *dev = crtc->dev; in atombios_crtc_disable()
2157 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_disable()
2162 if (crtc->primary->fb) { in atombios_crtc_disable()
2166 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); in atombios_crtc_disable()
2177 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2179 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2184 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_disable()
2185 if (rdev->mode_info.crtcs[i] && in atombios_crtc_disable()
2186 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_disable()
2187 i != radeon_crtc->crtc_id && in atombios_crtc_disable()
2188 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
2196 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
2200 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2205 if ((rdev->family == CHIP_ARUBA) || in atombios_crtc_disable()
2206 (rdev->family == CHIP_KAVERI) || in atombios_crtc_disable()
2207 (rdev->family == CHIP_BONAIRE) || in atombios_crtc_disable()
2208 (rdev->family == CHIP_HAWAII)) in atombios_crtc_disable()
2209 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2216 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in atombios_crtc_disable()
2217 radeon_crtc->adjusted_clock = 0; in atombios_crtc_disable()
2218 radeon_crtc->encoder = NULL; in atombios_crtc_disable()
2219 radeon_crtc->connector = NULL; in atombios_crtc_disable()
2237 struct radeon_device *rdev = dev->dev_private; in radeon_atombios_init_crtc()
2240 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2246 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2249 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2252 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2255 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2258 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2262 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
2263 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2264 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; in radeon_atombios_init_crtc()
2266 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
2268 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in radeon_atombios_init_crtc()
2269 radeon_crtc->adjusted_clock = 0; in radeon_atombios_init_crtc()
2270 radeon_crtc->encoder = NULL; in radeon_atombios_init_crtc()
2271 radeon_crtc->connector = NULL; in radeon_atombios_init_crtc()
2272 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()