Lines Matching +full:0 +full:x1740
64 #define DRIVER_PATCHLEVEL 0
187 #define R128_AUX_SC_CNTL 0x1660
188 # define R128_AUX1_SC_EN (1 << 0)
189 # define R128_AUX1_SC_MODE_OR (0 << 1)
192 # define R128_AUX2_SC_MODE_OR (0 << 3)
195 # define R128_AUX3_SC_MODE_OR (0 << 5)
197 #define R128_AUX1_SC_LEFT 0x1664
198 #define R128_AUX1_SC_RIGHT 0x1668
199 #define R128_AUX1_SC_TOP 0x166c
200 #define R128_AUX1_SC_BOTTOM 0x1670
201 #define R128_AUX2_SC_LEFT 0x1674
202 #define R128_AUX2_SC_RIGHT 0x1678
203 #define R128_AUX2_SC_TOP 0x167c
204 #define R128_AUX2_SC_BOTTOM 0x1680
205 #define R128_AUX3_SC_LEFT 0x1684
206 #define R128_AUX3_SC_RIGHT 0x1688
207 #define R128_AUX3_SC_TOP 0x168c
208 #define R128_AUX3_SC_BOTTOM 0x1690
210 #define R128_BRUSH_DATA0 0x1480
211 #define R128_BUS_CNTL 0x0030
214 #define R128_CLOCK_CNTL_INDEX 0x0008
215 #define R128_CLOCK_CNTL_DATA 0x000c
217 #define R128_CONSTANT_COLOR_C 0x1d34
218 #define R128_CRTC_OFFSET 0x0224
219 #define R128_CRTC_OFFSET_CNTL 0x0228
222 #define R128_DP_GUI_MASTER_CNTL 0x146c
223 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
237 # define R128_ROP3_S 0x00cc0000
238 # define R128_ROP3_P 0x00f00000
239 #define R128_DP_WRITE_MASK 0x16cc
240 #define R128_DST_PITCH_OFFSET_C 0x1c80
243 #define R128_GEN_INT_CNTL 0x0040
244 # define R128_CRTC_VBLANK_INT_EN (1 << 0)
245 #define R128_GEN_INT_STATUS 0x0044
246 # define R128_CRTC_VBLANK_INT (1 << 0)
247 # define R128_CRTC_VBLANK_INT_AK (1 << 0)
248 #define R128_GEN_RESET_CNTL 0x00f0
249 # define R128_SOFT_RESET_GUI (1 << 0)
251 #define R128_GUI_SCRATCH_REG0 0x15e0
252 #define R128_GUI_SCRATCH_REG1 0x15e4
253 #define R128_GUI_SCRATCH_REG2 0x15e8
254 #define R128_GUI_SCRATCH_REG3 0x15ec
255 #define R128_GUI_SCRATCH_REG4 0x15f0
256 #define R128_GUI_SCRATCH_REG5 0x15f4
258 #define R128_GUI_STAT 0x1740
259 # define R128_GUI_FIFOCNT_MASK 0x0fff
262 #define R128_MCLK_CNTL 0x000f
267 #define R128_PC_GUI_CTLSTAT 0x1748
268 #define R128_PC_NGUI_CTLSTAT 0x0184
269 # define R128_PC_FLUSH_GUI (3 << 0)
271 # define R128_PC_FLUSH_ALL 0x00ff
274 #define R128_PCI_GART_PAGE 0x017c
275 #define R128_PRIM_TEX_CNTL_C 0x1cb0
277 #define R128_SCALE_3D_CNTL 0x1a00
278 #define R128_SEC_TEX_CNTL_C 0x1d00
279 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
280 #define R128_SETUP_CNTL 0x1bc4
281 #define R128_STEN_REF_MASK_C 0x1d40
283 #define R128_TEX_CNTL_C 0x1c9c
286 #define R128_WAIT_UNTIL 0x1720
287 # define R128_EVENT_CRTC_OFFSET (1 << 0)
288 #define R128_WINDOW_XY_OFFSET 0x1bcc
292 #define R128_PM4_BUFFER_OFFSET 0x0700
293 #define R128_PM4_BUFFER_CNTL 0x0704
295 # define R128_PM4_NONPM4 (0 << 28)
307 #define R128_PM4_BUFFER_WM_CNTL 0x0708
308 # define R128_WMA_SHIFT 0
313 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
314 #define R128_PM4_BUFFER_DL_RPTR 0x0710
315 #define R128_PM4_BUFFER_DL_WPTR 0x0714
318 #define R128_PM4_VC_FPU_SETUP 0x071c
320 #define R128_PM4_IW_INDOFF 0x0738
321 #define R128_PM4_IW_INDSIZE 0x073c
323 #define R128_PM4_STAT 0x07b8
324 # define R128_PM4_FIFOCNT_MASK 0x0fff
328 #define R128_PM4_MICROCODE_ADDR 0x07d4
329 #define R128_PM4_MICROCODE_RADDR 0x07d8
330 #define R128_PM4_MICROCODE_DATAH 0x07dc
331 #define R128_PM4_MICROCODE_DATAL 0x07e0
333 #define R128_PM4_BUFFER_ADDR 0x07f0
334 #define R128_PM4_MICRO_CNTL 0x07fc
337 #define R128_PM4_FIFO_DATA_EVEN 0x1000
338 #define R128_PM4_FIFO_DATA_ODD 0x1004
342 #define R128_CCE_PACKET0 0x00000000
343 #define R128_CCE_PACKET1 0x40000000
344 #define R128_CCE_PACKET2 0x80000000
345 #define R128_CCE_PACKET3 0xC0000000
346 # define R128_CNTL_HOSTDATA_BLT 0x00009400
347 # define R128_CNTL_PAINT_MULTI 0x00009A00
348 # define R128_CNTL_BITBLT_MULTI 0x00009B00
349 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
351 #define R128_CCE_PACKET_MASK 0xC0000000
352 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
353 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
354 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
355 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
357 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
358 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
359 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
360 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
361 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
362 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
363 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
364 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
365 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
366 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
367 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
370 #define R128_DATATYPE_VQ 0
387 #define R128_AGP_OFFSET 0x02000000
398 #define R128_MAX_VB_AGE 0x7fffffff
399 #define R128_MAX_VB_VERTS (0xffff)
403 #define R128_PERFORMANCE_BOXES 0
415 ((addr) & 0x1f) | R128_PLL_WR_EN); \
417 } while (0)
431 if (ring->space <= 0) in r128_update_ring_snapshot()
445 } while (0)
451 for (i = 0 ; i < dev_priv->usec_timeout ; i++) { \
462 } while (0)
471 sarea_priv->last_dispatch = 0; \
474 } while (0)
477 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
479 } while (0)
485 #define R128_VERBOSE 0
501 } while (0)
512 DRM_INFO("ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
525 } while (0)
529 DRM_INFO("COMMIT_RING() tail=0x%06x\n", \
534 } while (0)
538 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
542 } while (0)