Lines Matching +full:counter +full:- +full:clockwise
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
174 /* maps which plane is using a fifo. fifo-id -> plane-id */
356 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
361 return __raw_readl(dispc->base + idx); in dispc_read_reg()
369 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
377 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
382 return dispc->feat->num_ovls; in dispc_get_num_ovls()
387 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
394 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
396 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
397 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
405 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
406 if (dispc->feat->features[i] == id) in dispc_has_feature()
414 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
416 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
520 dispc->ctx_valid = true; in dispc_save_context()
531 if (!dispc->ctx_valid) in dispc_restore_context()
653 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
655 pm_runtime_put_noidle(&dispc->pdev->dev); in dispc_runtime_get()
667 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
668 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
680 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
811 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
871 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
873 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
878 /* YUV -> RGB, ITU-R BT.601, full range */
881 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
886 /* YUV -> RGB, ITU-R BT.601, limited range */
889 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
894 /* YUV -> RGB, ITU-R BT.709, full range */
897 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
902 /* YUV -> RGB, ITU-R BT.709, limited range */
905 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
978 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size()
994 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_output_size()
1271 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1279 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1288 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1301 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1322 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | in dispc_mgr_set_cpr_coef()
1323 FLD_VAL(coefs->rb, 9, 0); in dispc_mgr_set_cpr_coef()
1324 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | in dispc_mgr_set_cpr_coef()
1325 FLD_VAL(coefs->gb, 9, 0); in dispc_mgr_set_cpr_coef()
1326 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | in dispc_mgr_set_cpr_coef()
1327 FLD_VAL(coefs->bb, 9, 0); in dispc_mgr_set_cpr_coef()
1366 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1367 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1380 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1384 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1388 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1394 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1404 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1416 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1417 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1434 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1453 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1454 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1455 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1468 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1499 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1524 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1540 * We use the same low threshold for both fifomerge and non-fifomerge in dispc_ovl_compute_fifo_thresholds()
1546 *fifo_low = ovl_fifo_size - burst_size * 2; in dispc_ovl_compute_fifo_thresholds()
1547 *fifo_high = total_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1557 *fifo_low = ovl_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1558 *fifo_high = total_fifo_size - buf_unit; in dispc_ovl_compute_fifo_thresholds()
1595 * As a work-around, set force MFLAG to always on. in dispc_init_mflag()
1603 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1620 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1622 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1759 { 0, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1760 { 1, 2, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1761 { -1, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1762 { -1, 2, -1, 2 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1766 { 0, 1, 0, 1 , -3, 4, -1, 4 }, in dispc_ovl_set_accu_uv()
1767 { -1, 4, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1768 { -1, 1, 0, 1 , -1, 4, -3, 4 }, in dispc_ovl_set_accu_uv()
1769 { -3, 4, -3, 4 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1775 { -1, 1, 0, 1, 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1776 { 0, 1, 0, 1, -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1779 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_accu_uv()
1817 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; in dispc_ovl_set_accu_uv()
1818 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; in dispc_ovl_set_accu_uv()
1819 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; in dispc_ovl_set_accu_uv()
1820 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; in dispc_ovl_set_accu_uv()
1873 accu0 -= accu1; in dispc_ovl_set_scaling_common()
1899 if (!info->is_yuv) { in dispc_ovl_set_scaling_uv()
1991 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_rotation_attrs()
2090 return 1 + (pixels - 1) * ps; in pixinc()
2092 return 1 - (-pixels + 1) * ps; in pixinc()
2130 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + in calc_offset()
2153 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + in check_horiz_timing_omap3()
2154 vm->hback_porch - out_width; in check_horiz_timing_omap3()
2161 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * in check_horiz_timing_omap3()
2165 return -EINVAL; in check_horiz_timing_omap3()
2167 /* FIXME add checks for 3-tap filter once the limitations are known */ in check_horiz_timing_omap3()
2173 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2174 * during nonactive - pos_x period. in check_horiz_timing_omap3()
2176 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2177 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", in check_horiz_timing_omap3()
2178 val, max(0, ds - 2) * width); in check_horiz_timing_omap3()
2179 if (val < max(0, ds - 2) * width) in check_horiz_timing_omap3()
2180 return -EINVAL; in check_horiz_timing_omap3()
2185 * DS - 1 lines should be loaded during nonactive period. in check_horiz_timing_omap3()
2188 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", in check_horiz_timing_omap3()
2189 val, max(0, ds - 1) * width); in check_horiz_timing_omap3()
2190 if (val < max(0, ds - 1) * width) in check_horiz_timing_omap3()
2191 return -EINVAL; in check_horiz_timing_omap3()
2208 unsigned int ppl = vm->hactive; in calc_core_clk_five_taps()
2218 tmp = (u64)pclk * (height - 2 * out_height) * out_width; in calc_core_clk_five_taps()
2219 do_div(tmp, 2 * out_height * (ppl - out_width)); in calc_core_clk_five_taps()
2303 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2310 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2328 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2333 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2351 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2368 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2404 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2410 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2416 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2421 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2440 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2441 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2454 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2463 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2478 * be true also for 16-bit color formats. in dispc_ovl_calc_scaling_44xx()
2480 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x); in dispc_ovl_calc_scaling_44xx()
2482 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2485 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2491 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2505 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2506 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2514 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2515 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2524 return -EINVAL; in dispc_ovl_calc_scaling()
2541 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { in dispc_ovl_calc_scaling()
2543 return -EINVAL; in dispc_ovl_calc_scaling()
2547 return -EINVAL; in dispc_ovl_calc_scaling()
2562 return -EINVAL; in dispc_ovl_calc_scaling()
2565 return -EINVAL; in dispc_ovl_calc_scaling()
2567 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2575 …DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req cl… in dispc_ovl_calc_scaling()
2594 return -EINVAL; in dispc_ovl_calc_scaling()
2628 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); in dispc_ovl_setup_common()
2637 pclk = vm->pixelclock; in dispc_ovl_setup_common()
2640 return -EINVAL; in dispc_ovl_setup_common()
2642 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2644 return -EINVAL; in dispc_ovl_setup_common()
2666 return -EINVAL; in dispc_ovl_setup_common()
2682 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2684 DSSDBG("adjusting input width %d -> %d\n", in dispc_ovl_setup_common()
2690 if (info->is_yuv) in dispc_ovl_setup_common()
2734 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2745 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2746 row_inc += pix_inc - 1; in dispc_ovl_setup_common()
2751 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, in dispc_ovl_setup_common()
2788 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2791 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" in dispc_ovl_setup()
2793 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, in dispc_ovl_setup()
2794 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, in dispc_ovl_setup()
2795 oi->fourcc, oi->rotation, channel, replication); in dispc_ovl_setup()
2799 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2800 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, in dispc_ovl_setup()
2801 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, in dispc_ovl_setup()
2802 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, in dispc_ovl_setup()
2803 oi->rotation_type, replication, vm, mem_to_mem, in dispc_ovl_setup()
2804 oi->color_encoding, oi->color_range); in dispc_ovl_setup()
2821 int in_width = vm->hactive; in dispc_wb_setup()
2822 int in_height = vm->vactive; in dispc_wb_setup()
2826 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_wb_setup()
2829 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " in dispc_wb_setup()
2830 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, in dispc_wb_setup()
2831 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); in dispc_wb_setup()
2833 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2834 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, in dispc_wb_setup()
2835 wi->height, wi->fourcc, wi->rotation, zorder, in dispc_wb_setup()
2836 wi->pre_mult_alpha, global_alpha, wi->rotation_type, in dispc_wb_setup()
2842 switch (wi->fourcc) { in dispc_wb_setup()
2876 wbdelay = vm->vsync_len + vm->vback_porch; in dispc_wb_setup()
2878 wbdelay = vm->vfront_porch + vm->vsync_len + in dispc_wb_setup()
2879 vm->vback_porch; in dispc_wb_setup()
2881 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_wb_setup()
2895 return dispc->feat->has_writeback; in dispc_has_writeback()
2993 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
2994 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
2995 info->trans_key); in dispc_mgr_setup()
2996 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
2998 info->partial_alpha_enabled); in dispc_mgr_setup()
3000 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
3001 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
3072 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3074 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3075 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3077 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3079 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3081 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3089 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3090 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3097 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3098 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3099 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3100 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3101 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3102 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3112 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3114 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3121 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3124 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3129 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_mgr_check_timings()
3132 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3133 vm->hfront_porch, vm->hback_porch, in dispc_mgr_check_timings()
3134 vm->vsync_len, vm->vfront_porch, in dispc_mgr_check_timings()
3135 vm->vback_porch)) in dispc_mgr_check_timings()
3149 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3150 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3151 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3152 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3153 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3154 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3159 vs = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3160 hs = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3161 de = !!(vm->flags & DISPLAY_FLAGS_DE_LOW); in _dispc_mgr_set_lcd_timings()
3162 ipc = !!(vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE); in _dispc_mgr_set_lcd_timings()
3164 rf = !!(vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE); in _dispc_mgr_set_lcd_timings()
3174 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3179 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3194 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3205 return -1; in vm_flag_to_int()
3231 ht = vm->pixelclock / xtot; in dispc_mgr_set_timings()
3232 vt = vm->pixelclock / xtot / ytot; in dispc_mgr_set_timings()
3234 DSSDBG("pck %lu\n", vm->pixelclock); in dispc_mgr_set_timings()
3250 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3271 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3289 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3292 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3297 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3300 r = pll->cinfo.clkout[clkout_idx]; in dispc_fclk_rate()
3317 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3320 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3325 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3328 r = pll->cinfo.clkout[clkout_idx]; in dispc_mgr_lclk_rate()
3353 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3359 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3364 return dispc->core_clk_rate; in dispc_core_clk_rate()
3400 seq_printf(s, "- %s -\n", mgr_desc[channel].name); in dispc_dump_clocks_channel()
3402 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3409 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks_channel()
3411 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", in dispc_dump_clocks_channel()
3424 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3426 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3430 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3433 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3437 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks()
3453 struct dispc_device *dispc = s->private; in dispc_dump_regs()
3471 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3505 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ in dispc_dump_regs()
3574 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3609 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ in dispc_dump_regs()
3655 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) in dispc_calc_clock_rates()
3656 return -EINVAL; in dispc_calc_clock_rates()
3657 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) in dispc_calc_clock_rates()
3658 return -EINVAL; in dispc_calc_clock_rates()
3660 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; in dispc_calc_clock_rates()
3661 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_calc_clock_rates()
3684 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3687 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3730 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); in dispc_mgr_set_clock_div()
3731 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); in dispc_mgr_set_clock_div()
3733 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3734 cinfo->pck_div); in dispc_mgr_set_clock_div()
3745 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3746 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3748 cinfo->lck = fck / cinfo->lck_div; in dispc_mgr_get_clock_div()
3749 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_mgr_get_clock_div()
3793 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3796 return gdesc->len; in dispc_mgr_gamma_size()
3803 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3808 for (i = 0; i < gdesc->len; ++i) { in dispc_mgr_write_gamma_table()
3811 if (gdesc->has_index) in dispc_mgr_write_gamma_table()
3816 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3824 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3849 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3853 channel, length, gdesc->len); in dispc_mgr_set_gamma()
3855 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3863 for (i = 0; i < length - 1; ++i) { in dispc_mgr_set_gamma()
3864 uint first = i * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3865 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3866 uint w = last - first; in dispc_mgr_set_gamma()
3874 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; in dispc_mgr_set_gamma()
3875 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; in dispc_mgr_set_gamma()
3876 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; in dispc_mgr_set_gamma()
3878 r >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3879 g >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3880 b >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3882 table[first + j] = (r << (gdesc->bits * 2)) | in dispc_mgr_set_gamma()
3883 (g << gdesc->bits) | b; in dispc_mgr_set_gamma()
3887 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3895 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3898 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3910 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3913 return -ENOMEM; in dispc_init_gamma_tables()
3915 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3934 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3938 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3942 * func-clock auto-gating. For newer versions in _omap_dispc_initial_config()
3943 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. in _omap_dispc_initial_config()
3946 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3957 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
4493 if (!dispc->is_enabled) in dispc_irq_handler()
4496 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4504 if (dispc->user_handler != NULL) in dispc_request_irq()
4505 return -EBUSY; in dispc_request_irq()
4507 dispc->user_handler = handler; in dispc_request_irq()
4508 dispc->user_data = dev_id; in dispc_request_irq()
4513 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4516 dispc->user_handler = NULL; in dispc_request_irq()
4517 dispc->user_data = NULL; in dispc_request_irq()
4525 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4527 dispc->user_handler = NULL; in dispc_free_irq()
4528 dispc->user_data = NULL; in dispc_free_irq()
4536 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4544 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4615 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4621 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4624 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4626 return -ENOMEM; in dispc_errata_i734_wa_init()
4634 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4637 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4650 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4669 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4687 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4703 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4704 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4705 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4706 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4707 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4729 struct device_node *np = pdev->dev.of_node; in dispc_bind()
4733 return -ENOMEM; in dispc_bind()
4735 dispc->pdev = pdev; in dispc_bind()
4737 dispc->dss = dss; in dispc_bind()
4740 * The OMAP3-based models can't be told apart using the compatible in dispc_bind()
4745 dispc->feat = soc->data; in dispc_bind()
4747 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; in dispc_bind()
4753 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); in dispc_bind()
4754 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); in dispc_bind()
4755 if (IS_ERR(dispc->base)) { in dispc_bind()
4756 r = PTR_ERR(dispc->base); in dispc_bind()
4760 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4761 if (dispc->irq < 0) { in dispc_bind()
4763 r = -ENODEV; in dispc_bind()
4767 if (np && of_property_read_bool(np, "syscon-pol")) { in dispc_bind()
4768 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4769 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4770 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); in dispc_bind()
4771 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4775 if (of_property_read_u32_index(np, "syscon-pol", 1, in dispc_bind()
4776 &dispc->syscon_pol_offset)) { in dispc_bind()
4777 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); in dispc_bind()
4778 r = -EINVAL; in dispc_bind()
4787 pm_runtime_enable(&pdev->dev); in dispc_bind()
4796 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
4801 dss->dispc = dispc; in dispc_bind()
4803 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4809 pm_runtime_disable(&pdev->dev); in dispc_bind()
4818 struct dss_device *dss = dispc->dss; in dispc_unbind()
4820 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4822 dss->dispc = NULL; in dispc_unbind()
4838 return component_add(&pdev->dev, &dispc_component_ops); in dispc_probe()
4843 component_del(&pdev->dev, &dispc_component_ops); in dispc_remove()
4851 dispc->is_enabled = false; in dispc_runtime_suspend()
4855 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4882 dispc->is_enabled = true; in dispc_runtime_resume()