Lines Matching +full:0 +full:xc0000000
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
84 zbc = (zbc < 0) ? i : zbc; in gf100_gr_zbc_color_get()
88 if (zbc < 0) in gf100_gr_zbc_color_get()
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
106 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ in gf100_gr_zbc_clear_depth()
129 zbc = (zbc < 0) ? i : zbc; in gf100_gr_zbc_depth_get()
133 if (zbc < 0) in gf100_gr_zbc_depth_get()
169 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in gf100_fermi_mthd_zbc_color()
193 if (ret >= 0) { in gf100_fermi_mthd_zbc_color()
195 return 0; in gf100_fermi_mthd_zbc_color()
215 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in gf100_fermi_mthd_zbc_depth()
221 return (ret >= 0) ? 0 : -ENOSPC; in gf100_fermi_mthd_zbc_depth()
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
260 switch (class & 0x00ff) { in gf100_gr_mthd_sw()
261 case 0x97: in gf100_gr_mthd_sw()
262 case 0xc0: in gf100_gr_mthd_sw()
264 case 0x1528: in gf100_gr_mthd_sw()
295 return 0; in gf100_gr_object_new()
302 int c = 0; in gf100_gr_object_get()
333 for (i = 0; i < gr->size; i += 4) in gf100_gr_chan_bind()
337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); in gf100_gr_chan_bind()
338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8); in gf100_gr_chan_bind()
340 nvkm_wo32(*pgpuobj, 0xf4, 0); in gf100_gr_chan_bind()
341 nvkm_wo32(*pgpuobj, 0xf8, 0); in gf100_gr_chan_bind()
342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); in gf100_gr_chan_bind()
343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr)); in gf100_gr_chan_bind()
344 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr)); in gf100_gr_chan_bind()
345 nvkm_wo32(*pgpuobj, 0x1c, 1); in gf100_gr_chan_bind()
346 nvkm_wo32(*pgpuobj, 0x20, 0); in gf100_gr_chan_bind()
347 nvkm_wo32(*pgpuobj, 0x28, 0); in gf100_gr_chan_bind()
348 nvkm_wo32(*pgpuobj, 0x2c, 0); in gf100_gr_chan_bind()
351 return 0; in gf100_gr_chan_bind()
360 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { in gf100_gr_chan_dtor()
401 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, in gf100_gr_chan_new()
406 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma); in gf100_gr_chan_new()
410 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm, in gf100_gr_chan_new()
416 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { in gf100_gr_chan_new()
431 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm, in gf100_gr_chan_new()
441 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { in gf100_gr_chan_new()
445 if (mmio->buffer >= 0) { in gf100_gr_chan_new()
455 return 0; in gf100_gr_chan_new()
464 { 0x400080, 1, 0x04, 0x003083c2 },
465 { 0x400088, 1, 0x04, 0x00006fe7 },
466 { 0x40008c, 1, 0x04, 0x00000000 },
467 { 0x400090, 1, 0x04, 0x00000030 },
468 { 0x40013c, 1, 0x04, 0x013901f7 },
469 { 0x400140, 1, 0x04, 0x00000100 },
470 { 0x400144, 1, 0x04, 0x00000000 },
471 { 0x400148, 1, 0x04, 0x00000110 },
472 { 0x400138, 1, 0x04, 0x00000000 },
473 { 0x400130, 2, 0x04, 0x00000000 },
474 { 0x400124, 1, 0x04, 0x00000002 },
480 { 0x40415c, 1, 0x04, 0x00000000 },
481 { 0x404170, 1, 0x04, 0x00000000 },
487 { 0x404488, 2, 0x04, 0x00000000 },
493 { 0x407808, 1, 0x04, 0x00000000 },
499 { 0x406024, 1, 0x04, 0x00000000 },
505 { 0x405844, 1, 0x04, 0x00ffffff },
506 { 0x405850, 1, 0x04, 0x00000000 },
507 { 0x405908, 1, 0x04, 0x00000000 },
513 { 0x40803c, 1, 0x04, 0x00000000 },
519 { 0x4184a0, 1, 0x04, 0x00000000 },
525 { 0x418604, 1, 0x04, 0x00000000 },
526 { 0x418680, 1, 0x04, 0x00000000 },
527 { 0x418714, 1, 0x04, 0x80000000 },
528 { 0x418384, 1, 0x04, 0x00000000 },
534 { 0x418814, 3, 0x04, 0x00000000 },
540 { 0x418b04, 1, 0x04, 0x00000000 },
546 { 0x4188c8, 1, 0x04, 0x80000000 },
547 { 0x4188cc, 1, 0x04, 0x00000000 },
548 { 0x4188d0, 1, 0x04, 0x00010000 },
549 { 0x4188d4, 1, 0x04, 0x00000001 },
555 { 0x418910, 1, 0x04, 0x00010001 },
556 { 0x418914, 1, 0x04, 0x00000301 },
557 { 0x418918, 1, 0x04, 0x00800000 },
558 { 0x418980, 1, 0x04, 0x77777770 },
559 { 0x418984, 3, 0x04, 0x77777777 },
565 { 0x418c04, 1, 0x04, 0x00000000 },
566 { 0x418c88, 1, 0x04, 0x00000000 },
572 { 0x418d00, 1, 0x04, 0x00000000 },
573 { 0x418f08, 1, 0x04, 0x00000000 },
574 { 0x418e00, 1, 0x04, 0x00000050 },
575 { 0x418e08, 1, 0x04, 0x00000000 },
581 { 0x41900c, 1, 0x04, 0x00000000 },
582 { 0x419018, 1, 0x04, 0x00000000 },
588 { 0x419d08, 2, 0x04, 0x00000000 },
589 { 0x419d10, 1, 0x04, 0x00000014 },
595 { 0x419ab0, 1, 0x04, 0x00000000 },
596 { 0x419ab8, 1, 0x04, 0x000000e7 },
597 { 0x419abc, 2, 0x04, 0x00000000 },
603 { 0x41980c, 3, 0x04, 0x00000000 },
604 { 0x419844, 1, 0x04, 0x00000000 },
605 { 0x41984c, 1, 0x04, 0x00005bc5 },
606 { 0x419850, 4, 0x04, 0x00000000 },
612 { 0x419c98, 1, 0x04, 0x00000000 },
613 { 0x419ca8, 1, 0x04, 0x80000000 },
614 { 0x419cb4, 1, 0x04, 0x00000000 },
615 { 0x419cb8, 1, 0x04, 0x00008bf4 },
616 { 0x419cbc, 1, 0x04, 0x28137606 },
617 { 0x419cc0, 2, 0x04, 0x00000000 },
623 { 0x419bd4, 1, 0x04, 0x00800000 },
624 { 0x419bdc, 1, 0x04, 0x00000000 },
630 { 0x419d2c, 1, 0x04, 0x00000000 },
636 { 0x419c0c, 1, 0x04, 0x00000000 },
642 { 0x419e00, 1, 0x04, 0x00000000 },
643 { 0x419ea0, 1, 0x04, 0x00000000 },
644 { 0x419ea4, 1, 0x04, 0x00000100 },
645 { 0x419ea8, 1, 0x04, 0x00001100 },
646 { 0x419eac, 1, 0x04, 0x11100702 },
647 { 0x419eb0, 1, 0x04, 0x00000003 },
648 { 0x419eb4, 4, 0x04, 0x00000000 },
649 { 0x419ec8, 1, 0x04, 0x06060618 },
650 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
651 { 0x419ed4, 1, 0x04, 0x011104f1 },
652 { 0x419edc, 1, 0x04, 0x00000000 },
653 { 0x419f00, 1, 0x04, 0x00000000 },
654 { 0x419f2c, 1, 0x04, 0x00000000 },
660 { 0x40880c, 1, 0x04, 0x00000000 },
661 { 0x408910, 9, 0x04, 0x00000000 },
662 { 0x408950, 1, 0x04, 0x00000000 },
663 { 0x408954, 1, 0x04, 0x0000ffff },
664 { 0x408984, 1, 0x04, 0x00000000 },
665 { 0x408988, 1, 0x04, 0x08040201 },
666 { 0x40898c, 1, 0x04, 0x80402010 },
672 { 0x4040f0, 1, 0x04, 0x00000000 },
678 { 0x419880, 1, 0x04, 0x00000002 },
721 return nvkm_rd32(gr->engine.subdev.device, 0x409b00); in gf100_gr_ctxsw_inst()
729 nvkm_wr32(device, 0x409804, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
730 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
731 nvkm_wr32(device, 0x409500, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
732 nvkm_wr32(device, 0x409504, mthd); in gf100_gr_fecs_ctrl_ctxsw()
734 u32 stat = nvkm_rd32(device, 0x409804); in gf100_gr_fecs_ctrl_ctxsw()
735 if (stat == 0x00000002) in gf100_gr_fecs_ctrl_ctxsw()
737 if (stat == 0x00000001) in gf100_gr_fecs_ctrl_ctxsw()
738 return 0; in gf100_gr_fecs_ctrl_ctxsw()
748 int ret = 0; in gf100_gr_fecs_start_ctxsw()
752 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39))) in gf100_gr_fecs_start_ctxsw()
763 int ret = 0; in gf100_gr_fecs_stop_ctxsw()
767 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38))) in gf100_gr_fecs_stop_ctxsw()
779 nvkm_wr32(device, 0x409840, 0x00000030); in gf100_gr_fecs_bind_pointer()
780 nvkm_wr32(device, 0x409500, inst); in gf100_gr_fecs_bind_pointer()
781 nvkm_wr32(device, 0x409504, 0x00000003); in gf100_gr_fecs_bind_pointer()
783 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_bind_pointer()
784 if (stat & 0x00000020) in gf100_gr_fecs_bind_pointer()
786 if (stat & 0x00000010) in gf100_gr_fecs_bind_pointer()
787 return 0; in gf100_gr_fecs_bind_pointer()
798 nvkm_wr32(device, 0x409810, addr >> 8); in gf100_gr_fecs_set_reglist_virtual_address()
799 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_virtual_address()
800 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_virtual_address()
801 nvkm_wr32(device, 0x409504, 0x00000032); in gf100_gr_fecs_set_reglist_virtual_address()
803 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_virtual_address()
804 return 0; in gf100_gr_fecs_set_reglist_virtual_address()
815 nvkm_wr32(device, 0x409810, inst); in gf100_gr_fecs_set_reglist_bind_instance()
816 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_bind_instance()
817 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_bind_instance()
818 nvkm_wr32(device, 0x409504, 0x00000031); in gf100_gr_fecs_set_reglist_bind_instance()
820 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_bind_instance()
821 return 0; in gf100_gr_fecs_set_reglist_bind_instance()
832 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_reglist_image_size()
833 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_discover_reglist_image_size()
834 nvkm_wr32(device, 0x409504, 0x00000030); in gf100_gr_fecs_discover_reglist_image_size()
836 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_reglist_image_size()
837 return 0; in gf100_gr_fecs_discover_reglist_image_size()
858 ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0); in gf100_gr_fecs_elpg_bind()
862 return gf100_gr_fecs_set_reglist_virtual_address(gr, 0); in gf100_gr_fecs_elpg_bind()
870 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_fecs_discover_pm_image_size()
871 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_pm_image_size()
872 nvkm_wr32(device, 0x409504, 0x00000025); in gf100_gr_fecs_discover_pm_image_size()
874 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_pm_image_size()
875 return 0; in gf100_gr_fecs_discover_pm_image_size()
886 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_fecs_discover_zcull_image_size()
887 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_zcull_image_size()
888 nvkm_wr32(device, 0x409504, 0x00000016); in gf100_gr_fecs_discover_zcull_image_size()
890 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_zcull_image_size()
891 return 0; in gf100_gr_fecs_discover_zcull_image_size()
902 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_fecs_discover_image_size()
903 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_image_size()
904 nvkm_wr32(device, 0x409504, 0x00000010); in gf100_gr_fecs_discover_image_size()
906 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_image_size()
907 return 0; in gf100_gr_fecs_discover_image_size()
918 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_fecs_set_watchdog_timeout()
919 nvkm_wr32(device, 0x409500, timeout); in gf100_gr_fecs_set_watchdog_timeout()
920 nvkm_wr32(device, 0x409504, 0x00000021); in gf100_gr_fecs_set_watchdog_timeout()
928 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); in gf100_gr_chsw_load()
929 if (trace & 0x00000040) in gf100_gr_chsw_load()
932 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); in gf100_gr_chsw_load()
933 if (mthd & 0x00080000) in gf100_gr_chsw_load()
943 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; in gf100_gr_rops()
949 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, in gf100_gr_zbc_init()
950 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; in gf100_gr_zbc_init()
951 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, in gf100_gr_zbc_init()
952 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; in gf100_gr_zbc_init()
953 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, in gf100_gr_zbc_init()
954 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; in gf100_gr_zbc_init()
955 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, in gf100_gr_zbc_init()
956 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; in gf100_gr_zbc_init()
960 if (!gr->zbc_color[0].format) { in gf100_gr_zbc_init()
961 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++; in gf100_gr_zbc_init()
962 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++; in gf100_gr_zbc_init()
963 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++; in gf100_gr_zbc_init()
964 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++; in gf100_gr_zbc_init()
965 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++; in gf100_gr_zbc_init()
966 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++; in gf100_gr_zbc_init()
968 gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++; in gf100_gr_zbc_init()
969 gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++; in gf100_gr_zbc_init()
970 gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++; in gf100_gr_zbc_init()
987 * MC (0x200) register, or GR is not busy and a context switch is not in
1000 * required to make sure FIFO_ENGINE_STATUS (0x2640) is in gf100_gr_wait_idle()
1003 nvkm_rd32(device, 0x400700); in gf100_gr_wait_idle()
1005 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; in gf100_gr_wait_idle()
1006 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; in gf100_gr_wait_idle()
1007 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; in gf100_gr_wait_idle()
1010 return 0; in gf100_gr_wait_idle()
1042 u32 data = 0; in gf100_gr_icmd()
1044 nvkm_wr32(device, 0x400208, 0x80000000); in gf100_gr_icmd()
1051 nvkm_wr32(device, 0x400204, init->data); in gf100_gr_icmd()
1056 nvkm_wr32(device, 0x400200, addr); in gf100_gr_icmd()
1061 if ((addr & 0xffff) == 0xe100) in gf100_gr_icmd()
1064 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) in gf100_gr_icmd()
1071 nvkm_wr32(device, 0x400208, 0x00000000); in gf100_gr_icmd()
1080 u32 data = 0; in gf100_gr_mthd()
1083 u32 ctrl = 0x80000000 | pack->type; in gf100_gr_mthd()
1088 nvkm_wr32(device, 0x40448c, init->data); in gf100_gr_mthd()
1093 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); in gf100_gr_mthd()
1113 { 0x00000001, "INJECTED_BUNDLE_ERROR" },
1114 { 0x00000002, "CLASS_SUBCH_MISMATCH" },
1115 { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
1120 { 0x00000001, "PUSH_TOO_MUCH_DATA" },
1121 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
1126 { 0x00000001, "TEMP_TOO_SMALL" },
1131 { 0x00000001, "INTR" },
1132 { 0x00000002, "LDCONST_OOB" },
1137 { 0x00000001, "TOO_FEW_PARAMS" },
1138 { 0x00000002, "TOO_MANY_PARAMS" },
1139 { 0x00000004, "ILLEGAL_OPCODE" },
1140 { 0x00000008, "DOUBLE_BRANCH" },
1141 { 0x00000010, "WATCHDOG" },
1146 { 0x00000040, "CTA_RESUME" },
1147 { 0x00000080, "CONSTANT_BUFFER_SIZE" },
1148 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
1149 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
1150 { 0x00000800, "WARP_CSTACK_SIZE" },
1151 { 0x00001000, "TOTAL_TEMP_SIZE" },
1152 { 0x00002000, "REGISTER_COUNT" },
1153 { 0x00040000, "TOTAL_THREADS" },
1154 { 0x00100000, "PROGRAM_OFFSET" },
1155 { 0x00200000, "SHARED_MEMORY_SIZE" },
1156 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
1157 { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
1158 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
1159 { 0x04000000, "TOTAL_REGISTER_COUNT" },
1164 { 0x00000002, "RT_PITCH_OVERRUN" },
1165 { 0x00000010, "RT_WIDTH_OVERRUN" },
1166 { 0x00000020, "RT_HEIGHT_OVERRUN" },
1167 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
1168 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
1169 { 0x00000400, "RT_LINEAR_MISMATCH" },
1181 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1182 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1183 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1184 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1186 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); in gf100_gr_trap_gpc_rop()
1190 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, in gf100_gr_trap_gpc_rop()
1191 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); in gf100_gr_trap_gpc_rop()
1192 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1196 { 0x01, "STACK_ERROR" },
1197 { 0x02, "API_STACK_ERROR" },
1198 { 0x03, "RET_EMPTY_STACK_ERROR" },
1199 { 0x04, "PC_WRAP" },
1200 { 0x05, "MISALIGNED_PC" },
1201 { 0x06, "PC_OVERFLOW" },
1202 { 0x07, "MISALIGNED_IMMC_ADDR" },
1203 { 0x08, "MISALIGNED_REG" },
1204 { 0x09, "ILLEGAL_INSTR_ENCODING" },
1205 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
1206 { 0x0b, "ILLEGAL_INSTR_PARAM" },
1207 { 0x0c, "INVALID_CONST_ADDR" },
1208 { 0x0d, "OOR_REG" },
1209 { 0x0e, "OOR_ADDR" },
1210 { 0x0f, "MISALIGNED_ADDR" },
1211 { 0x10, "INVALID_ADDR_SPACE" },
1212 { 0x11, "ILLEGAL_INSTR_PARAM2" },
1213 { 0x12, "INVALID_CONST_ADDR_LDC" },
1214 { 0x13, "GEOMETRY_SM_ERROR" },
1215 { 0x14, "DIVERGENT" },
1216 { 0x15, "WARP_EXIT" },
1221 { 0x00000001, "SM_TO_SM_FAULT" },
1222 { 0x00000002, "L1_ERROR" },
1223 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1224 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1225 { 0x00000010, "BPT_INT" },
1226 { 0x00000020, "BPT_PAUSE" },
1227 { 0x00000040, "SINGLE_STEP_COMPLETE" },
1228 { 0x20000000, "ECC_SEC_ERROR" },
1229 { 0x40000000, "ECC_DED_ERROR" },
1230 { 0x80000000, "TIMEOUT" },
1239 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
1240 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
1245 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); in gf100_gr_trap_mp()
1251 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); in gf100_gr_trap_mp()
1252 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); in gf100_gr_trap_mp()
1260 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); in gf100_gr_trap_tpc()
1262 if (stat & 0x00000001) { in gf100_gr_trap_tpc()
1263 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); in gf100_gr_trap_tpc()
1265 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); in gf100_gr_trap_tpc()
1266 stat &= ~0x00000001; in gf100_gr_trap_tpc()
1269 if (stat & 0x00000002) { in gf100_gr_trap_tpc()
1271 stat &= ~0x00000002; in gf100_gr_trap_tpc()
1274 if (stat & 0x00000004) { in gf100_gr_trap_tpc()
1275 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); in gf100_gr_trap_tpc()
1277 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); in gf100_gr_trap_tpc()
1278 stat &= ~0x00000004; in gf100_gr_trap_tpc()
1281 if (stat & 0x00000008) { in gf100_gr_trap_tpc()
1282 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); in gf100_gr_trap_tpc()
1284 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); in gf100_gr_trap_tpc()
1285 stat &= ~0x00000008; in gf100_gr_trap_tpc()
1288 if (stat & 0x00000010) { in gf100_gr_trap_tpc()
1289 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); in gf100_gr_trap_tpc()
1291 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); in gf100_gr_trap_tpc()
1292 stat &= ~0x00000010; in gf100_gr_trap_tpc()
1305 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); in gf100_gr_trap_gpc()
1308 if (stat & 0x00000001) { in gf100_gr_trap_gpc()
1310 stat &= ~0x00000001; in gf100_gr_trap_gpc()
1313 if (stat & 0x00000002) { in gf100_gr_trap_gpc()
1314 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); in gf100_gr_trap_gpc()
1316 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_trap_gpc()
1317 stat &= ~0x00000002; in gf100_gr_trap_gpc()
1320 if (stat & 0x00000004) { in gf100_gr_trap_gpc()
1321 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); in gf100_gr_trap_gpc()
1323 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_trap_gpc()
1324 stat &= ~0x00000004; in gf100_gr_trap_gpc()
1327 if (stat & 0x00000008) { in gf100_gr_trap_gpc()
1328 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); in gf100_gr_trap_gpc()
1330 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_trap_gpc()
1331 stat &= ~0x00000009; in gf100_gr_trap_gpc()
1334 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_gr_trap_gpc()
1335 u32 mask = 0x00010000 << tpc; in gf100_gr_trap_gpc()
1338 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); in gf100_gr_trap_gpc()
1354 u32 trap = nvkm_rd32(device, 0x400108); in gf100_gr_trap_intr()
1357 if (trap & 0x00000001) { in gf100_gr_trap_intr()
1358 u32 stat = nvkm_rd32(device, 0x404000); in gf100_gr_trap_intr()
1361 stat & 0x3fffffff); in gf100_gr_trap_intr()
1363 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_trap_intr()
1364 nvkm_wr32(device, 0x400108, 0x00000001); in gf100_gr_trap_intr()
1365 trap &= ~0x00000001; in gf100_gr_trap_intr()
1368 if (trap & 0x00000002) { in gf100_gr_trap_intr()
1369 u32 stat = nvkm_rd32(device, 0x404600); in gf100_gr_trap_intr()
1372 stat & 0x3fffffff); in gf100_gr_trap_intr()
1375 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_trap_intr()
1376 nvkm_wr32(device, 0x400108, 0x00000002); in gf100_gr_trap_intr()
1377 trap &= ~0x00000002; in gf100_gr_trap_intr()
1380 if (trap & 0x00000008) { in gf100_gr_trap_intr()
1381 u32 stat = nvkm_rd32(device, 0x408030); in gf100_gr_trap_intr()
1384 stat & 0x3fffffff); in gf100_gr_trap_intr()
1386 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_trap_intr()
1387 nvkm_wr32(device, 0x400108, 0x00000008); in gf100_gr_trap_intr()
1388 trap &= ~0x00000008; in gf100_gr_trap_intr()
1391 if (trap & 0x00000010) { in gf100_gr_trap_intr()
1392 u32 stat = nvkm_rd32(device, 0x405840); in gf100_gr_trap_intr()
1393 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", in gf100_gr_trap_intr()
1394 stat, stat & 0xffffff, (stat >> 24) & 0x3f); in gf100_gr_trap_intr()
1395 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_trap_intr()
1396 nvkm_wr32(device, 0x400108, 0x00000010); in gf100_gr_trap_intr()
1397 trap &= ~0x00000010; in gf100_gr_trap_intr()
1400 if (trap & 0x00000040) { in gf100_gr_trap_intr()
1401 u32 stat = nvkm_rd32(device, 0x40601c); in gf100_gr_trap_intr()
1404 stat & 0x3fffffff); in gf100_gr_trap_intr()
1407 nvkm_wr32(device, 0x40601c, 0xc0000000); in gf100_gr_trap_intr()
1408 nvkm_wr32(device, 0x400108, 0x00000040); in gf100_gr_trap_intr()
1409 trap &= ~0x00000040; in gf100_gr_trap_intr()
1412 if (trap & 0x00000080) { in gf100_gr_trap_intr()
1413 u32 stat = nvkm_rd32(device, 0x404490); in gf100_gr_trap_intr()
1414 u32 pc = nvkm_rd32(device, 0x404494); in gf100_gr_trap_intr()
1415 u32 op = nvkm_rd32(device, 0x40449c); in gf100_gr_trap_intr()
1418 stat & 0x1fffffff); in gf100_gr_trap_intr()
1419 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", in gf100_gr_trap_intr()
1420 stat, error, pc & 0x7ff, in gf100_gr_trap_intr()
1421 (pc & 0x10000000) ? "" : " (invalid)", in gf100_gr_trap_intr()
1424 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_trap_intr()
1425 nvkm_wr32(device, 0x400108, 0x00000080); in gf100_gr_trap_intr()
1426 trap &= ~0x00000080; in gf100_gr_trap_intr()
1429 if (trap & 0x00000100) { in gf100_gr_trap_intr()
1430 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; in gf100_gr_trap_intr()
1436 nvkm_wr32(device, 0x407020, 0x40000000); in gf100_gr_trap_intr()
1437 nvkm_wr32(device, 0x400108, 0x00000100); in gf100_gr_trap_intr()
1438 trap &= ~0x00000100; in gf100_gr_trap_intr()
1441 if (trap & 0x01000000) { in gf100_gr_trap_intr()
1442 u32 stat = nvkm_rd32(device, 0x400118); in gf100_gr_trap_intr()
1443 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { in gf100_gr_trap_intr()
1444 u32 mask = 0x00000001 << gpc; in gf100_gr_trap_intr()
1447 nvkm_wr32(device, 0x400118, mask); in gf100_gr_trap_intr()
1451 nvkm_wr32(device, 0x400108, 0x01000000); in gf100_gr_trap_intr()
1452 trap &= ~0x01000000; in gf100_gr_trap_intr()
1455 if (trap & 0x02000000) { in gf100_gr_trap_intr()
1456 for (rop = 0; rop < gr->rop_nr; rop++) { in gf100_gr_trap_intr()
1457 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); in gf100_gr_trap_intr()
1458 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); in gf100_gr_trap_intr()
1461 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); in gf100_gr_trap_intr()
1462 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); in gf100_gr_trap_intr()
1464 nvkm_wr32(device, 0x400108, 0x02000000); in gf100_gr_trap_intr()
1465 trap &= ~0x02000000; in gf100_gr_trap_intr()
1470 nvkm_wr32(device, 0x400108, trap); in gf100_gr_trap_intr()
1480 nvkm_rd32(device, base + 0x400)); in gf100_gr_ctxctl_debug_unit()
1482 nvkm_rd32(device, base + 0x800), in gf100_gr_ctxctl_debug_unit()
1483 nvkm_rd32(device, base + 0x804), in gf100_gr_ctxctl_debug_unit()
1484 nvkm_rd32(device, base + 0x808), in gf100_gr_ctxctl_debug_unit()
1485 nvkm_rd32(device, base + 0x80c)); in gf100_gr_ctxctl_debug_unit()
1487 nvkm_rd32(device, base + 0x810), in gf100_gr_ctxctl_debug_unit()
1488 nvkm_rd32(device, base + 0x814), in gf100_gr_ctxctl_debug_unit()
1489 nvkm_rd32(device, base + 0x818), in gf100_gr_ctxctl_debug_unit()
1490 nvkm_rd32(device, base + 0x81c)); in gf100_gr_ctxctl_debug_unit()
1497 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; in gf100_gr_ctxctl_debug()
1500 gf100_gr_ctxctl_debug_unit(gr, 0x409000); in gf100_gr_ctxctl_debug()
1501 for (gpc = 0; gpc < gpcnr; gpc++) in gf100_gr_ctxctl_debug()
1502 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); in gf100_gr_ctxctl_debug()
1510 u32 stat = nvkm_rd32(device, 0x409c18); in gf100_gr_ctxctl_isr()
1512 if (!gr->firmware && (stat & 0x00000001)) { in gf100_gr_ctxctl_isr()
1513 u32 code = nvkm_rd32(device, 0x409814); in gf100_gr_ctxctl_isr()
1515 u32 class = nvkm_rd32(device, 0x409808); in gf100_gr_ctxctl_isr()
1516 u32 addr = nvkm_rd32(device, 0x40980c); in gf100_gr_ctxctl_isr()
1517 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_ctxctl_isr()
1518 u32 mthd = (addr & 0x00003ffc); in gf100_gr_ctxctl_isr()
1519 u32 data = nvkm_rd32(device, 0x409810); in gf100_gr_ctxctl_isr()
1527 nvkm_wr32(device, 0x409c20, 0x00000001); in gf100_gr_ctxctl_isr()
1528 stat &= ~0x00000001; in gf100_gr_ctxctl_isr()
1531 if (!gr->firmware && (stat & 0x00080000)) { in gf100_gr_ctxctl_isr()
1534 nvkm_wr32(device, 0x409c20, 0x00080000); in gf100_gr_ctxctl_isr()
1535 stat &= ~0x00080000; in gf100_gr_ctxctl_isr()
1541 nvkm_wr32(device, 0x409c20, stat); in gf100_gr_ctxctl_isr()
1553 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; in gf100_gr_intr()
1554 u32 stat = nvkm_rd32(device, 0x400100); in gf100_gr_intr()
1555 u32 addr = nvkm_rd32(device, 0x400704); in gf100_gr_intr()
1556 u32 mthd = (addr & 0x00003ffc); in gf100_gr_intr()
1557 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_intr()
1558 u32 data = nvkm_rd32(device, 0x400708); in gf100_gr_intr()
1559 u32 code = nvkm_rd32(device, 0x400110); in gf100_gr_intr()
1571 class = nvkm_rd32(device, 0x404200 + (subc * 4)); in gf100_gr_intr()
1573 class = 0x0000; in gf100_gr_intr()
1575 if (stat & 0x00000001) { in gf100_gr_intr()
1580 nvkm_wr32(device, 0x400100, 0x00000001); in gf100_gr_intr()
1581 stat &= ~0x00000001; in gf100_gr_intr()
1584 if (stat & 0x00000010) { in gf100_gr_intr()
1591 nvkm_wr32(device, 0x400100, 0x00000010); in gf100_gr_intr()
1592 stat &= ~0x00000010; in gf100_gr_intr()
1595 if (stat & 0x00000020) { in gf100_gr_intr()
1599 nvkm_wr32(device, 0x400100, 0x00000020); in gf100_gr_intr()
1600 stat &= ~0x00000020; in gf100_gr_intr()
1603 if (stat & 0x00100000) { in gf100_gr_intr()
1610 nvkm_wr32(device, 0x400100, 0x00100000); in gf100_gr_intr()
1611 stat &= ~0x00100000; in gf100_gr_intr()
1614 if (stat & 0x00200000) { in gf100_gr_intr()
1618 nvkm_wr32(device, 0x400100, 0x00200000); in gf100_gr_intr()
1619 stat &= ~0x00200000; in gf100_gr_intr()
1622 if (stat & 0x00080000) { in gf100_gr_intr()
1624 nvkm_wr32(device, 0x400100, 0x00080000); in gf100_gr_intr()
1625 stat &= ~0x00080000; in gf100_gr_intr()
1630 nvkm_wr32(device, 0x400100, stat); in gf100_gr_intr()
1633 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_intr()
1641 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); in gf100_gr_init_fw()
1642 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); in gf100_gr_init_fw()
1653 u32 addr = ~0, prev = ~0, xfer = 0; in gf100_gr_init_csdata()
1656 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); in gf100_gr_init_csdata()
1657 star = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1658 temp = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1661 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); in gf100_gr_init_csdata()
1670 nvkm_wr32(device, falcon + 0x01c4, data); in gf100_gr_init_csdata()
1674 xfer = 0; in gf100_gr_init_csdata()
1682 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); in gf100_gr_init_csdata()
1683 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); in gf100_gr_init_csdata()
1684 nvkm_wr32(device, falcon + 0x01c4, star + 4); in gf100_gr_init_csdata()
1693 u32 lsf_mask = 0; in gf100_gr_init_ctxctl_ext()
1697 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_ext()
1724 nvkm_wr32(device, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl_ext()
1725 nvkm_wr32(device, 0x41a10c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1726 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1732 if (nvkm_rd32(device, 0x409800) & 0x00000001) in gf100_gr_init_ctxctl_ext()
1734 ) < 0) in gf100_gr_init_ctxctl_ext()
1737 gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff); in gf100_gr_init_ctxctl_ext()
1760 if (0) { in gf100_gr_init_ctxctl_ext()
1775 return 0; in gf100_gr_init_ctxctl_ext()
1790 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_int()
1792 gr->func->fecs.ucode->data.data, 0x0, in gf100_gr_init_ctxctl_int()
1793 gr->func->fecs.ucode->data.size, 0); in gf100_gr_init_ctxctl_int()
1795 gr->func->fecs.ucode->code.data, 0x0, in gf100_gr_init_ctxctl_int()
1796 gr->func->fecs.ucode->code.size, 0, 0, false); in gf100_gr_init_ctxctl_int()
1800 gr->func->gpccs.ucode->data.data, 0x0, in gf100_gr_init_ctxctl_int()
1801 gr->func->gpccs.ucode->data.size, 0); in gf100_gr_init_ctxctl_int()
1803 gr->func->gpccs.ucode->code.data, 0x0, in gf100_gr_init_ctxctl_int()
1804 gr->func->gpccs.ucode->code.size, 0, 0, false); in gf100_gr_init_ctxctl_int()
1808 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); in gf100_gr_init_ctxctl_int()
1809 gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000); in gf100_gr_init_ctxctl_int()
1810 gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000); in gf100_gr_init_ctxctl_int()
1811 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); in gf100_gr_init_ctxctl_int()
1812 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); in gf100_gr_init_ctxctl_int()
1815 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_int()
1816 nvkm_wr32(device, 0x409100, 0x00000002); in gf100_gr_init_ctxctl_int()
1818 if (nvkm_rd32(device, 0x409800) & 0x80000000) in gf100_gr_init_ctxctl_int()
1820 ) < 0) { in gf100_gr_init_ctxctl_int()
1825 gr->size = nvkm_rd32(device, 0x409804); in gf100_gr_init_ctxctl_int()
1834 return 0; in gf100_gr_init_ctxctl_int()
1854 for (tpc = 0; tpc < gr->tpc_max; tpc++) { in gf100_gr_oneinit_sm_id()
1855 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_oneinit_sm_id()
1877 case 15: gr->screen_tile_row_offset = 0x06; break; in gf100_gr_oneinit_tiles()
1878 case 14: gr->screen_tile_row_offset = 0x05; break; in gf100_gr_oneinit_tiles()
1879 case 13: gr->screen_tile_row_offset = 0x02; break; in gf100_gr_oneinit_tiles()
1880 case 11: gr->screen_tile_row_offset = 0x07; break; in gf100_gr_oneinit_tiles()
1881 case 10: gr->screen_tile_row_offset = 0x06; break; in gf100_gr_oneinit_tiles()
1883 case 5: gr->screen_tile_row_offset = 0x01; break; in gf100_gr_oneinit_tiles()
1884 case 3: gr->screen_tile_row_offset = 0x02; break; in gf100_gr_oneinit_tiles()
1886 case 1: gr->screen_tile_row_offset = 0x01; break; in gf100_gr_oneinit_tiles()
1887 default: gr->screen_tile_row_offset = 0x03; in gf100_gr_oneinit_tiles()
1888 for (i = 0; i < ARRAY_SIZE(primes); i++) { in gf100_gr_oneinit_tiles()
1898 for (i = 0; i < gr->gpc_nr; i++) in gf100_gr_oneinit_tiles()
1903 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) { in gf100_gr_oneinit_tiles()
1905 gr->tpc_nr[gpc_map[i + 0]]) { in gf100_gr_oneinit_tiles()
1907 gpc_map[i + 0] = gpc_map[i + 1]; in gf100_gr_oneinit_tiles()
1923 for (i = 0; i < gr->gpc_nr; i++) { in gf100_gr_oneinit_tiles()
1929 for (i = 0; i < gr->tpc_total;) { in gf100_gr_oneinit_tiles()
1930 for (j = 0; j < gr->gpc_nr; j++) { in gf100_gr_oneinit_tiles()
1952 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; in gf100_gr_oneinit()
1953 for (i = 0; i < gr->gpc_nr; i++) { in gf100_gr_oneinit()
1954 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); in gf100_gr_oneinit()
1958 for (j = 0; j < gr->ppc_nr[i]; j++) { in gf100_gr_oneinit()
1960 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); in gf100_gr_oneinit()
1961 if (gr->ppc_tpc_mask[i][j] == 0) in gf100_gr_oneinit()
1965 if (gr->ppc_tpc_min == 0 || in gf100_gr_oneinit()
1973 memset(gr->tile, 0xff, sizeof(gr->tile)); in gf100_gr_oneinit()
1976 return 0; in gf100_gr_oneinit()
1985 bool reset = device->chipset == 0x137 || device->chipset == 0x138; in gf100_gr_init_()
2005 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gf100_gr_init_()
2006 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2008 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000); in gf100_gr_init_()
2009 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2032 return 0; in gf100_gr_fini()
2076 .fbif = 0x600,
2111 "fecs", 0x409000, &gr->fecs.falcon); in gf100_gr_new_()
2118 "gpccs", 0x41a000, &gr->gpccs.falcon); in gf100_gr_new_()
2122 return 0; in gf100_gr_new_()
2132 for (gpc = 0, i = 0; i < 4; i++) { in gf100_gr_init_num_tpc_per_gpc()
2133 for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) in gf100_gr_init_num_tpc_per_gpc()
2136 nvkm_wr32(device, 0x406028 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2138 nvkm_wr32(device, 0x405870 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2145 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); in gf100_gr_init_400054()
2152 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); in gf100_gr_init_shader_exceptions()
2153 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); in gf100_gr_init_shader_exceptions()
2160 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); in gf100_gr_init_tex_hww_esr()
2167 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init_419eb4()
2176 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init_419cc0()
2178 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_419cc0()
2179 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) in gf100_gr_init_419cc0()
2180 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); in gf100_gr_init_419cc0()
2187 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); in gf100_gr_init_40601c()
2193 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001; in gf100_gr_init_fecs_exceptions()
2194 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); in gf100_gr_init_fecs_exceptions()
2203 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); in gf100_gr_init_gpc_mmu()
2204 nvkm_wr32(device, 0x4188a4, 0x03000000); in gf100_gr_init_gpc_mmu()
2205 nvkm_wr32(device, 0x418888, 0x00000000); in gf100_gr_init_gpc_mmu()
2206 nvkm_wr32(device, 0x41888c, 0x00000000); in gf100_gr_init_gpc_mmu()
2207 nvkm_wr32(device, 0x418890, 0x00000000); in gf100_gr_init_gpc_mmu()
2208 nvkm_wr32(device, 0x418894, 0x00000000); in gf100_gr_init_gpc_mmu()
2209 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8); in gf100_gr_init_gpc_mmu()
2210 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8); in gf100_gr_init_gpc_mmu()
2217 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); in gf100_gr_init_num_active_ltcs()
2224 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init_zcull()
2229 for (i = 0; i < tile_nr; i += 8) { in gf100_gr_init_zcull()
2230 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf100_gr_init_zcull()
2234 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); in gf100_gr_init_zcull()
2237 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_zcull()
2238 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf100_gr_init_zcull()
2240 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf100_gr_init_zcull()
2242 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf100_gr_init_zcull()
2245 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); in gf100_gr_init_zcull()
2252 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); in gf100_gr_init_vsc_stream_master()
2294 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_init()
2296 nvkm_wr32(device, 0x400100, 0xffffffff); in gf100_gr_init()
2297 nvkm_wr32(device, 0x40013c, 0xffffffff); in gf100_gr_init()
2298 nvkm_wr32(device, 0x400124, 0x00000002); in gf100_gr_init()
2304 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_init()
2305 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_init()
2306 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_init()
2311 nvkm_wr32(device, 0x406018, 0xc0000000); in gf100_gr_init()
2312 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_init()
2317 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_init()
2318 nvkm_wr32(device, 0x405844, 0x00ffffff); in gf100_gr_init()
2330 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init()
2331 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_init()
2332 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_init()
2333 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_init()
2334 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_init()
2335 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_gr_init()
2336 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); in gf100_gr_init()
2337 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); in gf100_gr_init()
2340 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); in gf100_gr_init()
2345 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); in gf100_gr_init()
2346 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); in gf100_gr_init()
2349 for (rop = 0; rop < gr->rop_nr; rop++) { in gf100_gr_init()
2350 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); in gf100_gr_init()
2351 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); in gf100_gr_init()
2352 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); in gf100_gr_init()
2353 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); in gf100_gr_init()
2356 nvkm_wr32(device, 0x400108, 0xffffffff); in gf100_gr_init()
2357 nvkm_wr32(device, 0x400138, 0xffffffff); in gf100_gr_init()
2358 nvkm_wr32(device, 0x400118, 0xffffffff); in gf100_gr_init()
2359 nvkm_wr32(device, 0x400130, 0xffffffff); in gf100_gr_init()
2360 nvkm_wr32(device, 0x40011c, 0xffffffff); in gf100_gr_init()
2361 nvkm_wr32(device, 0x400134, 0xffffffff); in gf100_gr_init()
2430 return 0; in gf100_gr_nofw()
2457 return (blob->data != NULL) ? 0 : -ENOMEM; in gf100_gr_load_fw()
2475 return 0; in gf100_gr_load()