42 		return 0;  in gf100_fifo_chan_ntfy()
45 		return 0;  in gf100_fifo_chan_ntfy()
56 	case NVKM_ENGINE_SW    : return 0;  in gf100_fifo_gpfifo_engine_addr()
57 	case NVKM_ENGINE_GR    : return 0x0210;  in gf100_fifo_gpfifo_engine_addr()
58 	case NVKM_ENGINE_CE    : return 0x0230 + (engine->subdev.inst * 0x10);  in gf100_fifo_gpfifo_engine_addr()
59 	case NVKM_ENGINE_MSPDEC: return 0x0250;  in gf100_fifo_gpfifo_engine_addr()
60 	case NVKM_ENGINE_MSPPP : return 0x0260;  in gf100_fifo_gpfifo_engine_addr()
61 	case NVKM_ENGINE_MSVLD : return 0x0270;  in gf100_fifo_gpfifo_engine_addr()
64 		return 0;  in gf100_fifo_gpfifo_engine_addr()
72 	if (engi >= 0)  in gf100_fifo_gpfifo_engine()
86 	int ret = 0;  in gf100_fifo_gpfifo_engine_fini()
89 	nvkm_wr32(device, 0x002634, chan->base.chid);  in gf100_fifo_gpfifo_engine_fini()
91 		if (nvkm_rd32(device, 0x002634) == chan->base.chid)  in gf100_fifo_gpfifo_engine_fini()
93 	) < 0) {  in gf100_fifo_gpfifo_engine_fini()
105 		nvkm_wo32(inst, offset + 0x00, 0x00000000);  in gf100_fifo_gpfifo_engine_fini()
106 		nvkm_wo32(inst, offset + 0x04, 0x00000000);  in gf100_fifo_gpfifo_engine_fini()
124 		nvkm_wo32(inst, offset + 0x00, lower_32_bits(engn->vma->addr) | 4);  in gf100_fifo_gpfifo_engine_init()
125 		nvkm_wo32(inst, offset + 0x04, upper_32_bits(engn->vma->addr));  in gf100_fifo_gpfifo_engine_init()
129 	return 0;  in gf100_fifo_gpfifo_engine_init()
152 		return 0;  in gf100_fifo_gpfifo_engine_ctor()
154 	ret = nvkm_object_bind(object, NULL, 0, &engn->inst);  in gf100_fifo_gpfifo_engine_ctor()
162 	return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0);  in gf100_fifo_gpfifo_engine_ctor()
175 		nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000);  in gf100_fifo_gpfifo_fini()
181 	nvkm_wr32(device, 0x003000 + coff, 0x00000000);  in gf100_fifo_gpfifo_fini()
193 	nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr);  in gf100_fifo_gpfifo_init()
197 		nvkm_wr32(device, 0x003004 + coff, 0x001f0001);  in gf100_fifo_gpfifo_init()
234 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {  in gf100_fifo_gpfifo_new()
252 				  0x1000, 0x1000, true, args->v0.vmm, 0,  in gf100_fifo_gpfifo_new()
260 				  1, fifo->user.bar->addr, 0x1000,  in gf100_fifo_gpfifo_new()
269 	usermem = chan->base.chid * 0x1000;  in gf100_fifo_gpfifo_new()
274 	for (i = 0; i < 0x1000; i += 4)  in gf100_fifo_gpfifo_new()
275 		nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);  in gf100_fifo_gpfifo_new()
281 	nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));  in gf100_fifo_gpfifo_new()
282 	nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));  in gf100_fifo_gpfifo_new()
283 	nvkm_wo32(chan->base.inst, 0x10, 0x0000face);  in gf100_fifo_gpfifo_new()
284 	nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);  in gf100_fifo_gpfifo_new()
285 	nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));  in gf100_fifo_gpfifo_new()
286 	nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |  in gf100_fifo_gpfifo_new()
288 	nvkm_wo32(chan->base.inst, 0x54, 0x00000002);  in gf100_fifo_gpfifo_new()
289 	nvkm_wo32(chan->base.inst, 0x84, 0x20400000);  in gf100_fifo_gpfifo_new()
290 	nvkm_wo32(chan->base.inst, 0x94, 0x30000001);  in gf100_fifo_gpfifo_new()
291 	nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);  in gf100_fifo_gpfifo_new()
292 	nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f);  in gf100_fifo_gpfifo_new()
293 	nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f);  in gf100_fifo_gpfifo_new()
294 	nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);  in gf100_fifo_gpfifo_new()
295 	nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);  in gf100_fifo_gpfifo_new()
296 	nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */  in gf100_fifo_gpfifo_new()
297 	nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */  in gf100_fifo_gpfifo_new()
299 	return 0;  in gf100_fifo_gpfifo_new()
305 	.base.minver = 0,
306 	.base.maxver = 0,