Lines Matching +full:0 +full:x00000010
58 NON_BURST_SYNCH_PULSE = 0,
64 VID_DST_FORMAT_RGB565 = 0,
71 SWAP_RGB = 0,
80 TRIGGER_NONE = 0,
89 CMD_DST_FORMAT_RGB111 = 0,
98 LANE_SWAP_0123 = 0,
109 VIDEO_CONFIG_18BPP = 0,
114 VID_PRBS = 0,
121 CMD_MDP_PRBS = 0,
128 CMD_DMA_PRBS = 0,
134 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
135 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
136 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
137 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
138 #define DSI_IRQ_VIDEO_DONE 0x00010000
139 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
140 #define DSI_IRQ_BTA_DONE 0x00100000
141 #define DSI_IRQ_MASK_BTA_DONE 0x00200000
142 #define DSI_IRQ_ERROR 0x01000000
143 #define DSI_IRQ_MASK_ERROR 0x02000000
144 #define REG_DSI_6G_HW_VERSION 0x00000000
145 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
151 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
157 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
158 #define DSI_6G_HW_VERSION_STEP__SHIFT 0
164 #define REG_DSI_CTRL 0x00000000
165 #define DSI_CTRL_ENABLE 0x00000001
166 #define DSI_CTRL_VID_MODE_EN 0x00000002
167 #define DSI_CTRL_CMD_MODE_EN 0x00000004
168 #define DSI_CTRL_LANE0 0x00000010
169 #define DSI_CTRL_LANE1 0x00000020
170 #define DSI_CTRL_LANE2 0x00000040
171 #define DSI_CTRL_LANE3 0x00000080
172 #define DSI_CTRL_CLK_EN 0x00000100
173 #define DSI_CTRL_ECC_CHECK 0x00100000
174 #define DSI_CTRL_CRC_CHECK 0x01000000
176 #define REG_DSI_STATUS0 0x00000004
177 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
178 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
179 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
180 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
181 #define DSI_STATUS0_DSI_BUSY 0x00000010
182 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
184 #define REG_DSI_FIFO_STATUS 0x00000008
185 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
186 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
187 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
188 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
189 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
190 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
191 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
192 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
193 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
194 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
195 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
196 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
197 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
198 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
199 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
200 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
201 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
202 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
203 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
204 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
205 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
206 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
207 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
208 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
209 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
211 #define REG_DSI_VID_CFG0 0x0000000c
212 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
213 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
218 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
224 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
230 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
231 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
232 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
233 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
234 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
235 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
237 #define REG_DSI_VID_CFG1 0x0000001c
238 #define DSI_VID_CFG1_R_SEL 0x00000001
239 #define DSI_VID_CFG1_G_SEL 0x00000010
240 #define DSI_VID_CFG1_B_SEL 0x00000100
241 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
248 #define REG_DSI_ACTIVE_H 0x00000020
249 #define DSI_ACTIVE_H_START__MASK 0x00000fff
250 #define DSI_ACTIVE_H_START__SHIFT 0
255 #define DSI_ACTIVE_H_END__MASK 0x0fff0000
262 #define REG_DSI_ACTIVE_V 0x00000024
263 #define DSI_ACTIVE_V_START__MASK 0x00000fff
264 #define DSI_ACTIVE_V_START__SHIFT 0
269 #define DSI_ACTIVE_V_END__MASK 0x0fff0000
276 #define REG_DSI_TOTAL 0x00000028
277 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
278 #define DSI_TOTAL_H_TOTAL__SHIFT 0
283 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
290 #define REG_DSI_ACTIVE_HSYNC 0x0000002c
291 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
292 #define DSI_ACTIVE_HSYNC_START__SHIFT 0
297 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
304 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
305 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
306 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
311 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
318 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
319 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
320 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
325 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
332 #define REG_DSI_CMD_DMA_CTRL 0x00000038
333 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
334 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
335 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
337 #define REG_DSI_CMD_CFG0 0x0000003c
338 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
339 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
344 #define DSI_CMD_CFG0_R_SEL 0x00000010
345 #define DSI_CMD_CFG0_G_SEL 0x00000100
346 #define DSI_CMD_CFG0_B_SEL 0x00001000
347 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
353 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
360 #define REG_DSI_CMD_CFG1 0x00000040
361 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
362 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
367 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
373 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
375 #define REG_DSI_DMA_BASE 0x00000044
377 #define REG_DSI_DMA_LEN 0x00000048
379 #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
380 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
381 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
386 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
392 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
399 #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
400 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
401 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
406 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
413 #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
414 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
415 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
420 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
426 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
433 #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
434 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
435 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
440 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
447 #define REG_DSI_ACK_ERR_STATUS 0x00000064
449 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK()
451 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA()
453 #define REG_DSI_TRIG_CTRL 0x00000080
454 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
455 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
460 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
466 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
472 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
473 #define DSI_TRIG_CTRL_TE 0x80000000
475 #define REG_DSI_TRIG_DMA 0x0000008c
477 #define REG_DSI_DLN0_PHY_ERR 0x000000b0
478 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
479 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
480 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
481 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
482 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
484 #define REG_DSI_LP_TIMER_CTRL 0x000000b4
485 #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
486 #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
491 #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
498 #define REG_DSI_HS_TIMER_CTRL 0x000000b8
499 #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
500 #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
505 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
511 #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
513 #define REG_DSI_TIMEOUT_STATUS 0x000000bc
515 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
516 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
517 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
522 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
529 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8
530 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
531 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
533 #define REG_DSI_LANE_STATUS 0x000000a4
534 #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
535 #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
536 #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
537 #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
538 #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
539 #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
540 #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
541 #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
542 #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
543 #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
544 #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
546 #define REG_DSI_LANE_CTRL 0x000000a8
547 #define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000
548 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
550 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
551 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
552 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
558 #define REG_DSI_ERR_INT_MASK0 0x00000108
560 #define REG_DSI_INTR_CTRL 0x0000010c
562 #define REG_DSI_RESET 0x00000114
564 #define REG_DSI_CLK_CTRL 0x00000118
565 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
566 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
567 #define DSI_CLK_CTRL_PCLK_ON 0x00000004
568 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008
569 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
570 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
571 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
573 #define REG_DSI_CLK_STATUS 0x0000011c
574 #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
575 #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
576 #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
577 #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
578 #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
579 #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
580 #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
581 #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
582 #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
583 #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
584 #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
585 #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
586 #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
587 #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
588 #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
589 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
591 #define REG_DSI_PHY_RESET 0x00000128
592 #define DSI_PHY_RESET_RESET 0x00000001
594 #define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160
596 #define REG_DSI_TPG_MAIN_CONTROL 0x00000198
597 #define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100
599 #define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0
600 #define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003
601 #define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0
606 #define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004
608 #define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158
609 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000
615 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300
621 #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030
627 #define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004
628 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002
629 #define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001
631 #define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168
633 #define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180
634 #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001
636 #define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
637 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080
638 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000
639 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000
641 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
642 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
644 #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
645 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
646 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
651 #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
652 #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
653 #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
654 #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
655 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
661 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
667 #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
669 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
670 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
671 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
676 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
682 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
689 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
690 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
696 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001
698 #define REG_DSI_VERSION 0x000001f0
699 #define DSI_VERSION_MAJOR__MASK 0xff000000
706 #define REG_DSI_CPHY_MODE_CTRL 0x000002d4