192 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)  in MDSS_HW_VERSION_STEP()
198 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)  in MDSS_HW_VERSION_MINOR()
204 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)  in MDSS_HW_VERSION_MAJOR()
219 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)  in MDP5_HW_VERSION_STEP()
225 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)  in MDP5_HW_VERSION_MINOR()
231 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)  in MDP5_HW_VERSION_MAJOR()
239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF0()
245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF1()
251 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF2()
257 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF3()
277 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W()
279 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W_REG()
282 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT0()
288 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT1()
294 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT2()
299 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R()
301 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R_REG()
304 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT0()
310 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT1()
316 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT2()
321 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)  in __offset_IGC()
331 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }  in REG_MDP5_IGC()
333 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_IGC_LUT()
335 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000…  in REG_MDP5_IGC_LUT_REG()
338 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)  in MDP5_IGC_LUT_REG_VAL()
361 static inline uint32_t __offset_CTL(uint32_t idx)  in __offset_CTL()
372 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }  in REG_MDP5_CTL()
374 static inline uint32_t __offset_LAYER(uint32_t idx)  in __offset_LAYER()
386 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_…  in REG_MDP5_CTL_LAYER()
388 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_REG()
391 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG0()
397 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG1()
403 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG2()
409 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB0()
415 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB1()
421 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB2()
427 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)  in MDP5_CTL_LAYER_REG_DMA0()
433 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)  in MDP5_CTL_LAYER_REG_DMA1()
441 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG3()
447 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB3()
452 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }  in REG_MDP5_CTL_OP()
455 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)  in MDP5_CTL_OP_MODE()
461 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)  in MDP5_CTL_OP_INTF_NUM()
469 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)  in MDP5_CTL_OP_PACK_3D()
474 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }  in REG_MDP5_CTL_FLUSH()
505 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }  in REG_MDP5_CTL_START()
507 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }  in REG_MDP5_CTL_PACK_3D()
509 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)  in __offset_LAYER_EXT()
521 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_EXT()
523 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_CTL_LAYER_EXT_REG()
536 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR0()
542 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR1()
547 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)  in __offset_PIPE()
566 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
568 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
571 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT()
577 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT()
583 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
585 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
587 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
589 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
592 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11()
598 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12()
603 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
606 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13()
612 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21()
617 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
620 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22()
626 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23()
631 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
634 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31()
640 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32()
645 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
648 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33()
653 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
655 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
658 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH()
664 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW()
669 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
671 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
674 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH()
680 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW()
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
687 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
690 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE()
695 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
697 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
700 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE()
705 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
708 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_SIZE_HEIGHT()
714 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_SIZE_WIDTH()
719 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
722 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_HEIGHT()
728 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_WIDTH()
733 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
736 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)  in MDP5_PIPE_SRC_XY_Y()
742 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)  in MDP5_PIPE_SRC_XY_X()
747 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
750 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_OUT_SIZE_HEIGHT()
756 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_OUT_SIZE_WIDTH()
761 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
764 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)  in MDP5_PIPE_OUT_XY_Y()
770 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)  in MDP5_PIPE_OUT_XY_X()
775 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
777 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
779 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
781 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
783 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
786 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P0()
792 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P1()
797 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
800 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P2()
806 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P3()
811 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
813 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
816 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_G_BPC()
822 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_B_BPC()
828 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_R_BPC()
834 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP5_PIPE_SRC_FORMAT_A_BPC()
841 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_CPP()
848 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT()
856 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)  in MDP5_PIPE_SRC_FORMAT_FETCH_TYPE()
862 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP()
867 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
870 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM0()
876 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM1()
882 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM2()
888 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM3()
893 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
897 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)  in MDP5_PIPE_SRC_OP_MODE_BWC()
910 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
912 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
914 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
916 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
918 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
920 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
922 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
924 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
926 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
928 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
930 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
932 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
935 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)  in MDP5_PIPE_DECIMATION_VERT()
941 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)  in MDP5_PIPE_DECIMATION_HORZ()
946 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)  in __offset_SW_PIX_EXT()
955 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { re…  in REG_MDP5_PIPE_SW_PIX_EXT()
957 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
960 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT()
966 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF()
972 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT()
978 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF()
983 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
986 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT()
992 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF()
998 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT()
1004 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF()
1009 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_ty…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1012 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT()
1018 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM()
1023 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1028 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0()
1034 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0()
1040 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2()
1046 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2()
1052 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3()
1058 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3()
1063 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1065 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1067 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1069 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1071 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1073 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
1075 static inline uint32_t __offset_LM(uint32_t idx)  in __offset_LM()
1087 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }  in REG_MDP5_LM()
1089 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i…  in REG_MDP5_LM_BLEND_COLOR_OUT()
1099 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }  in REG_MDP5_LM_OUT_SIZE()
1102 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_LM_OUT_SIZE_HEIGHT()
1108 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_LM_OUT_SIZE_WIDTH()
1113 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_0()
1115 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_1()
1117 static inline uint32_t __offset_BLEND(uint32_t idx)  in __offset_BLEND()
1130 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L…  in REG_MDP5_LM_BLEND()
1132 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __…  in REG_MDP5_LM_BLEND_OP_MODE()
1135 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_FG_ALPHA()
1145 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_BG_ALPHA()
1154 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + _…  in REG_MDP5_LM_BLEND_FG_ALPHA()
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + _…  in REG_MDP5_LM_BLEND_BG_ALPHA()
1158 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
1160 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
1162 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
1164 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
1166 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
1168 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
1170 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
1172 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
1174 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_IMG_SIZE()
1177 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_W()
1183 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_H()
1188 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_SIZE()
1191 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_W()
1197 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_H()
1202 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_XY()
1205 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_X()
1211 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_Y()
1216 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_STRIDE()
1219 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)  in MDP5_LM_CURSOR_STRIDE_STRIDE()
1224 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_FORMAT()
1227 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)  in MDP5_LM_CURSOR_FORMAT_FORMAT()
1232 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(…  in REG_MDP5_LM_CURSOR_BASE_ADDR()
1234 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_START_XY()
1237 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_X_START()
1243 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_Y_START()
1248 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_…  in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
1252 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)  in MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL()
1258 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L…  in REG_MDP5_LM_CURSOR_BLEND_PARAM()
1260 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
1262 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
1264 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
1266 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
1268 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }  in REG_MDP5_LM_GC_LUT_BASE()
1270 static inline uint32_t __offset_DSPP(uint32_t idx)  in __offset_DSPP()
1280 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP()
1282 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_OP_MODE()
1286 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)  in MDP5_DSPP_OP_MODE_IGC_TBL_IDX()
1299 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);…  in REG_MDP5_DSPP_PCC_BASE()
1301 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(…  in REG_MDP5_DSPP_DITHER_DEPTH()
1303 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_CTL_BASE()
1305 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_BASE()
1307 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_SWAP()
1309 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_PA_BASE()
1311 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0…  in REG_MDP5_DSPP_GAMUT_BASE()
1313 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_GC_BASE()
1315 static inline uint32_t __offset_PP(uint32_t idx)  in __offset_PP()
1325 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }  in REG_MDP5_PP()
1327 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)…  in REG_MDP5_PP_TEAR_CHECK_EN()
1329 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP…  in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1332 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)  in MDP5_PP_SYNC_CONFIG_VSYNC_COUNT()
1339 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_P…  in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1341 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);…  in REG_MDP5_PP_SYNC_WRCOUNT()
1344 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_LINE_COUNT()
1350 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT()
1355 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0…  in REG_MDP5_PP_VSYNC_INIT_VAL()
1357 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)…  in REG_MDP5_PP_INT_COUNT_VAL()
1360 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_LINE_COUNT()
1366 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_FRAME_COUNT()
1371 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }  in REG_MDP5_PP_SYNC_THRESH()
1374 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)  in MDP5_PP_SYNC_THRESH_START()
1380 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)  in MDP5_PP_SYNC_THRESH_CONTINUE()
1385 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }  in REG_MDP5_PP_START_POS()
1387 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }  in REG_MDP5_PP_RD_PTR_IRQ()
1389 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }  in REG_MDP5_PP_WR_PTR_IRQ()
1391 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0…  in REG_MDP5_PP_OUT_LINE_COUNT()
1393 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)…  in REG_MDP5_PP_PP_LINE_COUNT()
1395 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PP_AUTOREFRESH_CONFIG()
1397 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }  in REG_MDP5_PP_FBC_MODE()
1399 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0…  in REG_MDP5_PP_FBC_BUDGET_CTL()
1401 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0…  in REG_MDP5_PP_FBC_LOSSY_MODE()
1403 static inline uint32_t __offset_WB(uint32_t idx)  in __offset_WB()
1416 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB()
1418 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB_DST_FORMAT()
1421 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC0_OUT()
1427 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC1_OUT()
1433 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC2_OUT()
1439 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC3_OUT()
1446 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_BPP()
1452 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)  in MDP5_WB_DST_FORMAT_PACK_COUNT()
1461 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)  in MDP5_WB_DST_FORMAT_WRITE_PLANES()
1468 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP()
1474 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_CHROMA_SITE()
1480 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)  in MDP5_WB_DST_FORMAT_FRAME_FORMAT()
1485 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }  in REG_MDP5_WB_DST_OP_MODE()
1489 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)  in MDP5_WB_DST_OP_MODE_BWC_ENC_OP()
1495 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)  in MDP5_WB_DST_OP_MODE_BLOCK_SIZE()
1501 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)  in MDP5_WB_DST_OP_MODE_ROT_MODE()
1509 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT()
1515 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT()
1522 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT()
1528 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD()
1534 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD()
1539 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(…  in REG_MDP5_WB_DST_PACK_PATTERN()
1542 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT0()
1548 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT1()
1554 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT2()
1560 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT3()
1565 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }  in REG_MDP5_WB_DST0_ADDR()
1567 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }  in REG_MDP5_WB_DST1_ADDR()
1569 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }  in REG_MDP5_WB_DST2_ADDR()
1571 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }  in REG_MDP5_WB_DST3_ADDR()
1573 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE0()
1576 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE()
1582 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE()
1587 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE1()
1590 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE()
1596 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE()
1601 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_…  in REG_MDP5_WB_DST_DITHER_BITDEPTH()
1603 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW0()
1605 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW1()
1607 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW2()
1609 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW3()
1611 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(…  in REG_MDP5_WB_DST_WRITE_CONFIG()
1613 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB…  in REG_MDP5_WB_ROTATION_DNSCALER()
1615 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_0_3()
1617 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_1_2()
1619 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3()
1621 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2()
1623 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }  in REG_MDP5_WB_OUT_SIZE()
1626 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)  in MDP5_WB_OUT_SIZE_DST_W()
1632 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)  in MDP5_WB_OUT_SIZE_DST_H()
1637 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)…  in REG_MDP5_WB_ALPHA_X_VALUE()
1639 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_0()
1642 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11()
1648 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12()
1653 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_1()
1656 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13()
1662 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21()
1667 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_2()
1670 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22()
1676 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23()
1681 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_3()
1684 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31()
1690 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32()
1695 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_4()
1698 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33()
1703 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 …  in REG_MDP5_WB_CSC_COMP_PRECLAMP()
1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG()
1708 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)  in MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH()
1714 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)  in MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW()
1719 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP()
1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x0000…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG()
1724 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)  in MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH()
1730 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)  in MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW()
1735 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c +…  in REG_MDP5_WB_CSC_COMP_PREBIAS()
1737 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x000002…  in REG_MDP5_WB_CSC_COMP_PREBIAS_REG()
1740 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)  in MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE()
1745 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 …  in REG_MDP5_WB_CSC_COMP_POSTBIAS()
1747 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG()
1750 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)  in MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE()
1755 static inline uint32_t __offset_INTF(uint32_t idx)  in __offset_INTF()
1766 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }  in REG_MDP5_INTF()
1768 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I…  in REG_MDP5_INTF_TIMING_ENGINE_EN()
1770 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }  in REG_MDP5_INTF_CONFIG()
1772 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)…  in REG_MDP5_INTF_HSYNC_CTL()
1775 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PULSEW()
1781 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PERIOD()
1786 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1788 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1790 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F0()
1792 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F1()
1794 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F0()
1796 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F1()
1798 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F0()
1800 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F1()
1802 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F0()
1805 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F0_VAL()
1811 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F1()
1814 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F1_VAL()
1819 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F0()
1821 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F1()
1823 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(…  in REG_MDP5_INTF_DISPLAY_HCTL()
1826 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_START()
1832 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_END()
1837 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i…  in REG_MDP5_INTF_ACTIVE_HCTL()
1840 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_START()
1846 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_END()
1852 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(…  in REG_MDP5_INTF_BORDER_COLOR()
1854 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN…  in REG_MDP5_INTF_UNDERFLOW_COLOR()
1856 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0…  in REG_MDP5_INTF_HSYNC_SKEW()
1858 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(…  in REG_MDP5_INTF_POLARITY_CTL()
1863 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);…  in REG_MDP5_INTF_TEST_CTL()
1865 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR0()
1867 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR1()
1869 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o…  in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1871 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(…  in REG_MDP5_INTF_PANEL_FORMAT()
1873 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse…  in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1875 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i…  in REG_MDP5_INTF_FRAME_COUNT()
1877 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0…  in REG_MDP5_INTF_LINE_COUNT()
1879 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I…  in REG_MDP5_INTF_DEFLICKER_CONFIG()
1881 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off…  in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1883 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs…  in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1885 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0…  in REG_MDP5_INTF_TPG_ENABLE()
1887 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I…  in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1889 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I…  in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1891 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs…  in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1893 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF…  in REG_MDP5_INTF_TPG_RECTANGLE()
1895 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_…  in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1897 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +…  in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1899 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN…  in REG_MDP5_INTF_TPG_RGB_MAPPING()
1901 static inline uint32_t __offset_AD(uint32_t idx)  in __offset_AD()
1909 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD()
1911 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD_BYPASS()
1913 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_0()
1915 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_1()
1917 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }  in REG_MDP5_AD_FRAME_SIZE()
1919 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_0()
1921 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_1()
1923 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }  in REG_MDP5_AD_STR_MAN()
1925 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }  in REG_MDP5_AD_VAR()
1927 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }  in REG_MDP5_AD_DITH()
1929 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }  in REG_MDP5_AD_DITH_CTRL()
1931 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }  in REG_MDP5_AD_AMP_LIM()
1933 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }  in REG_MDP5_AD_SLOPE()
1935 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }  in REG_MDP5_AD_BW_LVL()
1937 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }  in REG_MDP5_AD_LOGO_POS()
1939 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_FI()
1941 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }  in REG_MDP5_AD_LUT_CC()
1943 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }  in REG_MDP5_AD_STR_LIM()
1945 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_AB()
1947 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_CD()
1949 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }  in REG_MDP5_AD_MODE_SEL()
1951 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }  in REG_MDP5_AD_TFILT_CTRL()
1953 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }  in REG_MDP5_AD_BL_MINMAX()
1955 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }  in REG_MDP5_AD_BL()
1957 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }  in REG_MDP5_AD_BL_MAX()
1959 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }  in REG_MDP5_AD_AL()
1961 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }  in REG_MDP5_AD_AL_MIN()
1963 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }  in REG_MDP5_AD_AL_FILT()
1965 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }  in REG_MDP5_AD_CFG_BUF()
1967 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_AL()
1969 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }  in REG_MDP5_AD_TARG_STR()
1971 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }  in REG_MDP5_AD_START_CALC()
1973 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }  in REG_MDP5_AD_STR_OUT()
1975 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }  in REG_MDP5_AD_BL_OUT()
1977 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }  in REG_MDP5_AD_CALC_DONE()