Lines Matching +full:0 +full:x00000003
52 VS_DEALLOC = 0,
101 DI_PT_NONE = 0,
150 DI_SRC_SEL_DMA = 0,
157 DI_FACE_CULL_NONE = 0,
164 INDEX_SIZE_IGN = 0,
165 INDEX_SIZE_16_BIT = 0,
168 INDEX_SIZE_INVALID = 0,
172 IGNORE_VISIBILITY = 0,
177 CP_TYPE0_PKT = 0,
178 CP_TYPE1_PKT = 0x40000000,
179 CP_TYPE2_PKT = 0x80000000,
180 CP_TYPE3_PKT = 0xc0000000,
181 CP_TYPE4_PKT = 0x40000000,
182 CP_TYPE7_PKT = 0x70000000,
305 SB_VERT_TEX = 0,
316 ST_SHADER = 0,
321 SS_DIRECT = 0,
330 SB4_VS_TEX = 0,
347 ST4_SHADER = 0,
353 SS4_DIRECT = 0,
358 SB6_VS_TEX = 0,
375 ST6_SHADER = 0,
382 SS6_DIRECT = 0,
389 INDEX4_SIZE_8_BIT = 0,
395 TESS_QUADS = 0,
412 NE_0_PASS = 0,
417 WRITE_ALWAYS = 0,
436 BLIT_OP_FILL = 0,
457 SMMU_INFO = 0,
471 RESTORE_IB = 0,
483 #define REG_CP_LOAD_STATE_0 0x00000000
484 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
485 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
490 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
496 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
502 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
509 #define REG_CP_LOAD_STATE_1 0x00000001
510 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
511 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
516 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
523 #define REG_CP_LOAD_STATE4_0 0x00000000
524 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
525 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
530 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
536 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
542 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
549 #define REG_CP_LOAD_STATE4_1 0x00000001
550 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
551 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
556 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
563 #define REG_CP_LOAD_STATE4_2 0x00000002
564 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
565 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
571 #define REG_CP_LOAD_STATE6_0 0x00000000
572 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
573 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
578 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
584 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
590 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
596 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
603 #define REG_CP_LOAD_STATE6_1 0x00000001
604 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
611 #define REG_CP_LOAD_STATE6_2 0x00000002
612 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
613 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
619 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
621 #define REG_CP_DRAW_INDX_0 0x00000000
622 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
623 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
629 #define REG_CP_DRAW_INDX_1 0x00000001
630 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
631 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
636 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
642 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
648 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
654 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
655 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
656 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
657 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
664 #define REG_CP_DRAW_INDX_2 0x00000002
665 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
666 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
672 #define REG_CP_DRAW_INDX_3 0x00000003
673 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
674 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
680 #define REG_CP_DRAW_INDX_4 0x00000004
681 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
682 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
688 #define REG_CP_DRAW_INDX_2_0 0x00000000
689 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
690 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
696 #define REG_CP_DRAW_INDX_2_1 0x00000001
697 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
698 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
703 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
709 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
715 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
721 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
722 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
723 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
724 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
731 #define REG_CP_DRAW_INDX_2_2 0x00000002
732 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
733 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
739 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
740 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
741 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
746 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
752 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
758 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
764 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
770 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
771 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
773 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
774 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
775 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
781 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
782 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
783 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
789 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
790 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
791 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
798 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
799 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
800 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
806 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
807 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
808 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
814 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
816 #define REG_CP_DRAW_INDX_OFFSET_6 0x00000006
817 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
818 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
824 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
825 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
826 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
832 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
833 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
834 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
840 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
841 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
842 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
847 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
853 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
859 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
865 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
871 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
872 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
875 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
876 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
877 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
884 #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
885 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
886 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
892 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
893 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
894 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
900 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
902 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
903 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
904 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
909 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
915 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
921 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
927 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
933 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
934 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
937 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
938 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
939 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
945 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
946 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
947 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
953 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
954 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
955 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
962 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
963 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
964 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
970 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
971 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
972 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
978 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
980 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
981 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
982 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
988 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
989 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
990 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
996 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
997 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
998 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
1004 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
1006 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
1007 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
1008 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
1013 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
1019 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
1025 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
1031 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
1037 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
1038 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
1040 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
1041 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
1042 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
1047 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
1054 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
1057 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1059 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1062 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
1064 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
1066 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
1068 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
1071 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
1073 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
1075 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
1078 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
1080 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
1082 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
1084 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
1086 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
1088 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
1089 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
1091 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
1092 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
1094 #define REG_CP_DRAW_PRED_SET_0 0x00000000
1095 #define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
1101 #define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
1108 #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
1110 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE_()
1112 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__0()
1113 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
1114 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
1119 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
1120 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
1121 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
1122 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
1123 #define CP_SET_DRAW_STATE__0_BINNING 0x00100000
1124 #define CP_SET_DRAW_STATE__0_GMEM 0x00200000
1125 #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
1126 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
1133 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__1()
1134 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
1135 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
1141 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__2()
1142 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
1143 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
1149 #define REG_CP_SET_BIN_0 0x00000000
1151 #define REG_CP_SET_BIN_1 0x00000001
1152 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
1153 #define CP_SET_BIN_1_X1__SHIFT 0
1158 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
1165 #define REG_CP_SET_BIN_2 0x00000002
1166 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
1167 #define CP_SET_BIN_2_X2__SHIFT 0
1172 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
1179 #define REG_CP_SET_BIN_DATA_0 0x00000000
1180 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
1181 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
1187 #define REG_CP_SET_BIN_DATA_1 0x00000001
1188 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
1189 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
1195 #define REG_CP_SET_BIN_DATA5_0 0x00000000
1196 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
1202 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
1209 #define REG_CP_SET_BIN_DATA5_1 0x00000001
1210 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
1211 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
1217 #define REG_CP_SET_BIN_DATA5_2 0x00000002
1218 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
1219 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
1225 #define REG_CP_SET_BIN_DATA5_3 0x00000003
1226 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
1227 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
1233 #define REG_CP_SET_BIN_DATA5_4 0x00000004
1234 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
1235 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
1241 #define REG_CP_SET_BIN_DATA5_5 0x00000005
1242 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
1243 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
1249 #define REG_CP_SET_BIN_DATA5_6 0x00000006
1250 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
1251 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
1257 #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
1258 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
1264 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
1271 #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
1272 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
1273 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
1279 #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
1280 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
1281 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
1287 #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
1288 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
1289 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
1295 #define REG_CP_REG_RMW_0 0x00000000
1296 #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
1297 #define CP_REG_RMW_0_DST_REG__SHIFT 0
1302 #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
1308 #define CP_REG_RMW_0_SRC1_ADD 0x20000000
1309 #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
1310 #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
1312 #define REG_CP_REG_RMW_1 0x00000001
1313 #define CP_REG_RMW_1_SRC0__MASK 0xffffffff
1314 #define CP_REG_RMW_1_SRC0__SHIFT 0
1320 #define REG_CP_REG_RMW_2 0x00000002
1321 #define CP_REG_RMW_2_SRC1__MASK 0xffffffff
1322 #define CP_REG_RMW_2_SRC1__SHIFT 0
1328 #define REG_CP_REG_TO_MEM_0 0x00000000
1329 #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
1330 #define CP_REG_TO_MEM_0_REG__SHIFT 0
1335 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
1341 #define CP_REG_TO_MEM_0_64B 0x40000000
1342 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1344 #define REG_CP_REG_TO_MEM_1 0x00000001
1345 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1346 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
1352 #define REG_CP_REG_TO_MEM_2 0x00000002
1353 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1354 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1360 #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
1361 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
1362 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
1367 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
1373 #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
1374 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
1376 #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
1377 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
1378 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
1384 #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
1385 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
1386 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
1392 #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
1393 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
1394 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
1399 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
1401 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
1402 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
1403 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
1408 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
1414 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
1415 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
1417 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
1418 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
1419 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
1425 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
1426 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
1427 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
1433 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
1434 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
1435 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
1441 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
1442 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
1443 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
1449 #define REG_CP_MEM_TO_REG_0 0x00000000
1450 #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
1451 #define CP_MEM_TO_REG_0_REG__SHIFT 0
1456 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1462 #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
1463 #define CP_MEM_TO_REG_0_UNK31 0x80000000
1465 #define REG_CP_MEM_TO_REG_1 0x00000001
1466 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1467 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
1473 #define REG_CP_MEM_TO_REG_2 0x00000002
1474 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1475 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1481 #define REG_CP_MEM_TO_MEM_0 0x00000000
1482 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1483 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1484 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1485 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1486 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
1487 #define CP_MEM_TO_MEM_0_UNK31 0x80000000
1489 #define REG_CP_MEMCPY_0 0x00000000
1490 #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
1491 #define CP_MEMCPY_0_DWORDS__SHIFT 0
1497 #define REG_CP_MEMCPY_1 0x00000001
1498 #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
1499 #define CP_MEMCPY_1_SRC_LO__SHIFT 0
1505 #define REG_CP_MEMCPY_2 0x00000002
1506 #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
1507 #define CP_MEMCPY_2_SRC_HI__SHIFT 0
1513 #define REG_CP_MEMCPY_3 0x00000003
1514 #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
1515 #define CP_MEMCPY_3_DST_LO__SHIFT 0
1521 #define REG_CP_MEMCPY_4 0x00000004
1522 #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
1523 #define CP_MEMCPY_4_DST_HI__SHIFT 0
1529 #define REG_CP_REG_TO_SCRATCH_0 0x00000000
1530 #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
1531 #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
1536 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
1542 #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
1549 #define REG_CP_SCRATCH_TO_REG_0 0x00000000
1550 #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
1551 #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
1556 #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
1557 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
1563 #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
1570 #define REG_CP_SCRATCH_WRITE_0 0x00000000
1571 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
1578 #define REG_CP_MEM_WRITE_0 0x00000000
1579 #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
1580 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
1586 #define REG_CP_MEM_WRITE_1 0x00000001
1587 #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
1588 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
1594 #define REG_CP_COND_WRITE_0 0x00000000
1595 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1596 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1601 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1602 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1604 #define REG_CP_COND_WRITE_1 0x00000001
1605 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1606 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1612 #define REG_CP_COND_WRITE_2 0x00000002
1613 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1614 #define CP_COND_WRITE_2_REF__SHIFT 0
1620 #define REG_CP_COND_WRITE_3 0x00000003
1621 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1622 #define CP_COND_WRITE_3_MASK__SHIFT 0
1628 #define REG_CP_COND_WRITE_4 0x00000004
1629 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1630 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1636 #define REG_CP_COND_WRITE_5 0x00000005
1637 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1638 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1644 #define REG_CP_COND_WRITE5_0 0x00000000
1645 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1646 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1651 #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
1652 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1653 #define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020
1654 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1656 #define REG_CP_COND_WRITE5_1 0x00000001
1657 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1658 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1664 #define REG_CP_COND_WRITE5_2 0x00000002
1665 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1666 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1672 #define REG_CP_COND_WRITE5_3 0x00000003
1673 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1674 #define CP_COND_WRITE5_3_REF__SHIFT 0
1680 #define REG_CP_COND_WRITE5_4 0x00000004
1681 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1682 #define CP_COND_WRITE5_4_MASK__SHIFT 0
1688 #define REG_CP_COND_WRITE5_5 0x00000005
1689 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1690 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1696 #define REG_CP_COND_WRITE5_6 0x00000006
1697 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1698 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1704 #define REG_CP_COND_WRITE5_7 0x00000007
1705 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1706 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1712 #define REG_CP_WAIT_MEM_GTE_0 0x00000000
1713 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
1714 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
1720 #define REG_CP_WAIT_MEM_GTE_1 0x00000001
1721 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
1722 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
1728 #define REG_CP_WAIT_MEM_GTE_2 0x00000002
1729 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
1730 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
1736 #define REG_CP_WAIT_MEM_GTE_3 0x00000003
1737 #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
1738 #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
1744 #define REG_CP_WAIT_REG_MEM_0 0x00000000
1745 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
1746 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
1751 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
1752 #define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010
1753 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020
1754 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
1756 #define REG_CP_WAIT_REG_MEM_1 0x00000001
1757 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
1758 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
1764 #define REG_CP_WAIT_REG_MEM_2 0x00000002
1765 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
1766 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
1772 #define REG_CP_WAIT_REG_MEM_3 0x00000003
1773 #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
1774 #define CP_WAIT_REG_MEM_3_REF__SHIFT 0
1780 #define REG_CP_WAIT_REG_MEM_4 0x00000004
1781 #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
1782 #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
1788 #define REG_CP_WAIT_REG_MEM_5 0x00000005
1789 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
1790 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
1796 #define REG_CP_WAIT_TWO_REGS_0 0x00000000
1797 #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
1798 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
1804 #define REG_CP_WAIT_TWO_REGS_1 0x00000001
1805 #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
1806 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
1812 #define REG_CP_WAIT_TWO_REGS_2 0x00000002
1813 #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
1814 #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
1820 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1822 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1823 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1824 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1830 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1831 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1832 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1838 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1839 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1840 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1846 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1847 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1848 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1854 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1855 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1856 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1862 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1863 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1864 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1870 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1871 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1872 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1874 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1876 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1877 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1878 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1884 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1885 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1886 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1892 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1893 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1894 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1900 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1901 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1902 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1908 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1909 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1910 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1916 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1918 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1919 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1920 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1926 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1928 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1929 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1930 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1936 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1937 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1938 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1944 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1946 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1948 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1949 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1950 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
1956 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1957 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1958 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
1964 #define REG_CP_EVENT_WRITE_0 0x00000000
1965 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1966 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1971 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1972 #define CP_EVENT_WRITE_0_IRQ 0x80000000
1974 #define REG_CP_EVENT_WRITE_1 0x00000001
1975 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1976 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1982 #define REG_CP_EVENT_WRITE_2 0x00000002
1983 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1984 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1990 #define REG_CP_EVENT_WRITE_3 0x00000003
1992 #define REG_CP_BLIT_0 0x00000000
1993 #define CP_BLIT_0_OP__MASK 0x0000000f
1994 #define CP_BLIT_0_OP__SHIFT 0
2000 #define REG_CP_BLIT_1 0x00000001
2001 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
2002 #define CP_BLIT_1_SRC_X1__SHIFT 0
2007 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
2014 #define REG_CP_BLIT_2 0x00000002
2015 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
2016 #define CP_BLIT_2_SRC_X2__SHIFT 0
2021 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
2028 #define REG_CP_BLIT_3 0x00000003
2029 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
2030 #define CP_BLIT_3_DST_X1__SHIFT 0
2035 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
2042 #define REG_CP_BLIT_4 0x00000004
2043 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
2044 #define CP_BLIT_4_DST_X2__SHIFT 0
2049 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
2056 #define REG_CP_EXEC_CS_0 0x00000000
2058 #define REG_CP_EXEC_CS_1 0x00000001
2059 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
2060 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
2066 #define REG_CP_EXEC_CS_2 0x00000002
2067 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
2068 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
2074 #define REG_CP_EXEC_CS_3 0x00000003
2075 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
2076 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
2082 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
2085 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2086 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
2087 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
2093 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2094 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
2100 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
2106 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
2114 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2115 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
2116 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
2122 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2123 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
2124 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
2130 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
2131 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
2137 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
2143 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
2150 #define REG_A6XX_CP_SET_MARKER_0 0x00000000
2151 #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
2152 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
2157 #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
2158 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
2164 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG_()
2166 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__0()
2167 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
2168 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
2174 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__1()
2175 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
2176 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
2182 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__2()
2183 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
2184 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
2190 #define REG_A6XX_CP_REG_TEST_0 0x00000000
2191 #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
2192 #define A6XX_CP_REG_TEST_0_REG__SHIFT 0
2197 #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
2203 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000
2205 #define REG_CP_COND_REG_EXEC_0 0x00000000
2206 #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
2207 #define CP_COND_REG_EXEC_0_REG0__SHIFT 0
2212 #define CP_COND_REG_EXEC_0_BINNING 0x02000000
2213 #define CP_COND_REG_EXEC_0_GMEM 0x04000000
2214 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
2215 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
2222 #define REG_CP_COND_REG_EXEC_1 0x00000001
2223 #define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff
2224 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
2230 #define REG_CP_COND_EXEC_0 0x00000000
2231 #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
2232 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
2238 #define REG_CP_COND_EXEC_1 0x00000001
2239 #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
2240 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
2246 #define REG_CP_COND_EXEC_2 0x00000002
2247 #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
2248 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
2254 #define REG_CP_COND_EXEC_3 0x00000003
2255 #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
2256 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
2262 #define REG_CP_COND_EXEC_4 0x00000004
2263 #define CP_COND_EXEC_4_REF__MASK 0xffffffff
2264 #define CP_COND_EXEC_4_REF__SHIFT 0
2270 #define REG_CP_COND_EXEC_5 0x00000005
2271 #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
2272 #define CP_COND_EXEC_5_DWORDS__SHIFT 0
2278 #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
2279 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
2280 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
2286 #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
2287 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
2288 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
2294 #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
2295 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
2296 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
2301 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
2308 #define REG_CP_REG_WRITE_0 0x00000000
2309 #define CP_REG_WRITE_0_TRACKER__MASK 0x00000007
2310 #define CP_REG_WRITE_0_TRACKER__SHIFT 0
2316 #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
2317 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
2318 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
2324 #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
2325 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
2326 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
2331 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
2338 #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
2339 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
2340 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
2346 #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
2347 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
2348 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0