28 		OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));  in update_shadow_rptr()
29 		OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));  in update_shadow_rptr()
104 				OUT_RING(ring, ptr[i]);  in a5xx_submit_in_rb()
140 	OUT_RING(ring, 0x02);  in a5xx_submit()
144 	OUT_RING(ring, 0);  in a5xx_submit()
148 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
149 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
153 	OUT_RING(ring, 1);  in a5xx_submit()
157 	OUT_RING(ring, 0x02);  in a5xx_submit()
161 	OUT_RING(ring, 0x02);  in a5xx_submit()
174 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a5xx_submit()
175 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a5xx_submit()
176 			OUT_RING(ring, submit->cmd[i].size);  in a5xx_submit()
198 	OUT_RING(ring, 0);  in a5xx_submit()
199 	OUT_RING(ring, 0);  in a5xx_submit()
200 	OUT_RING(ring, 0);  in a5xx_submit()
201 	OUT_RING(ring, 0);  in a5xx_submit()
202 	OUT_RING(ring, 0);  in a5xx_submit()
206 	OUT_RING(ring, 0x01);  in a5xx_submit()
210 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
217 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |  in a5xx_submit()
219 	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
220 	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
221 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
230 	OUT_RING(ring, 0x00);  in a5xx_submit()
231 	OUT_RING(ring, 0x00);  in a5xx_submit()
233 	OUT_RING(ring, 0x01);  in a5xx_submit()
235 	OUT_RING(ring, 0x01);  in a5xx_submit()
475 	OUT_RING(ring, 0x0000002F);  in a5xx_me_init()
478 	OUT_RING(ring, 0x00000003);  in a5xx_me_init()
481 	OUT_RING(ring, 0x20000000);  in a5xx_me_init()
484 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
485 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
493 		OUT_RING(ring, 0x0000000B);  in a5xx_me_init()
496 		OUT_RING(ring, 0x00000001);  in a5xx_me_init()
499 		OUT_RING(ring, 0x00000000);  in a5xx_me_init()
502 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
503 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
520 	OUT_RING(ring, 0);  in a5xx_preempt_start()
524 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
525 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
529 	OUT_RING(ring, 1);  in a5xx_preempt_start()
532 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
535 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
538 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
542 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
543 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
544 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
545 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
961 		OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT));  in a5xx_hw_init()
979 		OUT_RING(gpu->rb[0], 0x00000000);  in a5xx_hw_init()