100 	TILE5_LINEAR = 0,
261 	DEPTH5_NONE = 0,
268 	BLIT_MRT0 = 0,
281 	PERF_CP_ALWAYS_COUNT = 0,
315 	PERF_RBBM_ALWAYS_COUNT = 0,
332 	PERF_PC_BUSY_CYCLES = 0,
372 	PERF_VFD_BUSY_CYCLES = 0,
406 	PERF_HLSQ_BUSY_CYCLES = 0,
424 	PERF_VPC_BUSY_CYCLES = 0,
444 	PERF_TSE_BUSY_CYCLES = 0,
466 	PERF_RAS_BUSY_CYCLES = 0,
479 	PERF_LRZ_BUSY_CYCLES = 0,
501 	PERF_UCHE_BUSY_CYCLES = 0,
535 	PERF_TP_BUSY_CYCLES = 0,
580 	PERF_SP_BUSY_CYCLES = 0,
648 	PERF_RB_BUSY_CYCLES = 0,
681 	TOTAL_SAMPLES = 0,
688 	PERF_VSC_BUSY_CYCLES = 0,
695 	PERF_CCU_BUSY_CYCLES = 0,
724 	PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
751 	AXI_READ_REQUESTS_ID_0 = 0,
840 	A5XX_TEX_NEAREST = 0,
846 	A5XX_TEX_REPEAT = 0,
854 	A5XX_TEX_ANISO_1 = 0,
862 	A5XX_TEX_X = 0,
871 	A5XX_TEX_1D = 0,
877 #define A5XX_INT0_RBBM_GPU_IDLE					0x00000001
878 #define A5XX_INT0_RBBM_AHB_ERROR				0x00000002
879 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT				0x00000004
880 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
881 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
882 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT				0x00000020
883 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW			0x00000040
884 #define A5XX_INT0_RBBM_GPC_ERROR				0x00000080
885 #define A5XX_INT0_CP_SW						0x00000100
886 #define A5XX_INT0_CP_HW_ERROR					0x00000200
887 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS				0x00000400
888 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS				0x00000800
889 #define A5XX_INT0_CP_CCU_RESOLVE_TS				0x00001000
890 #define A5XX_INT0_CP_IB2					0x00002000
891 #define A5XX_INT0_CP_IB1					0x00004000
892 #define A5XX_INT0_CP_RB						0x00008000
893 #define A5XX_INT0_CP_UNUSED_1					0x00010000
894 #define A5XX_INT0_CP_RB_DONE_TS					0x00020000
895 #define A5XX_INT0_CP_WT_DONE_TS					0x00040000
896 #define A5XX_INT0_UNKNOWN_1					0x00080000
897 #define A5XX_INT0_CP_CACHE_FLUSH_TS				0x00100000
898 #define A5XX_INT0_UNUSED_2					0x00200000
899 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00400000
900 #define A5XX_INT0_MISC_HANG_DETECT				0x00800000
901 #define A5XX_INT0_UCHE_OOB_ACCESS				0x01000000
902 #define A5XX_INT0_UCHE_TRAP_INTR				0x02000000
903 #define A5XX_INT0_DEBBUS_INTR_0					0x04000000
904 #define A5XX_INT0_DEBBUS_INTR_1					0x08000000
905 #define A5XX_INT0_GPMU_VOLTAGE_DROOP				0x10000000
906 #define A5XX_INT0_GPMU_FIRMWARE					0x20000000
907 #define A5XX_INT0_ISDB_CPU_IRQ					0x40000000
908 #define A5XX_INT0_ISDB_UNDER_DEBUG				0x80000000
909 #define A5XX_CP_INT_CP_OPCODE_ERROR				0x00000001
910 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR			0x00000002
911 #define A5XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
912 #define A5XX_CP_INT_CP_DMA_ERROR				0x00000008
913 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
914 #define A5XX_CP_INT_CP_AHB_ERROR				0x00000020
915 #define REG_A5XX_CP_RB_BASE					0x00000800
917 #define REG_A5XX_CP_RB_BASE_HI					0x00000801
919 #define REG_A5XX_CP_RB_CNTL					0x00000802
921 #define REG_A5XX_CP_RB_RPTR_ADDR				0x00000804
923 #define REG_A5XX_CP_RB_RPTR_ADDR_HI				0x00000805
925 #define REG_A5XX_CP_RB_RPTR					0x00000806
927 #define REG_A5XX_CP_RB_WPTR					0x00000807
929 #define REG_A5XX_CP_PFP_STAT_ADDR				0x00000808
931 #define REG_A5XX_CP_PFP_STAT_DATA				0x00000809
933 #define REG_A5XX_CP_DRAW_STATE_ADDR				0x0000080b
935 #define REG_A5XX_CP_DRAW_STATE_DATA				0x0000080c
937 #define REG_A5XX_CP_ME_NRT_ADDR_LO				0x0000080d
939 #define REG_A5XX_CP_ME_NRT_ADDR_HI				0x0000080e
941 #define REG_A5XX_CP_ME_NRT_DATA					0x00000810
943 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO			0x00000817
945 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI			0x00000818
947 #define REG_A5XX_CP_CRASH_DUMP_CNTL				0x00000819
949 #define REG_A5XX_CP_ME_STAT_ADDR				0x0000081a
951 #define REG_A5XX_CP_ROQ_THRESHOLDS_1				0x0000081f
953 #define REG_A5XX_CP_ROQ_THRESHOLDS_2				0x00000820
955 #define REG_A5XX_CP_ROQ_DBG_ADDR				0x00000821
957 #define REG_A5XX_CP_ROQ_DBG_DATA				0x00000822
959 #define REG_A5XX_CP_MEQ_DBG_ADDR				0x00000823
961 #define REG_A5XX_CP_MEQ_DBG_DATA				0x00000824
963 #define REG_A5XX_CP_MEQ_THRESHOLDS				0x00000825
965 #define REG_A5XX_CP_MERCIU_SIZE					0x00000826
967 #define REG_A5XX_CP_MERCIU_DBG_ADDR				0x00000827
969 #define REG_A5XX_CP_MERCIU_DBG_DATA_1				0x00000828
971 #define REG_A5XX_CP_MERCIU_DBG_DATA_2				0x00000829
973 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR				0x0000082a
975 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA				0x0000082b
977 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR				0x0000082f
979 #define REG_A5XX_CP_ME_UCODE_DBG_DATA				0x00000830
981 #define REG_A5XX_CP_CNTL					0x00000831
983 #define REG_A5XX_CP_PFP_ME_CNTL					0x00000832
985 #define REG_A5XX_CP_CHICKEN_DBG					0x00000833
987 #define REG_A5XX_CP_PFP_INSTR_BASE_LO				0x00000835
989 #define REG_A5XX_CP_PFP_INSTR_BASE_HI				0x00000836
991 #define REG_A5XX_CP_ME_INSTR_BASE_LO				0x00000838
993 #define REG_A5XX_CP_ME_INSTR_BASE_HI				0x00000839
995 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL				0x0000083b
997 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO		0x0000083c
999 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI		0x0000083d
1001 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO			0x0000083e
1003 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI			0x0000083f
1005 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO			0x00000840
1007 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI			0x00000841
1009 #define REG_A5XX_CP_ADDR_MODE_CNTL				0x00000860
1011 #define REG_A5XX_CP_ME_STAT_DATA				0x00000b14
1013 #define REG_A5XX_CP_WFI_PEND_CTR				0x00000b15
1015 #define REG_A5XX_CP_INTERRUPT_STATUS				0x00000b18
1017 #define REG_A5XX_CP_HW_FAULT					0x00000b1a
1019 #define REG_A5XX_CP_PROTECT_STATUS				0x00000b1c
1021 #define REG_A5XX_CP_IB1_BASE					0x00000b1f
1023 #define REG_A5XX_CP_IB1_BASE_HI					0x00000b20
1025 #define REG_A5XX_CP_IB1_BUFSZ					0x00000b21
1027 #define REG_A5XX_CP_IB2_BASE					0x00000b22
1029 #define REG_A5XX_CP_IB2_BASE_HI					0x00000b23
1031 #define REG_A5XX_CP_IB2_BUFSZ					0x00000b24
1033 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }  in REG_A5XX_CP_SCRATCH()
1035 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }  in REG_A5XX_CP_SCRATCH_REG()
1037 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }  in REG_A5XX_CP_PROTECT()
1039 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }  in REG_A5XX_CP_PROTECT_REG()
1040 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff
1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
1046 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000
1052 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK			0x20000000
1058 #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK			0x40000000
1065 #define REG_A5XX_CP_PROTECT_CNTL				0x000008a0
1067 #define REG_A5XX_CP_AHB_FAULT					0x00000b1b
1069 #define REG_A5XX_CP_PERFCTR_CP_SEL_0				0x00000bb0
1071 #define REG_A5XX_CP_PERFCTR_CP_SEL_1				0x00000bb1
1073 #define REG_A5XX_CP_PERFCTR_CP_SEL_2				0x00000bb2
1075 #define REG_A5XX_CP_PERFCTR_CP_SEL_3				0x00000bb3
1077 #define REG_A5XX_CP_PERFCTR_CP_SEL_4				0x00000bb4
1079 #define REG_A5XX_CP_PERFCTR_CP_SEL_5				0x00000bb5
1081 #define REG_A5XX_CP_PERFCTR_CP_SEL_6				0x00000bb6
1083 #define REG_A5XX_CP_PERFCTR_CP_SEL_7				0x00000bb7
1085 #define REG_A5XX_VSC_ADDR_MODE_CNTL				0x00000bc1
1087 #define REG_A5XX_CP_POWERCTR_CP_SEL_0				0x00000bba
1089 #define REG_A5XX_CP_POWERCTR_CP_SEL_1				0x00000bbb
1091 #define REG_A5XX_CP_POWERCTR_CP_SEL_2				0x00000bbc
1093 #define REG_A5XX_CP_POWERCTR_CP_SEL_3				0x00000bbd
1095 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A				0x00000004
1097 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B				0x00000005
1099 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C				0x00000006
1101 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D				0x00000007
1103 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT				0x00000008
1105 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM				0x00000009
1107 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT		0x00000018
1109 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL				0x0000000a
1111 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE				0x0000000b
1113 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0				0x0000000c
1115 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1				0x0000000d
1117 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2				0x0000000e
1119 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3				0x0000000f
1121 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0			0x00000010
1123 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1			0x00000011
1125 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2			0x00000012
1127 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3			0x00000013
1129 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0			0x00000014
1131 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1			0x00000015
1133 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0				0x00000016
1135 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1				0x00000017
1137 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2				0x00000018
1139 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3				0x00000019
1141 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0			0x0000001a
1143 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1			0x0000001b
1145 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2			0x0000001c
1147 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3			0x0000001d
1149 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE			0x0000001e
1151 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0				0x0000001f
1153 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1				0x00000020
1155 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG			0x00000021
1157 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX				0x00000022
1159 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC				0x00000023
1161 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT			0x00000024
1163 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000002f
1165 #define REG_A5XX_RBBM_INT_CLEAR_CMD				0x00000037
1167 #define REG_A5XX_RBBM_INT_0_MASK				0x00000038
1168 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
1169 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR			0x00000002
1170 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT		0x00000004
1171 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT			0x00000008
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT		0x00000010
1173 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT		0x00000020
1174 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW		0x00000040
1175 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
1176 #define A5XX_RBBM_INT_0_MASK_CP_SW				0x00000100
1177 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
1178 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
1179 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
1180 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
1181 #define A5XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
1182 #define A5XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
1183 #define A5XX_RBBM_INT_0_MASK_CP_RB				0x00008000
1184 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
1185 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
1186 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
1187 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
1188 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT			0x00800000
1189 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
1190 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
1191 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
1192 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
1193 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP			0x10000000
1194 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE			0x20000000
1195 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
1196 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
1198 #define REG_A5XX_RBBM_AHB_DBG_CNTL				0x0000003f
1200 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL				0x00000041
1202 #define REG_A5XX_RBBM_SW_RESET_CMD				0x00000043
1204 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1206 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046
1208 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO				0x00000048
1210 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL			0x00000049
1212 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0				0x0000004a
1214 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1				0x0000004b
1216 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2				0x0000004c
1218 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3				0x0000004d
1220 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0				0x0000004e
1222 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1				0x0000004f
1224 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2				0x00000050
1226 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3				0x00000051
1228 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0				0x00000052
1230 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1				0x00000053
1232 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2				0x00000054
1234 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3				0x00000055
1236 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG			0x00000059
1238 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE				0x0000005a
1240 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE				0x0000005b
1242 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE				0x0000005c
1244 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE				0x0000005d
1246 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE				0x0000005e
1248 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE				0x0000005f
1250 #define REG_A5XX_RBBM_CLOCK_MODE_GPC				0x00000060
1252 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC				0x00000061
1254 #define REG_A5XX_RBBM_CLOCK_HYST_GPC				0x00000062
1256 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000063
1258 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x00000064
1260 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000065
1262 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ				0x00000066
1264 #define REG_A5XX_RBBM_CLOCK_CNTL				0x00000067
1266 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0				0x00000068
1268 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1				0x00000069
1270 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2				0x0000006a
1272 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3				0x0000006b
1274 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0				0x0000006c
1276 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1				0x0000006d
1278 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2				0x0000006e
1280 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3				0x0000006f
1282 #define REG_A5XX_RBBM_CLOCK_HYST_SP0				0x00000070
1284 #define REG_A5XX_RBBM_CLOCK_HYST_SP1				0x00000071
1286 #define REG_A5XX_RBBM_CLOCK_HYST_SP2				0x00000072
1288 #define REG_A5XX_RBBM_CLOCK_HYST_SP3				0x00000073
1290 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0				0x00000074
1292 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1				0x00000075
1294 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2				0x00000076
1296 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3				0x00000077
1298 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0				0x00000078
1300 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1				0x00000079
1302 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2				0x0000007a
1304 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3				0x0000007b
1306 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0				0x0000007c
1308 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1				0x0000007d
1310 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2				0x0000007e
1312 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3				0x0000007f
1314 #define REG_A5XX_RBBM_CLOCK_HYST_RAC				0x00000080
1316 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC				0x00000081
1318 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0				0x00000082
1320 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1				0x00000083
1322 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2				0x00000084
1324 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3				0x00000085
1326 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000086
1328 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000087
1330 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000088
1332 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000089
1334 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC				0x0000008a
1336 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC				0x0000008b
1338 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0			0x0000008c
1340 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1			0x0000008d
1342 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2			0x0000008e
1344 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3			0x0000008f
1346 #define REG_A5XX_RBBM_CLOCK_HYST_VFD				0x00000090
1348 #define REG_A5XX_RBBM_CLOCK_MODE_VFD				0x00000091
1350 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD				0x00000092
1352 #define REG_A5XX_RBBM_AHB_CNTL0					0x00000093
1354 #define REG_A5XX_RBBM_AHB_CNTL1					0x00000094
1356 #define REG_A5XX_RBBM_AHB_CNTL2					0x00000095
1358 #define REG_A5XX_RBBM_AHB_CMD					0x00000096
1360 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11		0x0000009c
1362 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12		0x0000009d
1364 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13		0x0000009e
1366 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14		0x0000009f
1368 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15		0x000000a0
1370 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16		0x000000a1
1372 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17		0x000000a2
1374 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18		0x000000a3
1376 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0				0x000000a4
1378 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1				0x000000a5
1380 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2				0x000000a6
1382 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3				0x000000a7
1384 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0				0x000000a8
1386 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1				0x000000a9
1388 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2				0x000000aa
1390 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3				0x000000ab
1392 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0				0x000000ac
1394 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1				0x000000ad
1396 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2				0x000000ae
1398 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3				0x000000af
1400 #define REG_A5XX_RBBM_CLOCK_HYST_TP0				0x000000b0
1402 #define REG_A5XX_RBBM_CLOCK_HYST_TP1				0x000000b1
1404 #define REG_A5XX_RBBM_CLOCK_HYST_TP2				0x000000b2
1406 #define REG_A5XX_RBBM_CLOCK_HYST_TP3				0x000000b3
1408 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0				0x000000b4
1410 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1				0x000000b5
1412 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2				0x000000b6
1414 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3				0x000000b7
1416 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0				0x000000b8
1418 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1				0x000000b9
1420 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2				0x000000ba
1422 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3				0x000000bb
1424 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU				0x000000c8
1426 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU				0x000000c9
1428 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU				0x000000ca
1430 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO				0x000003a0
1432 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI				0x000003a1
1434 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO				0x000003a2
1436 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI				0x000003a3
1438 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO				0x000003a4
1440 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI				0x000003a5
1442 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO				0x000003a6
1444 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI				0x000003a7
1446 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO				0x000003a8
1448 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI				0x000003a9
1450 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO				0x000003aa
1452 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI				0x000003ab
1454 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO				0x000003ac
1456 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI				0x000003ad
1458 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO				0x000003ae
1460 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI				0x000003af
1462 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO				0x000003b0
1464 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI				0x000003b1
1466 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO				0x000003b2
1468 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI				0x000003b3
1470 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO				0x000003b4
1472 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI				0x000003b5
1474 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO				0x000003b6
1476 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI				0x000003b7
1478 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO				0x000003b8
1480 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI				0x000003b9
1482 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO				0x000003ba
1484 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI				0x000003bb
1486 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO				0x000003bc
1488 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI				0x000003bd
1490 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO				0x000003be
1492 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI				0x000003bf
1494 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO				0x000003c0
1496 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI				0x000003c1
1498 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO				0x000003c2
1500 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI				0x000003c3
1502 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO				0x000003c4
1504 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI				0x000003c5
1506 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO				0x000003c6
1508 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI				0x000003c7
1510 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO				0x000003c8
1512 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI				0x000003c9
1514 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO				0x000003ca
1516 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI				0x000003cb
1518 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO				0x000003cc
1520 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI				0x000003cd
1522 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO				0x000003ce
1524 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI				0x000003cf
1526 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO				0x000003d0
1528 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI				0x000003d1
1530 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO				0x000003d2
1532 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI				0x000003d3
1534 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO				0x000003d4
1536 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI				0x000003d5
1538 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO				0x000003d6
1540 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI				0x000003d7
1542 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO				0x000003d8
1544 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI				0x000003d9
1546 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO				0x000003da
1548 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI				0x000003db
1550 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO				0x000003dc
1552 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI				0x000003dd
1554 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO				0x000003de
1556 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI				0x000003df
1558 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO				0x000003e0
1560 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI				0x000003e1
1562 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO				0x000003e2
1564 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI				0x000003e3
1566 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO				0x000003e4
1568 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI				0x000003e5
1570 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO				0x000003e6
1572 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI				0x000003e7
1574 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO				0x000003e8
1576 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI				0x000003e9
1578 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO				0x000003ea
1580 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI				0x000003eb
1582 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO				0x000003ec
1584 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI				0x000003ed
1586 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO				0x000003ee
1588 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI				0x000003ef
1590 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO				0x000003f0
1592 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI				0x000003f1
1594 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO				0x000003f2
1596 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI				0x000003f3
1598 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO				0x000003f4
1600 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI				0x000003f5
1602 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO				0x000003f6
1604 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI				0x000003f7
1606 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO				0x000003f8
1608 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI				0x000003f9
1610 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO				0x000003fa
1612 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI				0x000003fb
1614 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO				0x000003fc
1616 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI				0x000003fd
1618 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO				0x000003fe
1620 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI				0x000003ff
1622 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO				0x00000400
1624 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI				0x00000401
1626 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO				0x00000402
1628 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI				0x00000403
1630 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO				0x00000404
1632 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI				0x00000405
1634 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO				0x00000406
1636 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI				0x00000407
1638 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO				0x00000408
1640 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI				0x00000409
1642 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO				0x0000040a
1644 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI				0x0000040b
1646 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO				0x0000040c
1648 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI				0x0000040d
1650 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO				0x0000040e
1652 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI				0x0000040f
1654 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO				0x00000410
1656 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI				0x00000411
1658 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO				0x00000412
1660 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI				0x00000413
1662 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO				0x00000414
1664 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI				0x00000415
1666 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO				0x00000416
1668 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI				0x00000417
1670 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO				0x00000418
1672 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI				0x00000419
1674 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO				0x0000041a
1676 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI				0x0000041b
1678 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO				0x0000041c
1680 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI				0x0000041d
1682 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO				0x0000041e
1684 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI				0x0000041f
1686 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO				0x00000420
1688 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI				0x00000421
1690 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO				0x00000422
1692 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI				0x00000423
1694 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO				0x00000424
1696 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI				0x00000425
1698 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO				0x00000426
1700 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI				0x00000427
1702 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO				0x00000428
1704 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI				0x00000429
1706 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO				0x0000042a
1708 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI				0x0000042b
1710 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO				0x0000042c
1712 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI				0x0000042d
1714 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO				0x0000042e
1716 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI				0x0000042f
1718 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO				0x00000430
1720 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI				0x00000431
1722 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO				0x00000432
1724 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI				0x00000433
1726 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO				0x00000434
1728 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI				0x00000435
1730 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO				0x00000436
1732 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI				0x00000437
1734 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO				0x00000438
1736 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI				0x00000439
1738 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO				0x0000043a
1740 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI				0x0000043b
1742 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO				0x0000043c
1744 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI				0x0000043d
1746 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO				0x0000043e
1748 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI				0x0000043f
1750 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO				0x00000440
1752 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI				0x00000441
1754 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO				0x00000442
1756 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI				0x00000443
1758 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO				0x00000444
1760 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI				0x00000445
1762 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO				0x00000446
1764 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI				0x00000447
1766 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO				0x00000448
1768 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI				0x00000449
1770 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO				0x0000044a
1772 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI				0x0000044b
1774 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO				0x0000044c
1776 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI				0x0000044d
1778 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO				0x0000044e
1780 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI				0x0000044f
1782 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO				0x00000450
1784 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI				0x00000451
1786 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO				0x00000452
1788 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI				0x00000453
1790 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO				0x00000454
1792 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI				0x00000455
1794 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO				0x00000456
1796 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI				0x00000457
1798 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO				0x00000458
1800 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI				0x00000459
1802 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO				0x0000045a
1804 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI				0x0000045b
1806 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO				0x0000045c
1808 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI				0x0000045d
1810 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO				0x0000045e
1812 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI				0x0000045f
1814 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO				0x00000460
1816 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI				0x00000461
1818 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO				0x00000462
1820 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI				0x00000463
1822 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0			0x0000046b
1824 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1			0x0000046c
1826 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2			0x0000046d
1828 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3			0x0000046e
1830 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO			0x000004d2
1832 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI			0x000004d3
1834 #define REG_A5XX_RBBM_STATUS					0x000004f5
1835 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK			0x80000000
1841 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK		0x40000000
1847 #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK			0x20000000
1853 #define A5XX_RBBM_STATUS_VSC_BUSY__MASK				0x10000000
1859 #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK			0x08000000
1865 #define A5XX_RBBM_STATUS_SP_BUSY__MASK				0x04000000
1871 #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK			0x02000000
1877 #define A5XX_RBBM_STATUS_VPC_BUSY__MASK				0x01000000
1883 #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK			0x00800000
1889 #define A5XX_RBBM_STATUS_VFD_BUSY__MASK				0x00400000
1895 #define A5XX_RBBM_STATUS_TESS_BUSY__MASK			0x00200000
1901 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK			0x00100000
1907 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK			0x00080000
1913 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK			0x00040000
1919 #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK			0x00020000
1925 #define A5XX_RBBM_STATUS_COM_BUSY__MASK				0x00010000
1931 #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK				0x00008000
1937 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK			0x00004000
1943 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK			0x00002000
1949 #define A5XX_RBBM_STATUS_RB_BUSY__MASK				0x00001000
1955 #define A5XX_RBBM_STATUS_RAS_BUSY__MASK				0x00000800
1961 #define A5XX_RBBM_STATUS_TSE_BUSY__MASK				0x00000400
1967 #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK			0x00000200
1973 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK		0x00000100
1979 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK			0x00000080
1985 #define A5XX_RBBM_STATUS_CP_BUSY__MASK				0x00000040
1991 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK			0x00000020
1997 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK			0x00000010
2003 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK			0x00000008
2009 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK			0x00000004
2015 #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK			0x00000002
2021 #define A5XX_RBBM_STATUS_HI_BUSY				0x00000001
2023 #define REG_A5XX_RBBM_STATUS3					0x00000530
2024 #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
2026 #define REG_A5XX_RBBM_INT_0_STATUS				0x000004e1
2028 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS			0x000004f0
2030 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS			0x000004f1
2032 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS			0x000004f3
2034 #define REG_A5XX_RBBM_AHB_ERROR_STATUS				0x000004f4
2036 #define REG_A5XX_RBBM_PERFCTR_CNTL				0x00000464
2038 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0				0x00000465
2040 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1				0x00000466
2042 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2				0x00000467
2044 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3				0x00000468
2046 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000469
2048 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x0000046a
2050 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000046f
2052 #define REG_A5XX_RBBM_AHB_ERROR					0x000004ed
2054 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC			0x00000504
2056 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER				0x00000505
2058 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0				0x00000506
2060 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1				0x00000507
2062 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2				0x00000508
2064 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3				0x00000509
2066 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4				0x0000050a
2068 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5				0x0000050b
2070 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR			0x0000050c
2072 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0			0x0000050d
2074 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1			0x0000050e
2076 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2			0x0000050f
2078 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3			0x00000510
2080 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4			0x00000511
2082 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0				0x00000512
2084 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1				0x00000513
2086 #define REG_A5XX_RBBM_ISDB_CNT					0x00000533
2088 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG			0x0000f000
2090 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
2092 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800
2094 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI		0x0000f801
2096 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802
2098 #define REG_A5XX_RBBM_SECVID_TSB_CNTL				0x0000f803
2100 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO			0x0000f804
2102 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI			0x0000f805
2104 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO			0x0000f806
2106 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI			0x0000f807
2108 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
2110 #define REG_A5XX_VSC_BIN_SIZE					0x00000bc2
2111 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
2112 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2117 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001fe00
2124 #define REG_A5XX_VSC_SIZE_ADDRESS_LO				0x00000bc3
2126 #define REG_A5XX_VSC_SIZE_ADDRESS_HI				0x00000bc4
2128 #define REG_A5XX_UNKNOWN_0BC5					0x00000bc5
2130 #define REG_A5XX_UNKNOWN_0BC6					0x00000bc6
2132 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_CONFIG()
2134 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_CONFIG_REG()
2135 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2136 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2141 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2147 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK			0x00f00000
2153 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK			0x0f000000
2160 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }  in REG_A5XX_VSC_PIPE_DATA_ADDRESS()
2162 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0;…  in REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO()
2164 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0;…  in REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI()
2166 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_DATA_LENGTH()
2168 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0;…  in REG_A5XX_VSC_PIPE_DATA_LENGTH_REG()
2170 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0				0x00000c60
2172 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1				0x00000c61
2174 #define REG_A5XX_VSC_RESOLVE_CNTL				0x00000cdd
2175 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE		0x80000000
2176 #define A5XX_VSC_RESOLVE_CNTL_X__MASK				0x00007fff
2177 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT				0
2182 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK				0x7fff0000
2189 #define REG_A5XX_GRAS_ADDR_MODE_CNTL				0x00000c81
2191 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0				0x00000c90
2193 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1				0x00000c91
2195 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2				0x00000c92
2197 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3				0x00000c93
2199 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0				0x00000c94
2201 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1				0x00000c95
2203 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2				0x00000c96
2205 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3				0x00000c97
2207 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0				0x00000c98
2209 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1				0x00000c99
2211 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2				0x00000c9a
2213 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3				0x00000c9b
2215 #define REG_A5XX_RB_DBG_ECO_CNTL				0x00000cc4
2217 #define REG_A5XX_RB_ADDR_MODE_CNTL				0x00000cc5
2219 #define REG_A5XX_RB_MODE_CNTL					0x00000cc6
2221 #define REG_A5XX_RB_CCU_CNTL					0x00000cc7
2223 #define REG_A5XX_RB_PERFCTR_RB_SEL_0				0x00000cd0
2225 #define REG_A5XX_RB_PERFCTR_RB_SEL_1				0x00000cd1
2227 #define REG_A5XX_RB_PERFCTR_RB_SEL_2				0x00000cd2
2229 #define REG_A5XX_RB_PERFCTR_RB_SEL_3				0x00000cd3
2231 #define REG_A5XX_RB_PERFCTR_RB_SEL_4				0x00000cd4
2233 #define REG_A5XX_RB_PERFCTR_RB_SEL_5				0x00000cd5
2235 #define REG_A5XX_RB_PERFCTR_RB_SEL_6				0x00000cd6
2237 #define REG_A5XX_RB_PERFCTR_RB_SEL_7				0x00000cd7
2239 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0				0x00000cd8
2241 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1				0x00000cd9
2243 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2				0x00000cda
2245 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3				0x00000cdb
2247 #define REG_A5XX_RB_POWERCTR_RB_SEL_0				0x00000ce0
2249 #define REG_A5XX_RB_POWERCTR_RB_SEL_1				0x00000ce1
2251 #define REG_A5XX_RB_POWERCTR_RB_SEL_2				0x00000ce2
2253 #define REG_A5XX_RB_POWERCTR_RB_SEL_3				0x00000ce3
2255 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0				0x00000ce4
2257 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1				0x00000ce5
2259 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0				0x00000cec
2261 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1				0x00000ced
2263 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2				0x00000cee
2265 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3				0x00000cef
2267 #define REG_A5XX_PC_DBG_ECO_CNTL				0x00000d00
2268 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI			0x00000100
2270 #define REG_A5XX_PC_ADDR_MODE_CNTL				0x00000d01
2272 #define REG_A5XX_PC_MODE_CNTL					0x00000d02
2274 #define REG_A5XX_PC_INDEX_BUF_LO				0x00000d04
2276 #define REG_A5XX_PC_INDEX_BUF_HI				0x00000d05
2278 #define REG_A5XX_PC_START_INDEX					0x00000d06
2280 #define REG_A5XX_PC_MAX_INDEX					0x00000d07
2282 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO				0x00000d08
2284 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI				0x00000d09
2286 #define REG_A5XX_PC_PERFCTR_PC_SEL_0				0x00000d10
2288 #define REG_A5XX_PC_PERFCTR_PC_SEL_1				0x00000d11
2290 #define REG_A5XX_PC_PERFCTR_PC_SEL_2				0x00000d12
2292 #define REG_A5XX_PC_PERFCTR_PC_SEL_3				0x00000d13
2294 #define REG_A5XX_PC_PERFCTR_PC_SEL_4				0x00000d14
2296 #define REG_A5XX_PC_PERFCTR_PC_SEL_5				0x00000d15
2298 #define REG_A5XX_PC_PERFCTR_PC_SEL_6				0x00000d16
2300 #define REG_A5XX_PC_PERFCTR_PC_SEL_7				0x00000d17
2302 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0			0x00000e00
2304 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1			0x00000e01
2306 #define REG_A5XX_HLSQ_DBG_ECO_CNTL				0x00000e04
2308 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL				0x00000e05
2310 #define REG_A5XX_HLSQ_MODE_CNTL					0x00000e06
2312 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x00000e10
2314 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x00000e11
2316 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x00000e12
2318 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x00000e13
2320 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x00000e14
2322 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x00000e15
2324 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6			0x00000e16
2326 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7			0x00000e17
2328 #define REG_A5XX_HLSQ_SPTP_RDSEL				0x00000f08
2330 #define REG_A5XX_HLSQ_DBG_READ_SEL				0x0000bc00
2332 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000a000
2334 #define REG_A5XX_VFD_ADDR_MODE_CNTL				0x00000e41
2336 #define REG_A5XX_VFD_MODE_CNTL					0x00000e42
2338 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0				0x00000e50
2340 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1				0x00000e51
2342 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2				0x00000e52
2344 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3				0x00000e53
2346 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4				0x00000e54
2348 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5				0x00000e55
2350 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6				0x00000e56
2352 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7				0x00000e57
2354 #define REG_A5XX_VPC_DBG_ECO_CNTL				0x00000e60
2355 #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS			0x00000400
2357 #define REG_A5XX_VPC_ADDR_MODE_CNTL				0x00000e61
2359 #define REG_A5XX_VPC_MODE_CNTL					0x00000e62
2360 #define A5XX_VPC_MODE_CNTL_BINNING_PASS				0x00000001
2362 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0				0x00000e64
2364 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1				0x00000e65
2366 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2				0x00000e66
2368 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3				0x00000e67
2370 #define REG_A5XX_UCHE_ADDR_MODE_CNTL				0x00000e80
2372 #define REG_A5XX_UCHE_MODE_CNTL					0x00000e81
2374 #define REG_A5XX_UCHE_SVM_CNTL					0x00000e82
2376 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO			0x00000e87
2378 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI			0x00000e88
2380 #define REG_A5XX_UCHE_TRAP_BASE_LO				0x00000e89
2382 #define REG_A5XX_UCHE_TRAP_BASE_HI				0x00000e8a
2384 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO				0x00000e8b
2386 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI				0x00000e8c
2388 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO				0x00000e8d
2390 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI				0x00000e8e
2392 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2				0x00000e8f
2394 #define REG_A5XX_UCHE_DBG_ECO_CNTL				0x00000e90
2396 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO			0x00000e91
2398 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI			0x00000e92
2400 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO			0x00000e93
2402 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI			0x00000e94
2404 #define REG_A5XX_UCHE_CACHE_INVALIDATE				0x00000e95
2406 #define REG_A5XX_UCHE_CACHE_WAYS				0x00000e96
2408 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000ea0
2410 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000ea1
2412 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000ea2
2414 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000ea3
2416 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000ea4
2418 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000ea5
2420 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000ea6
2422 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000ea7
2424 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0			0x00000ea8
2426 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1			0x00000ea9
2428 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2			0x00000eaa
2430 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3			0x00000eab
2432 #define REG_A5XX_UCHE_TRAP_LOG_LO				0x00000eb1
2434 #define REG_A5XX_UCHE_TRAP_LOG_HI				0x00000eb2
2436 #define REG_A5XX_SP_DBG_ECO_CNTL				0x00000ec0
2438 #define REG_A5XX_SP_ADDR_MODE_CNTL				0x00000ec1
2440 #define REG_A5XX_SP_MODE_CNTL					0x00000ec2
2442 #define REG_A5XX_SP_PERFCTR_SP_SEL_0				0x00000ed0
2444 #define REG_A5XX_SP_PERFCTR_SP_SEL_1				0x00000ed1
2446 #define REG_A5XX_SP_PERFCTR_SP_SEL_2				0x00000ed2
2448 #define REG_A5XX_SP_PERFCTR_SP_SEL_3				0x00000ed3
2450 #define REG_A5XX_SP_PERFCTR_SP_SEL_4				0x00000ed4
2452 #define REG_A5XX_SP_PERFCTR_SP_SEL_5				0x00000ed5
2454 #define REG_A5XX_SP_PERFCTR_SP_SEL_6				0x00000ed6
2456 #define REG_A5XX_SP_PERFCTR_SP_SEL_7				0x00000ed7
2458 #define REG_A5XX_SP_PERFCTR_SP_SEL_8				0x00000ed8
2460 #define REG_A5XX_SP_PERFCTR_SP_SEL_9				0x00000ed9
2462 #define REG_A5XX_SP_PERFCTR_SP_SEL_10				0x00000eda
2464 #define REG_A5XX_SP_PERFCTR_SP_SEL_11				0x00000edb
2466 #define REG_A5XX_SP_POWERCTR_SP_SEL_0				0x00000edc
2468 #define REG_A5XX_SP_POWERCTR_SP_SEL_1				0x00000edd
2470 #define REG_A5XX_SP_POWERCTR_SP_SEL_2				0x00000ede
2472 #define REG_A5XX_SP_POWERCTR_SP_SEL_3				0x00000edf
2474 #define REG_A5XX_TPL1_ADDR_MODE_CNTL				0x00000f01
2476 #define REG_A5XX_TPL1_MODE_CNTL					0x00000f02
2478 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0				0x00000f10
2480 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1				0x00000f11
2482 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2				0x00000f12
2484 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3				0x00000f13
2486 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4				0x00000f14
2488 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5				0x00000f15
2490 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6				0x00000f16
2492 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7				0x00000f17
2494 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0				0x00000f18
2496 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1				0x00000f19
2498 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2				0x00000f1a
2500 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3				0x00000f1b
2502 #define REG_A5XX_VBIF_VERSION					0x00003000
2504 #define REG_A5XX_VBIF_CLKON					0x00003001
2506 #define REG_A5XX_VBIF_ABIT_SORT					0x00003028
2508 #define REG_A5XX_VBIF_ABIT_SORT_CONF				0x00003029
2510 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
2512 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
2514 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
2516 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
2518 #define REG_A5XX_VBIF_XIN_HALT_CTRL0				0x00003080
2520 #define REG_A5XX_VBIF_XIN_HALT_CTRL1				0x00003081
2522 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
2524 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0				0x00003085
2526 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1				0x00003086
2528 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0				0x00003087
2530 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1				0x00003088
2532 #define REG_A5XX_VBIF_TEST_BUS_OUT				0x0000308c
2534 #define REG_A5XX_VBIF_PERF_CNT_EN0				0x000030c0
2536 #define REG_A5XX_VBIF_PERF_CNT_EN1				0x000030c1
2538 #define REG_A5XX_VBIF_PERF_CNT_EN2				0x000030c2
2540 #define REG_A5XX_VBIF_PERF_CNT_EN3				0x000030c3
2542 #define REG_A5XX_VBIF_PERF_CNT_CLR0				0x000030c8
2544 #define REG_A5XX_VBIF_PERF_CNT_CLR1				0x000030c9
2546 #define REG_A5XX_VBIF_PERF_CNT_CLR2				0x000030ca
2548 #define REG_A5XX_VBIF_PERF_CNT_CLR3				0x000030cb
2550 #define REG_A5XX_VBIF_PERF_CNT_SEL0				0x000030d0
2552 #define REG_A5XX_VBIF_PERF_CNT_SEL1				0x000030d1
2554 #define REG_A5XX_VBIF_PERF_CNT_SEL2				0x000030d2
2556 #define REG_A5XX_VBIF_PERF_CNT_SEL3				0x000030d3
2558 #define REG_A5XX_VBIF_PERF_CNT_LOW0				0x000030d8
2560 #define REG_A5XX_VBIF_PERF_CNT_LOW1				0x000030d9
2562 #define REG_A5XX_VBIF_PERF_CNT_LOW2				0x000030da
2564 #define REG_A5XX_VBIF_PERF_CNT_LOW3				0x000030db
2566 #define REG_A5XX_VBIF_PERF_CNT_HIGH0				0x000030e0
2568 #define REG_A5XX_VBIF_PERF_CNT_HIGH1				0x000030e1
2570 #define REG_A5XX_VBIF_PERF_CNT_HIGH2				0x000030e2
2572 #define REG_A5XX_VBIF_PERF_CNT_HIGH3				0x000030e3
2574 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
2576 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
2578 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
2580 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110
2582 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111
2584 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112
2586 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118
2588 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119
2590 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
2592 #define REG_A5XX_GPMU_INST_RAM_BASE				0x00008800
2594 #define REG_A5XX_GPMU_DATA_RAM_BASE				0x00009800
2596 #define REG_A5XX_GPMU_SP_POWER_CNTL				0x0000a881
2598 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL				0x0000a886
2600 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL				0x0000a887
2602 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS				0x0000a88b
2603 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON			0x00100000
2605 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS			0x0000a88d
2606 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON			0x00100000
2608 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY			0x0000a891
2610 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL			0x0000a892
2612 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST			0x0000a893
2614 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL			0x0000a894
2616 #define REG_A5XX_GPMU_WFI_CONFIG				0x0000a8c1
2618 #define REG_A5XX_GPMU_RBBM_INTR_INFO				0x0000a8d6
2620 #define REG_A5XX_GPMU_CM3_SYSRESET				0x0000a8d8
2622 #define REG_A5XX_GPMU_GENERAL_0					0x0000a8e0
2624 #define REG_A5XX_GPMU_GENERAL_1					0x0000a8e1
2626 #define REG_A5XX_SP_POWER_COUNTER_0_LO				0x0000a840
2628 #define REG_A5XX_SP_POWER_COUNTER_0_HI				0x0000a841
2630 #define REG_A5XX_SP_POWER_COUNTER_1_LO				0x0000a842
2632 #define REG_A5XX_SP_POWER_COUNTER_1_HI				0x0000a843
2634 #define REG_A5XX_SP_POWER_COUNTER_2_LO				0x0000a844
2636 #define REG_A5XX_SP_POWER_COUNTER_2_HI				0x0000a845
2638 #define REG_A5XX_SP_POWER_COUNTER_3_LO				0x0000a846
2640 #define REG_A5XX_SP_POWER_COUNTER_3_HI				0x0000a847
2642 #define REG_A5XX_TP_POWER_COUNTER_0_LO				0x0000a848
2644 #define REG_A5XX_TP_POWER_COUNTER_0_HI				0x0000a849
2646 #define REG_A5XX_TP_POWER_COUNTER_1_LO				0x0000a84a
2648 #define REG_A5XX_TP_POWER_COUNTER_1_HI				0x0000a84b
2650 #define REG_A5XX_TP_POWER_COUNTER_2_LO				0x0000a84c
2652 #define REG_A5XX_TP_POWER_COUNTER_2_HI				0x0000a84d
2654 #define REG_A5XX_TP_POWER_COUNTER_3_LO				0x0000a84e
2656 #define REG_A5XX_TP_POWER_COUNTER_3_HI				0x0000a84f
2658 #define REG_A5XX_RB_POWER_COUNTER_0_LO				0x0000a850
2660 #define REG_A5XX_RB_POWER_COUNTER_0_HI				0x0000a851
2662 #define REG_A5XX_RB_POWER_COUNTER_1_LO				0x0000a852
2664 #define REG_A5XX_RB_POWER_COUNTER_1_HI				0x0000a853
2666 #define REG_A5XX_RB_POWER_COUNTER_2_LO				0x0000a854
2668 #define REG_A5XX_RB_POWER_COUNTER_2_HI				0x0000a855
2670 #define REG_A5XX_RB_POWER_COUNTER_3_LO				0x0000a856
2672 #define REG_A5XX_RB_POWER_COUNTER_3_HI				0x0000a857
2674 #define REG_A5XX_CCU_POWER_COUNTER_0_LO				0x0000a858
2676 #define REG_A5XX_CCU_POWER_COUNTER_0_HI				0x0000a859
2678 #define REG_A5XX_CCU_POWER_COUNTER_1_LO				0x0000a85a
2680 #define REG_A5XX_CCU_POWER_COUNTER_1_HI				0x0000a85b
2682 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO			0x0000a85c
2684 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI			0x0000a85d
2686 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO			0x0000a85e
2688 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI			0x0000a85f
2690 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO			0x0000a860
2692 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI			0x0000a861
2694 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO			0x0000a862
2696 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI			0x0000a863
2698 #define REG_A5XX_CP_POWER_COUNTER_0_LO				0x0000a864
2700 #define REG_A5XX_CP_POWER_COUNTER_0_HI				0x0000a865
2702 #define REG_A5XX_CP_POWER_COUNTER_1_LO				0x0000a866
2704 #define REG_A5XX_CP_POWER_COUNTER_1_HI				0x0000a867
2706 #define REG_A5XX_CP_POWER_COUNTER_2_LO				0x0000a868
2708 #define REG_A5XX_CP_POWER_COUNTER_2_HI				0x0000a869
2710 #define REG_A5XX_CP_POWER_COUNTER_3_LO				0x0000a86a
2712 #define REG_A5XX_CP_POWER_COUNTER_3_HI				0x0000a86b
2714 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO			0x0000a86c
2716 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI			0x0000a86d
2718 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO			0x0000a86e
2720 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI			0x0000a86f
2722 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO			0x0000a870
2724 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI			0x0000a871
2726 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO			0x0000a872
2728 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI			0x0000a873
2730 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO			0x0000a874
2732 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI			0x0000a875
2734 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO			0x0000a876
2736 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI			0x0000a877
2738 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE			0x0000a878
2740 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO			0x0000a879
2742 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI			0x0000a87a
2744 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET			0x0000a87b
2746 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0			0x0000a87c
2748 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1			0x0000a87d
2750 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL			0x0000a8a3
2752 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL		0x0000a8a8
2754 #define REG_A5XX_GPMU_TEMP_SENSOR_ID				0x0000ac00
2756 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG			0x0000ac01
2758 #define REG_A5XX_GPMU_TEMP_VAL					0x0000ac02
2760 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD			0x0000ac03
2762 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS		0x0000ac05
2764 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK		0x0000ac06
2766 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1			0x0000ac40
2768 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3			0x0000ac41
2770 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1			0x0000ac42
2772 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3			0x0000ac43
2774 #define REG_A5XX_GPMU_BASE_LEAKAGE				0x0000ac46
2776 #define REG_A5XX_GPMU_GPMU_VOLTAGE				0x0000ac60
2778 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS			0x0000ac61
2780 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK			0x0000ac62
2782 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD			0x0000ac80
2784 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL			0x0000acc4
2786 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS			0x0000acc5
2788 #define REG_A5XX_GDPM_CONFIG1					0x0000b80c
2790 #define REG_A5XX_GDPM_CONFIG2					0x0000b80d
2792 #define REG_A5XX_GDPM_INT_EN					0x0000b80f
2794 #define REG_A5XX_GDPM_INT_MASK					0x0000b811
2796 #define REG_A5XX_GPMU_BEC_ENABLE				0x0000b9a0
2798 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS			0x0000c41a
2800 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0		0x0000c41d
2802 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2		0x0000c41f
2804 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4		0x0000c421
2806 #define REG_A5XX_GPU_CS_ENABLE_REG				0x0000c520
2808 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1		0x0000c557
2810 #define REG_A5XX_GRAS_CL_CNTL					0x0000e000
2811 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2813 #define REG_A5XX_GRAS_VS_CL_CNTL				0x0000e001
2814 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2815 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2820 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2827 #define REG_A5XX_UNKNOWN_E004					0x0000e004
2829 #define REG_A5XX_GRAS_CNTL					0x0000e005
2830 #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2831 #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2832 #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2833 #define A5XX_GRAS_CNTL_SIZE					0x00000008
2834 #define A5XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2841 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x0000e006
2842 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000003ff
2843 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
2848 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x000ffc00
2855 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0			0x0000e010
2856 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK			0xffffffff
2857 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT			0
2863 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0				0x0000e011
2864 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK			0xffffffff
2865 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT			0
2871 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0			0x0000e012
2872 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK			0xffffffff
2873 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT			0
2879 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0				0x0000e013
2880 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK			0xffffffff
2881 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT			0
2887 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0			0x0000e014
2888 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK			0xffffffff
2889 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT			0
2895 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0				0x0000e015
2896 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK			0xffffffff
2897 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT			0
2903 #define REG_A5XX_GRAS_SU_CNTL					0x0000e090
2904 #define A5XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
2905 #define A5XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
2906 #define A5XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
2907 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
2913 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2914 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE				0x00002000
2916 #define REG_A5XX_GRAS_SU_POINT_MINMAX				0x0000e091
2917 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
2918 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
2923 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
2930 #define REG_A5XX_GRAS_SU_POINT_SIZE				0x0000e092
2931 #define A5XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
2932 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT				0
2938 #define REG_A5XX_GRAS_SU_LAYERED				0x0000e093
2940 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL			0x0000e094
2941 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z		0x00000001
2942 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1			0x00000002
2944 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE			0x0000e095
2945 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
2946 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
2952 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET			0x0000e096
2953 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
2954 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
2960 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x0000e097
2961 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
2962 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
2968 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO			0x0000e098
2969 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
2970 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
2976 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL			0x0000e099
2978 #define REG_A5XX_GRAS_SC_CNTL					0x0000e0a0
2979 #define A5XX_GRAS_SC_CNTL_BINNING_PASS				0x00000001
2980 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED			0x00008000
2982 #define REG_A5XX_GRAS_SC_BIN_CNTL				0x0000e0a1
2984 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL				0x0000e0a2
2985 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK		0x00000003
2986 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT		0
2992 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL				0x0000e0a3
2993 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK		0x00000003
2994 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
2999 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE		0x00000004
3001 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL			0x0000e0a4
3003 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0			0x0000e0aa
3004 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
3005 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK		0x00007fff
3006 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT		0
3011 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK		0x7fff0000
3018 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0			0x0000e0ab
3019 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
3020 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK		0x00007fff
3021 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT		0
3026 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK		0x7fff0000
3033 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0			0x0000e0ca
3034 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
3035 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK		0x00007fff
3036 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT		0
3041 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK		0x7fff0000
3048 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0			0x0000e0cb
3049 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
3050 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK		0x00007fff
3051 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT		0
3056 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK		0x7fff0000
3063 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL			0x0000e0ea
3064 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3065 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
3066 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
3071 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
3078 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000e0eb
3079 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3080 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
3081 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
3086 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
3093 #define REG_A5XX_GRAS_LRZ_CNTL					0x0000e100
3094 #define A5XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
3095 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
3096 #define A5XX_GRAS_LRZ_CNTL_GREATER				0x00000004
3098 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO			0x0000e101
3100 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI			0x0000e102
3102 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH				0x0000e103
3103 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK			0xffffffff
3104 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT			0
3110 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO		0x0000e104
3112 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI		0x0000e105
3114 #define REG_A5XX_RB_CNTL					0x0000e140
3115 #define A5XX_RB_CNTL_WIDTH__MASK				0x000000ff
3116 #define A5XX_RB_CNTL_WIDTH__SHIFT				0
3121 #define A5XX_RB_CNTL_HEIGHT__MASK				0x0001fe00
3127 #define A5XX_RB_CNTL_BYPASS					0x00020000
3129 #define REG_A5XX_RB_RENDER_CNTL					0x0000e141
3130 #define A5XX_RB_RENDER_CNTL_BINNING_PASS			0x00000001
3131 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED			0x00000040
3132 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE			0x00000080
3133 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
3134 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2				0x00008000
3135 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
3141 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK			0xff000000
3148 #define REG_A5XX_RB_RAS_MSAA_CNTL				0x0000e142
3149 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
3150 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
3156 #define REG_A5XX_RB_DEST_MSAA_CNTL				0x0000e143
3157 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
3158 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
3163 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
3165 #define REG_A5XX_RB_RENDER_CONTROL0				0x0000e144
3166 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3167 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3168 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3169 #define A5XX_RB_RENDER_CONTROL0_SIZE				0x00000008
3170 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3177 #define REG_A5XX_RB_RENDER_CONTROL1				0x0000e145
3178 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
3179 #define A5XX_RB_RENDER_CONTROL1_FACENESS			0x00000002
3180 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000004
3182 #define REG_A5XX_RB_FS_OUTPUT_CNTL				0x0000e146
3183 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK			0x0000000f
3184 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT			0
3189 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z			0x00000020
3191 #define REG_A5XX_RB_RENDER_COMPONENTS				0x0000e147
3192 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
3193 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
3198 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
3204 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
3210 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
3216 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
3222 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
3228 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
3234 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
3241 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }  in REG_A5XX_RB_MRT()
3243 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }  in REG_A5XX_RB_MRT_CONTROL()
3244 #define A5XX_RB_MRT_CONTROL_BLEND				0x00000001
3245 #define A5XX_RB_MRT_CONTROL_BLEND2				0x00000002
3246 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
3247 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
3253 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
3260 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }  in REG_A5XX_RB_MRT_BLEND_CONTROL()
3261 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
3262 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
3267 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
3273 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
3279 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
3285 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
3291 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
3298 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }  in REG_A5XX_RB_MRT_BUF_INFO()
3299 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
3300 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
3305 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
3311 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK			0x00001800
3317 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
3323 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00008000
3325 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }  in REG_A5XX_RB_MRT_PITCH()
3326 #define A5XX_RB_MRT_PITCH__MASK					0xffffffff
3327 #define A5XX_RB_MRT_PITCH__SHIFT				0
3333 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }  in REG_A5XX_RB_MRT_ARRAY_PITCH()
3334 #define A5XX_RB_MRT_ARRAY_PITCH__MASK				0xffffffff
3335 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT				0
3341 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }  in REG_A5XX_RB_MRT_BASE_LO()
3343 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }  in REG_A5XX_RB_MRT_BASE_HI()
3345 #define REG_A5XX_RB_BLEND_RED					0x0000e1a0
3346 #define A5XX_RB_BLEND_RED_UINT__MASK				0x000000ff
3347 #define A5XX_RB_BLEND_RED_UINT__SHIFT				0
3352 #define A5XX_RB_BLEND_RED_SINT__MASK				0x0000ff00
3358 #define A5XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
3365 #define REG_A5XX_RB_BLEND_RED_F32				0x0000e1a1
3366 #define A5XX_RB_BLEND_RED_F32__MASK				0xffffffff
3367 #define A5XX_RB_BLEND_RED_F32__SHIFT				0
3373 #define REG_A5XX_RB_BLEND_GREEN					0x0000e1a2
3374 #define A5XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
3375 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT				0
3380 #define A5XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00
3386 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
3393 #define REG_A5XX_RB_BLEND_GREEN_F32				0x0000e1a3
3394 #define A5XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
3395 #define A5XX_RB_BLEND_GREEN_F32__SHIFT				0
3401 #define REG_A5XX_RB_BLEND_BLUE					0x0000e1a4
3402 #define A5XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
3403 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT				0
3408 #define A5XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00
3414 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
3421 #define REG_A5XX_RB_BLEND_BLUE_F32				0x0000e1a5
3422 #define A5XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
3423 #define A5XX_RB_BLEND_BLUE_F32__SHIFT				0
3429 #define REG_A5XX_RB_BLEND_ALPHA					0x0000e1a6
3430 #define A5XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
3431 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT				0
3436 #define A5XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00
3442 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
3449 #define REG_A5XX_RB_BLEND_ALPHA_F32				0x0000e1a7
3450 #define A5XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
3451 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT				0
3457 #define REG_A5XX_RB_ALPHA_CONTROL				0x0000e1a8
3458 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
3459 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
3464 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
3465 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
3472 #define REG_A5XX_RB_BLEND_CNTL					0x0000e1a9
3473 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
3474 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
3479 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3480 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3481 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
3488 #define REG_A5XX_RB_DEPTH_PLANE_CNTL				0x0000e1b0
3489 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z			0x00000001
3490 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1				0x00000002
3492 #define REG_A5XX_RB_DEPTH_CNTL					0x0000e1b1
3493 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE				0x00000001
3494 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
3495 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
3501 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000040
3503 #define REG_A5XX_RB_DEPTH_BUFFER_INFO				0x0000e1b2
3504 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
3505 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
3511 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO			0x0000e1b3
3513 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI			0x0000e1b4
3515 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH				0x0000e1b5
3516 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK			0xffffffff
3517 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
3523 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x0000e1b6
3524 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0xffffffff
3525 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
3531 #define REG_A5XX_RB_STENCIL_CONTROL				0x0000e1c0
3532 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
3533 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
3534 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
3535 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
3541 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
3547 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
3553 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
3559 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
3565 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
3571 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
3577 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
3584 #define REG_A5XX_RB_STENCIL_INFO				0x0000e1c1
3585 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
3587 #define REG_A5XX_RB_STENCIL_BASE_LO				0x0000e1c2
3589 #define REG_A5XX_RB_STENCIL_BASE_HI				0x0000e1c3
3591 #define REG_A5XX_RB_STENCIL_PITCH				0x0000e1c4
3592 #define A5XX_RB_STENCIL_PITCH__MASK				0xffffffff
3593 #define A5XX_RB_STENCIL_PITCH__SHIFT				0
3599 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH				0x0000e1c5
3600 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK			0xffffffff
3601 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT			0
3607 #define REG_A5XX_RB_STENCILREFMASK				0x0000e1c6
3608 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
3609 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
3614 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
3620 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
3627 #define REG_A5XX_RB_STENCILREFMASK_BF				0x0000e1c7
3628 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
3629 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
3634 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
3640 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
3647 #define REG_A5XX_RB_WINDOW_OFFSET				0x0000e1d0
3648 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
3649 #define A5XX_RB_WINDOW_OFFSET_X__MASK				0x00007fff
3650 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT				0
3655 #define A5XX_RB_WINDOW_OFFSET_Y__MASK				0x7fff0000
3662 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL			0x0000e1d1
3663 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
3665 #define REG_A5XX_RB_BLIT_CNTL					0x0000e210
3666 #define A5XX_RB_BLIT_CNTL_BUF__MASK				0x0000000f
3667 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT				0
3673 #define REG_A5XX_RB_RESOLVE_CNTL_1				0x0000e211
3674 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE		0x80000000
3675 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK				0x00007fff
3676 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT				0
3681 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK				0x7fff0000
3688 #define REG_A5XX_RB_RESOLVE_CNTL_2				0x0000e212
3689 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE		0x80000000
3690 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK				0x00007fff
3691 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT				0
3696 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK				0x7fff0000
3703 #define REG_A5XX_RB_RESOLVE_CNTL_3				0x0000e213
3704 #define A5XX_RB_RESOLVE_CNTL_3_TILED				0x00000001
3706 #define REG_A5XX_RB_BLIT_DST_LO					0x0000e214
3708 #define REG_A5XX_RB_BLIT_DST_HI					0x0000e215
3710 #define REG_A5XX_RB_BLIT_DST_PITCH				0x0000e216
3711 #define A5XX_RB_BLIT_DST_PITCH__MASK				0xffffffff
3712 #define A5XX_RB_BLIT_DST_PITCH__SHIFT				0
3718 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH			0x0000e217
3719 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0xffffffff
3720 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
3726 #define REG_A5XX_RB_CLEAR_COLOR_DW0				0x0000e218
3728 #define REG_A5XX_RB_CLEAR_COLOR_DW1				0x0000e219
3730 #define REG_A5XX_RB_CLEAR_COLOR_DW2				0x0000e21a
3732 #define REG_A5XX_RB_CLEAR_COLOR_DW3				0x0000e21b
3734 #define REG_A5XX_RB_CLEAR_CNTL					0x0000e21c
3735 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR				0x00000002
3736 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE				0x00000004
3737 #define A5XX_RB_CLEAR_CNTL_MASK__MASK				0x000000f0
3744 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO			0x0000e240
3746 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI			0x0000e241
3748 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x0000e242
3750 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }  in REG_A5XX_RB_MRT_FLAG_BUFFER()
3752 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO()
3754 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI()
3756 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0;…  in REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH()
3757 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK			0xffffffff
3758 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT			0
3764 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH()
3765 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK		0xffffffff
3766 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
3772 #define REG_A5XX_RB_BLIT_FLAG_DST_LO				0x0000e263
3774 #define REG_A5XX_RB_BLIT_FLAG_DST_HI				0x0000e264
3776 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH				0x0000e265
3777 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK			0xffffffff
3778 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT			0
3784 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH			0x0000e266
3785 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK			0xffffffff
3786 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT		0
3792 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO			0x0000e267
3794 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI			0x0000e268
3796 #define REG_A5XX_VPC_CNTL_0					0x0000e280
3797 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK			0x0000007f
3798 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT			0
3803 #define A5XX_VPC_CNTL_0_VARYING					0x00000800
3805 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }  in REG_A5XX_VPC_VARYING_INTERP()
3807 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }  in REG_A5XX_VPC_VARYING_INTERP_MODE()
3809 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }  in REG_A5XX_VPC_VARYING_PS_REPL()
3811 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0;…  in REG_A5XX_VPC_VARYING_PS_REPL_MODE()
3813 #define REG_A5XX_UNKNOWN_E292					0x0000e292
3815 #define REG_A5XX_UNKNOWN_E293					0x0000e293
3817 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }  in REG_A5XX_VPC_VAR()
3819 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }  in REG_A5XX_VPC_VAR_DISABLE()
3821 #define REG_A5XX_VPC_GS_SIV_CNTL				0x0000e298
3823 #define REG_A5XX_VPC_CLIP_CNTL					0x0000e29a
3824 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
3825 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT			0
3830 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
3836 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
3843 #define REG_A5XX_VPC_PACK					0x0000e29d
3844 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK			0x000000ff
3845 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT			0
3850 #define A5XX_VPC_PACK_PSIZELOC__MASK				0x0000ff00
3857 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL			0x0000e2a0
3859 #define REG_A5XX_VPC_SO_BUF_CNTL				0x0000e2a1
3860 #define A5XX_VPC_SO_BUF_CNTL_BUF0				0x00000001
3861 #define A5XX_VPC_SO_BUF_CNTL_BUF1				0x00000008
3862 #define A5XX_VPC_SO_BUF_CNTL_BUF2				0x00000040
3863 #define A5XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
3864 #define A5XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
3866 #define REG_A5XX_VPC_SO_OVERRIDE				0x0000e2a2
3867 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE				0x00000001
3869 #define REG_A5XX_VPC_SO_CNTL					0x0000e2a3
3870 #define A5XX_VPC_SO_CNTL_ENABLE					0x00010000
3872 #define REG_A5XX_VPC_SO_PROG					0x0000e2a4
3873 #define A5XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
3874 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT				0
3879 #define A5XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
3885 #define A5XX_VPC_SO_PROG_A_EN					0x00000800
3886 #define A5XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
3892 #define A5XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
3898 #define A5XX_VPC_SO_PROG_B_EN					0x00800000
3900 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }  in REG_A5XX_VPC_SO()
3902 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_BASE_LO()
3904 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_BASE_HI()
3906 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_SIZE()
3908 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }  in REG_A5XX_VPC_SO_NCOMP()
3910 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_OFFSET()
3912 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }  in REG_A5XX_VPC_SO_FLUSH_BASE_LO()
3914 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }  in REG_A5XX_VPC_SO_FLUSH_BASE_HI()
3916 #define REG_A5XX_PC_PRIMITIVE_CNTL				0x0000e384
3917 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK		0x0000007f
3918 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT		0
3923 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART		0x00000100
3924 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES			0x00000200
3925 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST		0x00000400
3927 #define REG_A5XX_PC_PRIM_VTX_CNTL				0x0000e385
3928 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE				0x00000800
3930 #define REG_A5XX_PC_RASTER_CNTL					0x0000e388
3931 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK		0x00000007
3932 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT		0
3937 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK		0x00000038
3943 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE			0x00000040
3945 #define REG_A5XX_PC_CLIP_CNTL					0x0000e389
3946 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
3947 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT			0
3953 #define REG_A5XX_PC_RESTART_INDEX				0x0000e38c
3955 #define REG_A5XX_PC_GS_LAYERED					0x0000e38d
3957 #define REG_A5XX_PC_GS_PARAM					0x0000e38e
3958 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK			0x000003ff
3959 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT			0
3964 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK			0x0000f800
3970 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK				0x01800000
3977 #define REG_A5XX_PC_HS_PARAM					0x0000e38f
3978 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK			0x0000003f
3979 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT			0
3984 #define A5XX_PC_HS_PARAM_SPACING__MASK				0x00600000
3990 #define A5XX_PC_HS_PARAM_CW					0x00800000
3991 #define A5XX_PC_HS_PARAM_CONNECTED				0x01000000
3993 #define REG_A5XX_PC_POWER_CNTL					0x0000e3b0
3995 #define REG_A5XX_VFD_CONTROL_0					0x0000e400
3996 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK				0x0000003f
3997 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT			0
4003 #define REG_A5XX_VFD_CONTROL_1					0x0000e401
4004 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
4005 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
4010 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
4016 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
4023 #define REG_A5XX_VFD_CONTROL_2					0x0000e402
4024 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK			0x000000ff
4025 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT			0
4031 #define REG_A5XX_VFD_CONTROL_3					0x0000e403
4032 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK			0x0000ff00
4038 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
4044 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
4051 #define REG_A5XX_VFD_CONTROL_4					0x0000e404
4053 #define REG_A5XX_VFD_CONTROL_5					0x0000e405
4055 #define REG_A5XX_VFD_INDEX_OFFSET				0x0000e408
4057 #define REG_A5XX_VFD_INSTANCE_START_OFFSET			0x0000e409
4059 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }  in REG_A5XX_VFD_FETCH()
4061 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }  in REG_A5XX_VFD_FETCH_BASE_LO()
4063 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }  in REG_A5XX_VFD_FETCH_BASE_HI()
4065 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }  in REG_A5XX_VFD_FETCH_SIZE()
4067 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }  in REG_A5XX_VFD_FETCH_STRIDE()
4069 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }  in REG_A5XX_VFD_DECODE()
4071 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }  in REG_A5XX_VFD_DECODE_INSTR()
4072 #define A5XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
4073 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT			0
4078 #define A5XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
4079 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
4085 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
4091 #define A5XX_VFD_DECODE_INSTR_UNK30				0x40000000
4092 #define A5XX_VFD_DECODE_INSTR_FLOAT				0x80000000
4094 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }  in REG_A5XX_VFD_DECODE_STEP_RATE()
4096 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }  in REG_A5XX_VFD_DEST_CNTL()
4098 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }  in REG_A5XX_VFD_DEST_CNTL_INSTR()
4099 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
4100 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
4105 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
4112 #define REG_A5XX_VFD_POWER_CNTL					0x0000e4f0
4114 #define REG_A5XX_SP_SP_CNTL					0x0000e580
4116 #define REG_A5XX_SP_VS_CONFIG					0x0000e584
4117 #define A5XX_SP_VS_CONFIG_ENABLED				0x00000001
4118 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4124 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4131 #define REG_A5XX_SP_FS_CONFIG					0x0000e585
4132 #define A5XX_SP_FS_CONFIG_ENABLED				0x00000001
4133 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4139 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4146 #define REG_A5XX_SP_HS_CONFIG					0x0000e586
4147 #define A5XX_SP_HS_CONFIG_ENABLED				0x00000001
4148 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4154 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4161 #define REG_A5XX_SP_DS_CONFIG					0x0000e587
4162 #define A5XX_SP_DS_CONFIG_ENABLED				0x00000001
4163 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4169 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4176 #define REG_A5XX_SP_GS_CONFIG					0x0000e588
4177 #define A5XX_SP_GS_CONFIG_ENABLED				0x00000001
4178 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4184 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4191 #define REG_A5XX_SP_CS_CONFIG					0x0000e589
4192 #define A5XX_SP_CS_CONFIG_ENABLED				0x00000001
4193 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4199 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4206 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST				0x0000e58a
4208 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST				0x0000e58b
4210 #define REG_A5XX_SP_VS_CTRL_REG0				0x0000e590
4211 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4217 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4223 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4229 #define A5XX_SP_VS_CTRL_REG0_VARYING				0x00010000
4230 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x00100000
4231 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4238 #define REG_A5XX_SP_PRIMITIVE_CNTL				0x0000e592
4239 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK			0x0000001f
4240 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT			0
4246 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }  in REG_A5XX_SP_VS_OUT()
4248 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }  in REG_A5XX_SP_VS_OUT_REG()
4249 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
4250 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
4255 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
4261 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
4267 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
4274 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }  in REG_A5XX_SP_VS_VPC_DST()
4276 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }  in REG_A5XX_SP_VS_VPC_DST_REG()
4277 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
4278 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
4283 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
4289 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
4295 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
4302 #define REG_A5XX_UNKNOWN_E5AB					0x0000e5ab
4304 #define REG_A5XX_SP_VS_OBJ_START_LO				0x0000e5ac
4306 #define REG_A5XX_SP_VS_OBJ_START_HI				0x0000e5ad
4308 #define REG_A5XX_SP_FS_CTRL_REG0				0x0000e5c0
4309 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4315 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4321 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4327 #define A5XX_SP_FS_CTRL_REG0_VARYING				0x00010000
4328 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00100000
4329 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4336 #define REG_A5XX_UNKNOWN_E5C2					0x0000e5c2
4338 #define REG_A5XX_SP_FS_OBJ_START_LO				0x0000e5c3
4340 #define REG_A5XX_SP_FS_OBJ_START_HI				0x0000e5c4
4342 #define REG_A5XX_SP_BLEND_CNTL					0x0000e5c9
4343 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
4344 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
4349 #define A5XX_SP_BLEND_CNTL_UNK8					0x00000100
4350 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
4352 #define REG_A5XX_SP_FS_OUTPUT_CNTL				0x0000e5ca
4353 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK			0x0000000f
4354 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT			0
4359 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK		0x00001fe0
4365 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK		0x001fe000
4372 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }  in REG_A5XX_SP_FS_OUTPUT()
4374 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }  in REG_A5XX_SP_FS_OUTPUT_REG()
4375 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
4376 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
4381 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100
4383 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }  in REG_A5XX_SP_FS_MRT()
4385 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }  in REG_A5XX_SP_FS_MRT_REG()
4386 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
4387 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
4392 #define A5XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
4393 #define A5XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
4394 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB				0x00000400
4396 #define REG_A5XX_UNKNOWN_E5DB					0x0000e5db
4398 #define REG_A5XX_SP_CS_CTRL_REG0				0x0000e5f0
4399 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4405 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4411 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4417 #define A5XX_SP_CS_CTRL_REG0_VARYING				0x00010000
4418 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x00100000
4419 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4426 #define REG_A5XX_UNKNOWN_E5F2					0x0000e5f2
4428 #define REG_A5XX_SP_CS_OBJ_START_LO				0x0000e5f3
4430 #define REG_A5XX_SP_CS_OBJ_START_HI				0x0000e5f4
4432 #define REG_A5XX_SP_HS_CTRL_REG0				0x0000e600
4433 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4439 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4445 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4451 #define A5XX_SP_HS_CTRL_REG0_VARYING				0x00010000
4452 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE			0x00100000
4453 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4460 #define REG_A5XX_UNKNOWN_E602					0x0000e602
4462 #define REG_A5XX_SP_HS_OBJ_START_LO				0x0000e603
4464 #define REG_A5XX_SP_HS_OBJ_START_HI				0x0000e604
4466 #define REG_A5XX_SP_DS_CTRL_REG0				0x0000e610
4467 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4473 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4479 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4485 #define A5XX_SP_DS_CTRL_REG0_VARYING				0x00010000
4486 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE			0x00100000
4487 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4494 #define REG_A5XX_UNKNOWN_E62B					0x0000e62b
4496 #define REG_A5XX_SP_DS_OBJ_START_LO				0x0000e62c
4498 #define REG_A5XX_SP_DS_OBJ_START_HI				0x0000e62d
4500 #define REG_A5XX_SP_GS_CTRL_REG0				0x0000e640
4501 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4507 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4513 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4519 #define A5XX_SP_GS_CTRL_REG0_VARYING				0x00010000
4520 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE			0x00100000
4521 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4528 #define REG_A5XX_UNKNOWN_E65B					0x0000e65b
4530 #define REG_A5XX_SP_GS_OBJ_START_LO				0x0000e65c
4532 #define REG_A5XX_SP_GS_OBJ_START_HI				0x0000e65d
4534 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL				0x0000e704
4535 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK		0x00000003
4536 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT		0
4542 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL				0x0000e705
4543 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK		0x00000003
4544 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
4549 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE		0x00000004
4551 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO		0x0000e706
4553 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI		0x0000e707
4555 #define REG_A5XX_TPL1_VS_TEX_COUNT				0x0000e700
4557 #define REG_A5XX_TPL1_HS_TEX_COUNT				0x0000e701
4559 #define REG_A5XX_TPL1_DS_TEX_COUNT				0x0000e702
4561 #define REG_A5XX_TPL1_GS_TEX_COUNT				0x0000e703
4563 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO				0x0000e722
4565 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI				0x0000e723
4567 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO				0x0000e724
4569 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI				0x0000e725
4571 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO				0x0000e726
4573 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI				0x0000e727
4575 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO				0x0000e728
4577 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI				0x0000e729
4579 #define REG_A5XX_TPL1_VS_TEX_CONST_LO				0x0000e72a
4581 #define REG_A5XX_TPL1_VS_TEX_CONST_HI				0x0000e72b
4583 #define REG_A5XX_TPL1_HS_TEX_CONST_LO				0x0000e72c
4585 #define REG_A5XX_TPL1_HS_TEX_CONST_HI				0x0000e72d
4587 #define REG_A5XX_TPL1_DS_TEX_CONST_LO				0x0000e72e
4589 #define REG_A5XX_TPL1_DS_TEX_CONST_HI				0x0000e72f
4591 #define REG_A5XX_TPL1_GS_TEX_CONST_LO				0x0000e730
4593 #define REG_A5XX_TPL1_GS_TEX_CONST_HI				0x0000e731
4595 #define REG_A5XX_TPL1_FS_TEX_COUNT				0x0000e750
4597 #define REG_A5XX_TPL1_CS_TEX_COUNT				0x0000e751
4599 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO				0x0000e75a
4601 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI				0x0000e75b
4603 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO				0x0000e75c
4605 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI				0x0000e75d
4607 #define REG_A5XX_TPL1_FS_TEX_CONST_LO				0x0000e75e
4609 #define REG_A5XX_TPL1_FS_TEX_CONST_HI				0x0000e75f
4611 #define REG_A5XX_TPL1_CS_TEX_CONST_LO				0x0000e760
4613 #define REG_A5XX_TPL1_CS_TEX_CONST_HI				0x0000e761
4615 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL			0x0000e764
4617 #define REG_A5XX_HLSQ_CONTROL_0_REG				0x0000e784
4618 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000001
4619 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT		0
4624 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK		0x00000004
4631 #define REG_A5XX_HLSQ_CONTROL_1_REG				0x0000e785
4632 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK	0x0000003f
4633 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT	0
4639 #define REG_A5XX_HLSQ_CONTROL_2_REG				0x0000e786
4640 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
4641 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
4646 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
4652 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
4658 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
4665 #define REG_A5XX_HLSQ_CONTROL_3_REG				0x0000e787
4666 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
4667 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
4672 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
4678 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
4684 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
4691 #define REG_A5XX_HLSQ_CONTROL_4_REG				0x0000e788
4692 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
4693 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
4698 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
4704 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
4710 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
4717 #define REG_A5XX_HLSQ_UPDATE_CNTL				0x0000e78a
4719 #define REG_A5XX_HLSQ_VS_CONFIG					0x0000e78b
4720 #define A5XX_HLSQ_VS_CONFIG_ENABLED				0x00000001
4721 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4727 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4734 #define REG_A5XX_HLSQ_FS_CONFIG					0x0000e78c
4735 #define A5XX_HLSQ_FS_CONFIG_ENABLED				0x00000001
4736 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4742 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4749 #define REG_A5XX_HLSQ_HS_CONFIG					0x0000e78d
4750 #define A5XX_HLSQ_HS_CONFIG_ENABLED				0x00000001
4751 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4757 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4764 #define REG_A5XX_HLSQ_DS_CONFIG					0x0000e78e
4765 #define A5XX_HLSQ_DS_CONFIG_ENABLED				0x00000001
4766 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4772 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4779 #define REG_A5XX_HLSQ_GS_CONFIG					0x0000e78f
4780 #define A5XX_HLSQ_GS_CONFIG_ENABLED				0x00000001
4781 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4787 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4794 #define REG_A5XX_HLSQ_CS_CONFIG					0x0000e790
4795 #define A5XX_HLSQ_CS_CONFIG_ENABLED				0x00000001
4796 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4802 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4809 #define REG_A5XX_HLSQ_VS_CNTL					0x0000e791
4810 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE				0x00000001
4811 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK			0xfffffffe
4818 #define REG_A5XX_HLSQ_FS_CNTL					0x0000e792
4819 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE				0x00000001
4820 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK			0xfffffffe
4827 #define REG_A5XX_HLSQ_HS_CNTL					0x0000e793
4828 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE				0x00000001
4829 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK			0xfffffffe
4836 #define REG_A5XX_HLSQ_DS_CNTL					0x0000e794
4837 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE				0x00000001
4838 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK			0xfffffffe
4845 #define REG_A5XX_HLSQ_GS_CNTL					0x0000e795
4846 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE				0x00000001
4847 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK			0xfffffffe
4854 #define REG_A5XX_HLSQ_CS_CNTL					0x0000e796
4855 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE				0x00000001
4856 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK			0xfffffffe
4863 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X				0x0000e7b9
4865 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000e7ba
4867 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000e7bb
4869 #define REG_A5XX_HLSQ_CS_NDRANGE_0				0x0000e7b0
4870 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
4871 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
4876 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
4882 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
4888 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
4895 #define REG_A5XX_HLSQ_CS_NDRANGE_1				0x0000e7b1
4896 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
4897 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
4903 #define REG_A5XX_HLSQ_CS_NDRANGE_2				0x0000e7b2
4904 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
4905 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
4911 #define REG_A5XX_HLSQ_CS_NDRANGE_3				0x0000e7b3
4912 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
4913 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
4919 #define REG_A5XX_HLSQ_CS_NDRANGE_4				0x0000e7b4
4920 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
4921 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
4927 #define REG_A5XX_HLSQ_CS_NDRANGE_5				0x0000e7b5
4928 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
4929 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
4935 #define REG_A5XX_HLSQ_CS_NDRANGE_6				0x0000e7b6
4936 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
4937 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
4943 #define REG_A5XX_HLSQ_CS_CNTL_0					0x0000e7b7
4944 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
4945 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
4950 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK				0x0000ff00
4956 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK				0x00ff0000
4962 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
4969 #define REG_A5XX_HLSQ_CS_CNTL_1					0x0000e7b8
4971 #define REG_A5XX_UNKNOWN_E7C0					0x0000e7c0
4973 #define REG_A5XX_HLSQ_VS_CONSTLEN				0x0000e7c3
4975 #define REG_A5XX_HLSQ_VS_INSTRLEN				0x0000e7c4
4977 #define REG_A5XX_UNKNOWN_E7C5					0x0000e7c5
4979 #define REG_A5XX_HLSQ_HS_CONSTLEN				0x0000e7c8
4981 #define REG_A5XX_HLSQ_HS_INSTRLEN				0x0000e7c9
4983 #define REG_A5XX_UNKNOWN_E7CA					0x0000e7ca
4985 #define REG_A5XX_HLSQ_DS_CONSTLEN				0x0000e7cd
4987 #define REG_A5XX_HLSQ_DS_INSTRLEN				0x0000e7ce
4989 #define REG_A5XX_UNKNOWN_E7CF					0x0000e7cf
4991 #define REG_A5XX_HLSQ_GS_CONSTLEN				0x0000e7d2
4993 #define REG_A5XX_HLSQ_GS_INSTRLEN				0x0000e7d3
4995 #define REG_A5XX_UNKNOWN_E7D4					0x0000e7d4
4997 #define REG_A5XX_HLSQ_FS_CONSTLEN				0x0000e7d7
4999 #define REG_A5XX_HLSQ_FS_INSTRLEN				0x0000e7d8
5001 #define REG_A5XX_UNKNOWN_E7D9					0x0000e7d9
5003 #define REG_A5XX_HLSQ_CS_CONSTLEN				0x0000e7dc
5005 #define REG_A5XX_HLSQ_CS_INSTRLEN				0x0000e7dd
5007 #define REG_A5XX_RB_2D_BLIT_CNTL				0x00002100
5009 #define REG_A5XX_RB_2D_SRC_SOLID_DW0				0x00002101
5011 #define REG_A5XX_RB_2D_SRC_SOLID_DW1				0x00002102
5013 #define REG_A5XX_RB_2D_SRC_SOLID_DW2				0x00002103
5015 #define REG_A5XX_RB_2D_SRC_SOLID_DW3				0x00002104
5017 #define REG_A5XX_RB_2D_SRC_INFO					0x00002107
5018 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK			0x000000ff
5019 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT			0
5024 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
5030 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
5036 #define A5XX_RB_2D_SRC_INFO_FLAGS				0x00001000
5038 #define REG_A5XX_RB_2D_SRC_LO					0x00002108
5040 #define REG_A5XX_RB_2D_SRC_HI					0x00002109
5042 #define REG_A5XX_RB_2D_SRC_SIZE					0x0000210a
5043 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK				0x0000ffff
5044 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT			0
5049 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK			0xffff0000
5056 #define REG_A5XX_RB_2D_DST_INFO					0x00002110
5057 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
5058 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
5063 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
5069 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
5075 #define A5XX_RB_2D_DST_INFO_FLAGS				0x00001000
5077 #define REG_A5XX_RB_2D_DST_LO					0x00002111
5079 #define REG_A5XX_RB_2D_DST_HI					0x00002112
5081 #define REG_A5XX_RB_2D_DST_SIZE					0x00002113
5082 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK				0x0000ffff
5083 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT			0
5088 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK			0xffff0000
5095 #define REG_A5XX_RB_2D_SRC_FLAGS_LO				0x00002140
5097 #define REG_A5XX_RB_2D_SRC_FLAGS_HI				0x00002141
5099 #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH				0x00002142
5100 #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK			0xffffffff
5101 #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT			0
5107 #define REG_A5XX_RB_2D_DST_FLAGS_LO				0x00002143
5109 #define REG_A5XX_RB_2D_DST_FLAGS_HI				0x00002144
5111 #define REG_A5XX_RB_2D_DST_FLAGS_PITCH				0x00002145
5112 #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK			0xffffffff
5113 #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
5119 #define REG_A5XX_GRAS_2D_BLIT_CNTL				0x00002180
5121 #define REG_A5XX_GRAS_2D_SRC_INFO				0x00002181
5122 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
5123 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
5128 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
5134 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
5140 #define A5XX_GRAS_2D_SRC_INFO_FLAGS				0x00001000
5142 #define REG_A5XX_GRAS_2D_DST_INFO				0x00002182
5143 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK		0x000000ff
5144 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT		0
5149 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK			0x00000300
5155 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
5161 #define A5XX_GRAS_2D_DST_INFO_FLAGS				0x00001000
5163 #define REG_A5XX_UNKNOWN_2100					0x00002100
5165 #define REG_A5XX_UNKNOWN_2180					0x00002180
5167 #define REG_A5XX_UNKNOWN_2184					0x00002184
5169 #define REG_A5XX_TEX_SAMP_0					0x00000000
5170 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
5171 #define A5XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
5177 #define A5XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
5183 #define A5XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
5189 #define A5XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
5195 #define A5XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
5201 #define A5XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
5207 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
5214 #define REG_A5XX_TEX_SAMP_1					0x00000001
5215 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
5221 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
5222 #define A5XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
5223 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
5224 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
5230 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
5237 #define REG_A5XX_TEX_SAMP_2					0x00000002
5238 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
5245 #define REG_A5XX_TEX_SAMP_3					0x00000003
5247 #define REG_A5XX_TEX_CONST_0					0x00000000
5248 #define A5XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
5249 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT			0
5254 #define A5XX_TEX_CONST_0_SRGB					0x00000004
5255 #define A5XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
5261 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
5267 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
5273 #define A5XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
5279 #define A5XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
5285 #define A5XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
5291 #define A5XX_TEX_CONST_0_FMT__MASK				0x3fc00000
5297 #define A5XX_TEX_CONST_0_SWAP__MASK				0xc0000000
5304 #define REG_A5XX_TEX_CONST_1					0x00000001
5305 #define A5XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
5306 #define A5XX_TEX_CONST_1_WIDTH__SHIFT				0
5311 #define A5XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
5318 #define REG_A5XX_TEX_CONST_2					0x00000002
5319 #define A5XX_TEX_CONST_2_UNK4					0x00000010
5320 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
5321 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
5326 #define A5XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
5332 #define A5XX_TEX_CONST_2_TYPE__MASK				0x60000000
5338 #define A5XX_TEX_CONST_2_UNK31					0x80000000
5340 #define REG_A5XX_TEX_CONST_3					0x00000003
5341 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
5342 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
5347 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
5353 #define A5XX_TEX_CONST_3_TILE_ALL				0x08000000
5354 #define A5XX_TEX_CONST_3_FLAG					0x10000000
5356 #define REG_A5XX_TEX_CONST_4					0x00000004
5357 #define A5XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
5364 #define REG_A5XX_TEX_CONST_5					0x00000005
5365 #define A5XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
5366 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT				0
5371 #define A5XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
5378 #define REG_A5XX_TEX_CONST_6					0x00000006
5380 #define REG_A5XX_TEX_CONST_7					0x00000007
5382 #define REG_A5XX_TEX_CONST_8					0x00000008
5384 #define REG_A5XX_TEX_CONST_9					0x00000009
5386 #define REG_A5XX_TEX_CONST_10					0x0000000a
5388 #define REG_A5XX_TEX_CONST_11					0x0000000b
5390 #define REG_A5XX_SSBO_0_0					0x00000000
5391 #define A5XX_SSBO_0_0_BASE_LO__MASK				0xffffffe0
5398 #define REG_A5XX_SSBO_0_1					0x00000001
5399 #define A5XX_SSBO_0_1_PITCH__MASK				0x003fffff
5400 #define A5XX_SSBO_0_1_PITCH__SHIFT				0
5406 #define REG_A5XX_SSBO_0_2					0x00000002
5407 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK				0x03fff000
5414 #define REG_A5XX_SSBO_0_3					0x00000003
5415 #define A5XX_SSBO_0_3_CPP__MASK					0x0000003f
5416 #define A5XX_SSBO_0_3_CPP__SHIFT				0
5422 #define REG_A5XX_SSBO_1_0					0x00000000
5423 #define A5XX_SSBO_1_0_FMT__MASK					0x0000ff00
5429 #define A5XX_SSBO_1_0_WIDTH__MASK				0xffff0000
5436 #define REG_A5XX_SSBO_1_1					0x00000001
5437 #define A5XX_SSBO_1_1_HEIGHT__MASK				0x0000ffff
5438 #define A5XX_SSBO_1_1_HEIGHT__SHIFT				0
5443 #define A5XX_SSBO_1_1_DEPTH__MASK				0xffff0000
5450 #define REG_A5XX_SSBO_2_0					0x00000000
5451 #define A5XX_SSBO_2_0_BASE_LO__MASK				0xffffffff
5452 #define A5XX_SSBO_2_0_BASE_LO__SHIFT				0
5458 #define REG_A5XX_SSBO_2_1					0x00000001
5459 #define A5XX_SSBO_2_1_BASE_HI__MASK				0xffffffff
5460 #define A5XX_SSBO_2_1_BASE_HI__SHIFT				0
5466 #define REG_A5XX_UBO_0						0x00000000
5467 #define A5XX_UBO_0_BASE_LO__MASK				0xffffffff
5468 #define A5XX_UBO_0_BASE_LO__SHIFT				0
5474 #define REG_A5XX_UBO_1						0x00000001
5475 #define A5XX_UBO_1_BASE_HI__MASK				0x0001ffff
5476 #define A5XX_UBO_1_BASE_HI__SHIFT				0