1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
8 /* The MCDE internal clock dividers for FIFO A and B */
19 	struct mcde *mcde = cdiv->mcde;  in mcde_clk_div_enable()
22 	spin_lock(&mcde->fifo_crx1_lock);  in mcde_clk_div_enable()
23 	val = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
25 	 * Select the PLL72 (LCD) clock as parent  in mcde_clk_div_enable()
30 	/* Internal clock */  in mcde_clk_div_enable()
35 	val |= cdiv->cr_div;  in mcde_clk_div_enable()
37 	writel(val, mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
38 	spin_unlock(&mcde->fifo_crx1_lock);  in mcde_clk_div_enable()
46 	int best_div = 1, div;  in mcde_clk_div_choose_div()  local
50 	int max_div = (1 << MCDE_CRX1_PCD_BITS) - 1;  in mcde_clk_div_choose_div()
52 	for (div = 1; div < max_div; div++) {  in mcde_clk_div_choose_div()
56 			this_prate = clk_hw_round_rate(parent, rate * div);  in mcde_clk_div_choose_div()
59 		div_rate = DIV_ROUND_UP_ULL(this_prate, div);  in mcde_clk_div_choose_div()
60 		diff = abs(rate - div_rate);  in mcde_clk_div_choose_div()
63 			best_div = div;  in mcde_clk_div_choose_div()
76 	int div = mcde_clk_div_choose_div(hw, rate, prate, true);  in mcde_clk_div_round_rate()  local
78 	return DIV_ROUND_UP_ULL(*prate, div);  in mcde_clk_div_round_rate()
85 	struct mcde *mcde = cdiv->mcde;  in mcde_clk_div_recalc_rate()
87 	int div;  in mcde_clk_div_recalc_rate()  local
94 	if (!regulator_is_enabled(mcde->epod))  in mcde_clk_div_recalc_rate()
97 	cr = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_recalc_rate()
102 	div = cr & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_recalc_rate()
103 	div += 2;  in mcde_clk_div_recalc_rate()
105 	return DIV_ROUND_UP_ULL(prate, div);  in mcde_clk_div_recalc_rate()
112 	int div = mcde_clk_div_choose_div(hw, rate, &prate, false);  in mcde_clk_div_set_rate()  local
119 	if (div == 1) {  in mcde_clk_div_set_rate()
120 		/* Bypass clock divider */  in mcde_clk_div_set_rate()
123 		div -= 2;  in mcde_clk_div_set_rate()
124 		cr |= div & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_set_rate()
126 	cdiv->cr_div = cr;  in mcde_clk_div_set_rate()
140 	struct device *dev = mcde->dev;  in mcde_init_clock_divider()
160 	spin_lock_init(&mcde->fifo_crx1_lock);  in mcde_init_clock_divider()
161 	parent_name = __clk_get_name(mcde->lcd_clk);  in mcde_init_clock_divider()
166 		return -ENOMEM;  in mcde_init_clock_divider()
169 		return -ENOMEM;  in mcde_init_clock_divider()
171 	fifoa->mcde = mcde;  in mcde_init_clock_divider()
172 	fifoa->cr = MCDE_CRA1;  in mcde_init_clock_divider()
173 	fifoa->hw.init = &fifoa_init;  in mcde_init_clock_divider()
174 	ret = devm_clk_hw_register(dev, &fifoa->hw);  in mcde_init_clock_divider()
176 		dev_err(dev, "error registering FIFO A clock divider\n");  in mcde_init_clock_divider()
179 	mcde->fifoa_clk = fifoa->hw.clk;  in mcde_init_clock_divider()
181 	fifob->mcde = mcde;  in mcde_init_clock_divider()
182 	fifob->cr = MCDE_CRB1;  in mcde_init_clock_divider()
183 	fifob->hw.init = &fifob_init;  in mcde_init_clock_divider()
184 	ret = devm_clk_hw_register(dev, &fifob->hw);  in mcde_init_clock_divider()
186 		dev_err(dev, "error registering FIFO B clock divider\n");  in mcde_init_clock_divider()
189 	mcde->fifob_clk = fifob->hw.clk;  in mcde_init_clock_divider()