Lines Matching +full:charge +full:- +full:ctrl +full:- +full:value
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
177 clk_disable_unprepare(kmb_dsi->clk_mipi); in kmb_dsi_clk_disable()
178 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_disable()
179 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_disable()
185 mipi_dsi_host_unregister(kmb_dsi->host); in kmb_dsi_host_unregister()
224 return -ENOMEM; in kmb_dsi_host_bridge_init()
226 dsi_host->ops = &kmb_dsi_host_ops; in kmb_dsi_host_bridge_init()
232 return -ENOMEM; in kmb_dsi_host_bridge_init()
236 dsi_host->dev = dev; in kmb_dsi_host_bridge_init()
241 dsi_out = of_graph_get_endpoint_by_regs(dev->of_node, 0, 1); in kmb_dsi_host_bridge_init()
244 return -EINVAL; in kmb_dsi_host_bridge_init()
250 return -EINVAL; in kmb_dsi_host_bridge_init()
258 return -EPROBE_DEFER; in kmb_dsi_host_bridge_init()
283 return -EINVAL; in mipi_get_datatype_params()
303 return -EINVAL; in mipi_get_datatype_params()
320 return -EINVAL; in mipi_get_datatype_params()
339 return -EINVAL; in mipi_get_datatype_params()
363 return -EINVAL; in mipi_get_datatype_params()
395 cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; in mipi_tx_fg_section_cfg_regs()
398 cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) in mipi_tx_fg_section_cfg_regs()
402 cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK) in mipi_tx_fg_section_cfg_regs()
406 cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) in mipi_tx_fg_section_cfg_regs()
408 if (ph_cfg->dma_packed) in mipi_tx_fg_section_cfg_regs()
411 dev_dbg(kmb_dsi->dev, in mipi_tx_fg_section_cfg_regs()
412 "ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", in mipi_tx_fg_section_cfg_regs()
413 ctrl_no, frame_id, section, cfg, ph_cfg->dma_packed); in mipi_tx_fg_section_cfg_regs()
423 * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 in mipi_tx_fg_section_cfg_regs()
424 * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 in mipi_tx_fg_section_cfg_regs()
431 dev_dbg(kmb_dsi->dev, in mipi_tx_fg_section_cfg_regs()
433 ph_cfg->wc); in mipi_tx_fg_section_cfg_regs()
451 ret = mipi_get_datatype_params(frame_scfg->data_type, in mipi_tx_fg_section_cfg()
452 frame_scfg->data_mode, in mipi_tx_fg_section_cfg()
460 if (frame_scfg->width_pixels % in mipi_tx_fg_section_cfg()
462 return -EINVAL; in mipi_tx_fg_section_cfg()
464 *wc = compute_wc(frame_scfg->width_pixels, in mipi_tx_fg_section_cfg()
470 ph_cfg.data_mode = frame_scfg->data_mode; in mipi_tx_fg_section_cfg()
471 ph_cfg.data_type = frame_scfg->data_type; in mipi_tx_fg_section_cfg()
472 ph_cfg.dma_packed = frame_scfg->dma_packed; in mipi_tx_fg_section_cfg()
476 frame_scfg->height_lines, in mipi_tx_fg_section_cfg()
499 if (kmb_dsi->sys_clk_mhz == SYSCLK_500) { in mipi_tx_fg_cfg_regs()
500 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW; in mipi_tx_fg_cfg_regs()
503 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI; in mipi_tx_fg_cfg_regs()
506 /* PPL-Pixel Packing Layer, LLP-Low Level Protocol in mipi_tx_fg_cfg_regs()
509 * on LLP Tx clock from the D-PHY - BYTE clock in mipi_tx_fg_cfg_regs()
513 ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / in mipi_tx_fg_cfg_regs()
514 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
516 dev_dbg(kmb_dsi->dev, "ppl_llp_ratio=%d\n", ppl_llp_ratio); in mipi_tx_fg_cfg_regs()
517 dev_dbg(kmb_dsi->dev, "bpp=%d sysclk=%d lane-rate=%d active-lanes=%d\n", in mipi_tx_fg_cfg_regs()
518 fg_cfg->bpp, sysclk, fg_cfg->lane_rate_mbps, in mipi_tx_fg_cfg_regs()
519 fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
523 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->v_active); in mipi_tx_fg_cfg_regs()
527 * channels 0-3) in mipi_tx_fg_cfg_regs()
528 * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 in mipi_tx_fg_cfg_regs()
529 * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 in mipi_tx_fg_cfg_regs()
533 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->vsync_width); in mipi_tx_fg_cfg_regs()
537 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_backporch); in mipi_tx_fg_cfg_regs()
541 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_frontporch); in mipi_tx_fg_cfg_regs()
545 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_active); in mipi_tx_fg_cfg_regs()
550 (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
555 (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
560 (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
566 val = (fg_cfg->h_active * sysclk * 1000) / in mipi_tx_fg_cfg_regs()
567 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
573 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
577 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
582 fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
596 if (fg_cfg->sections[i]) in mipi_tx_fg_cfg()
597 fg_num_lines += fg_cfg->sections[i]->height_lines; in mipi_tx_fg_cfg()
602 fg_t_cfg.hsync_width = fg_cfg->hsync_width; in mipi_tx_fg_cfg()
603 fg_t_cfg.h_backporch = fg_cfg->h_backporch; in mipi_tx_fg_cfg()
604 fg_t_cfg.h_frontporch = fg_cfg->h_frontporch; in mipi_tx_fg_cfg()
606 fg_t_cfg.vsync_width = fg_cfg->vsync_width; in mipi_tx_fg_cfg()
607 fg_t_cfg.v_backporch = fg_cfg->v_backporch; in mipi_tx_fg_cfg()
608 fg_t_cfg.v_frontporch = fg_cfg->v_frontporch; in mipi_tx_fg_cfg()
631 MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; in mipi_tx_multichannel_fifo_cfg()
633 /* MC fifo size for virtual channels 0-3 in mipi_tx_multichannel_fifo_cfg()
634 * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 in mipi_tx_multichannel_fifo_cfg()
635 * REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 in mipi_tx_multichannel_fifo_cfg()
651 u32 sync_cfg = 0, ctrl = 0, fg_en; in mipi_tx_ctrl_cfg() local
655 if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) in mipi_tx_ctrl_cfg()
657 if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) in mipi_tx_ctrl_cfg()
659 if (ctrl_cfg->tx_ctrl_cfg.line_counter_active) in mipi_tx_ctrl_cfg()
661 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking) in mipi_tx_ctrl_cfg()
663 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) in mipi_tx_ctrl_cfg()
665 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) in mipi_tx_ctrl_cfg()
667 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) in mipi_tx_ctrl_cfg()
669 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn) in mipi_tx_ctrl_cfg()
671 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line) in mipi_tx_ctrl_cfg()
673 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) in mipi_tx_ctrl_cfg()
680 if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) in mipi_tx_ctrl_cfg()
682 if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) in mipi_tx_ctrl_cfg()
685 dev_dbg(kmb_dsi->dev, "sync_cfg=%d fg_en=%d\n", sync_cfg, fg_en); in mipi_tx_ctrl_cfg()
690 ctrl = HS_CTRL_EN | TX_SOURCE; in mipi_tx_ctrl_cfg()
691 ctrl |= LCD_VC(fg_id); in mipi_tx_ctrl_cfg()
692 ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); in mipi_tx_ctrl_cfg()
693 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) in mipi_tx_ctrl_cfg()
694 ctrl |= DSI_EOTP_EN; in mipi_tx_ctrl_cfg()
695 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) in mipi_tx_ctrl_cfg()
696 ctrl |= DSI_CMD_HFP_EN; in mipi_tx_ctrl_cfg()
699 ctrl |= HSEXIT_CNT(0x43); in mipi_tx_ctrl_cfg()
702 kmb_write_mipi(kmb_dsi, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); in mipi_tx_ctrl_cfg()
724 frame = ctrl_cfg->tx_ctrl_cfg.frames[frame_id]; in mipi_tx_init_cntrl()
731 /* TODO - assume there is only one valid section in a frame, in mipi_tx_init_cntrl()
735 if (!frame->sections[sect]) in mipi_tx_init_cntrl()
739 frame->sections[sect], in mipi_tx_init_cntrl()
747 mipi_tx_fg_cfg(kmb_dsi, frame_id, ctrl_cfg->active_lanes, in mipi_tx_init_cntrl()
749 ctrl_cfg->lane_rate_mbps, frame); in mipi_tx_init_cntrl()
760 return -EINVAL; in mipi_tx_init_cntrl()
761 /* Multi-Channel FIFO Configuration */ in mipi_tx_init_cntrl()
762 mipi_tx_multichannel_fifo_cfg(kmb_dsi, ctrl_cfg->active_lanes, frame_id); in mipi_tx_init_cntrl()
774 * - set testclk HIGH in test_mode_send()
775 * - set testdin with test code in test_mode_send()
776 * - set testen HIGH in test_mode_send()
777 * - set testclk LOW in test_mode_send()
778 * - set testen LOW in test_mode_send()
798 * - set testen LOW in test_mode_send()
799 * - set testclk LOW in test_mode_send()
800 * - set testdin with data in test_mode_send()
801 * - set testclk HIGH in test_mode_send()
853 if (vco->freq < vco_table[i].freq) { in mipi_tx_get_vco_params()
859 WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); in mipi_tx_get_vco_params()
869 /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz in mipi_tx_pll_setup()
870 * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) in mipi_tx_pll_setup()
871 * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) in mipi_tx_pll_setup()
872 * n: - valid range [0 15] in mipi_tx_pll_setup()
873 * N: - N = n + 1 in mipi_tx_pll_setup()
874 * -valid range: [1 16] in mipi_tx_pll_setup()
875 * -conditions: - (pll_ref_clk / N) >= 2 MHz in mipi_tx_pll_setup()
876 * -(pll_ref_clk / N) <= 8 MHz in mipi_tx_pll_setup()
878 * M: - M = m + 2 in mipi_tx_pll_setup()
879 * -valid range [64 625] in mipi_tx_pll_setup()
880 * -Fvco = (M/N) * pll_ref_clk in mipi_tx_pll_setup()
893 * multiply by 1000 for precision - in mipi_tx_pll_setup()
914 delta = abs(freq - target_freq_mhz); in mipi_tx_pll_setup()
935 dev_dbg(kmb_dsi->dev, "m = %d n = %d\n", best_m, best_n); in mipi_tx_pll_setup()
941 /* m - low nibble PLL_Loop_Divider_Ratio[4:0] in mipi_tx_pll_setup()
947 /* m - high nibble PLL_Loop_Divider_Ratio[4:0] in mipi_tx_pll_setup()
957 /* Program Charge-Pump parameters */ in mipi_tx_pll_setup()
959 /* pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ in mipi_tx_pll_setup()
965 /* pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ in mipi_tx_pll_setup()
969 /* pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ in mipi_tx_pll_setup()
972 /* pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ in mipi_tx_pll_setup()
975 /* pll_th1 -Lock Detector Phase error threshold, in mipi_tx_pll_setup()
976 * document gives fixed value in mipi_tx_pll_setup()
982 /* pll_th2 - Lock Filter length, document gives fixed value */ in mipi_tx_pll_setup()
985 /* pll_th3- PLL Unlocking filter, document gives fixed value */ in mipi_tx_pll_setup()
988 /* pll_lock_sel-PLL Lock Detector Selection, in mipi_tx_pll_setup()
989 * document gives fixed value in mipi_tx_pll_setup()
1014 /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON in set_slewrate_gt_1000()
1051 * - slew rate control ON in set_slewrate_lt_1000()
1052 * - typical rise/fall times: 225 ps in set_slewrate_lt_1000()
1087 mipi_tx_pll_setup(kmb_dsi, dphy_no, cfg->ref_clk_khz / 1000, in setup_pll()
1088 cfg->lane_rate_mbps / 2); in setup_pll()
1104 cfg->lane_rate_mbps) in set_lane_data_rate()
1123 /* Set D-PHY in shutdown mode */ in dphy_init_sequence()
1131 /* Init D-PHY_n in dphy_init_sequence()
1132 * Pulse testclear signal to make sure the d-phy configuration in dphy_init_sequence()
1142 /* Set mastermacro bit - Master or slave mode */ in dphy_init_sequence()
1157 /* High-Speed Tx Slew Rate Calibration in dphy_init_sequence()
1160 if (cfg->lane_rate_mbps > 1500) in dphy_init_sequence()
1162 else if (cfg->lane_rate_mbps > 1000) in dphy_init_sequence()
1168 val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; in dphy_init_sequence()
1171 /* Enable config clk for the corresponding d-phy */ in dphy_init_sequence()
1184 * NOTE: basedir only applies to LANE_0 of each D-PHY. in dphy_init_sequence()
1185 * The other lanes keep their direction based on the D-PHY type, in dphy_init_sequence()
1187 * bits[5:0] - BaseDir: 1 = Rx in dphy_init_sequence()
1188 * bits[9:6] - BaseDir: 0 = Tx in dphy_init_sequence()
1195 * set for the D-PHY (Rx/Tx) in dphy_init_sequence()
1201 ((1 << active_lanes) - 1)); in dphy_init_sequence()
1205 /* Take D-PHY out of shutdown mode */ in dphy_init_sequence()
1232 dev_dbg(kmb_dsi->dev, "%s: dphy %d val = %x", __func__, dphy_no, val); in dphy_wait_fsm()
1233 dev_dbg(kmb_dsi->dev, "* DPHY %d WAIT_FSM %s *", in dphy_wait_fsm()
1241 u32 data_lanes = (1 << active_lanes) - 1; in wait_init_done()
1249 /* TODO-need to add a time out and return failure */ in wait_init_done()
1254 dev_dbg(kmb_dsi->dev, in wait_init_done()
1261 dev_dbg(kmb_dsi->dev, "* DPHY %d INIT - %s *", in wait_init_done()
1271 /* TODO-need to add a time out and return failure */ in wait_pll_lock()
1275 dev_dbg(kmb_dsi->dev, "%s: timing out", __func__); in wait_pll_lock()
1280 dev_dbg(kmb_dsi->dev, "* PLL Locked for DPHY %d - %s *", in wait_pll_lock()
1289 /* Multiple D-PHYs needed */ in mipi_tx_init_dphy()
1290 if (cfg->active_lanes > MIPI_DPHY_D_LANES) { in mipi_tx_init_dphy()
1295 * b1. reg addr 0x03[3:0] - state_main[3:0] == 5 (LOCK) in mipi_tx_init_dphy()
1298 * - rescal_done in mipi_tx_init_dphy()
1300 * addr 0xA7[3:2] - srcal_done, sr_finished in mipi_tx_init_dphy()
1308 (cfg->active_lanes - MIPI_DPHY_D_LANES), in mipi_tx_init_dphy()
1319 cfg->active_lanes - MIPI_DPHY_D_LANES); in mipi_tx_init_dphy()
1324 dphy_init_sequence(kmb_dsi, cfg, dphy_no, cfg->active_lanes, in mipi_tx_init_dphy()
1327 wait_init_done(kmb_dsi, dphy_no, cfg->active_lanes); in mipi_tx_init_dphy()
1339 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam"); in connect_lcd_to_mipi()
1341 dev_dbg(kmb_dsi->dev, "failed to get msscam syscon"); in connect_lcd_to_mipi()
1345 /* DISABLE MIPI->CIF CONNECTION */ in connect_lcd_to_mipi()
1348 /* ENABLE LCD->MIPI CONNECTION */ in connect_lcd_to_mipi()
1350 /* DISABLE LCD->CIF LOOPBACK */ in connect_lcd_to_mipi()
1359 kmb_dsi->sys_clk_mhz = sys_clk_mhz; in kmb_dsi_mode_set()
1362 mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; in kmb_dsi_mode_set()
1363 mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; in kmb_dsi_mode_set()
1365 mode->crtc_vsync_end - mode->crtc_vsync_start; in kmb_dsi_mode_set()
1367 mode->crtc_vtotal - mode->crtc_vsync_end; in kmb_dsi_mode_set()
1369 mode->crtc_vsync_start - mode->crtc_vdisplay; in kmb_dsi_mode_set()
1371 mode->crtc_hsync_end - mode->crtc_hsync_start; in kmb_dsi_mode_set()
1373 mode->crtc_htotal - mode->crtc_hsync_end; in kmb_dsi_mode_set()
1375 mode->crtc_hsync_start - mode->crtc_hdisplay; in kmb_dsi_mode_set()
1380 data_rate = ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) * in kmb_dsi_mode_set()
1384 dev_dbg(kmb_dsi->dev, "data_rate=%u active_lanes=%d\n", in kmb_dsi_mode_set()
1404 dev_info(kmb_dsi->dev, "mipi hw initialized"); in kmb_dsi_mode_set()
1412 struct device *dev = get_device(&pdev->dev); in kmb_dsi_init()
1417 return ERR_PTR(-ENOMEM); in kmb_dsi_init()
1420 kmb_dsi->host = dsi_host; in kmb_dsi_init()
1421 kmb_dsi->host->ops = &kmb_dsi_host_ops; in kmb_dsi_init()
1423 dsi_device->host = kmb_dsi->host; in kmb_dsi_init()
1424 kmb_dsi->device = dsi_device; in kmb_dsi_init()
1435 encoder = &kmb_dsi->base; in kmb_dsi_encoder_init()
1436 encoder->possible_crtcs = 1; in kmb_dsi_encoder_init()
1437 encoder->possible_clones = 0; in kmb_dsi_encoder_init()
1441 dev_err(kmb_dsi->dev, "Failed to init encoder %d\n", ret); in kmb_dsi_encoder_init()
1466 struct device *dev = kmb_dsi->dev; in kmb_dsi_map_mmio()
1468 res = platform_get_resource_byname(kmb_dsi->pdev, IORESOURCE_MEM, in kmb_dsi_map_mmio()
1472 return -ENOMEM; in kmb_dsi_map_mmio()
1474 kmb_dsi->mipi_mmio = devm_ioremap_resource(dev, res); in kmb_dsi_map_mmio()
1475 if (IS_ERR(kmb_dsi->mipi_mmio)) { in kmb_dsi_map_mmio()
1477 return PTR_ERR(kmb_dsi->mipi_mmio); in kmb_dsi_map_mmio()
1485 struct device *dev = kmb_dsi->dev; in kmb_dsi_clk_enable()
1487 ret = clk_prepare_enable(kmb_dsi->clk_mipi); in kmb_dsi_clk_enable()
1493 ret = clk_prepare_enable(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_enable()
1499 ret = clk_prepare_enable(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_enable()
1511 struct device *dev = kmb_dsi->dev; in kmb_dsi_clk_init()
1514 kmb_dsi->clk_mipi = devm_clk_get(dev, "clk_mipi"); in kmb_dsi_clk_init()
1515 if (IS_ERR(kmb_dsi->clk_mipi)) { in kmb_dsi_clk_init()
1517 return PTR_ERR(kmb_dsi->clk_mipi); in kmb_dsi_clk_init()
1520 kmb_dsi->clk_mipi_ecfg = devm_clk_get(dev, "clk_mipi_ecfg"); in kmb_dsi_clk_init()
1521 if (IS_ERR(kmb_dsi->clk_mipi_ecfg)) { in kmb_dsi_clk_init()
1523 return PTR_ERR(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1526 kmb_dsi->clk_mipi_cfg = devm_clk_get(dev, "clk_mipi_cfg"); in kmb_dsi_clk_init()
1527 if (IS_ERR(kmb_dsi->clk_mipi_cfg)) { in kmb_dsi_clk_init()
1529 return PTR_ERR(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1532 clk_set_rate(kmb_dsi->clk_mipi, KMB_MIPI_DEFAULT_CLK); in kmb_dsi_clk_init()
1533 if (clk_get_rate(kmb_dsi->clk_mipi) != KMB_MIPI_DEFAULT_CLK) { in kmb_dsi_clk_init()
1536 return -1; in kmb_dsi_clk_init()
1538 dev_dbg(dev, "clk_mipi = %ld\n", clk_get_rate(kmb_dsi->clk_mipi)); in kmb_dsi_clk_init()
1540 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1543 clk_set_rate(kmb_dsi->clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); in kmb_dsi_clk_init()
1544 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1548 return -1; in kmb_dsi_clk_init()
1552 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1555 clk_set_rate(kmb_dsi->clk_mipi_cfg, 24000000); in kmb_dsi_clk_init()
1556 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1560 return -1; in kmb_dsi_clk_init()