1390 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_compute_pipe_wm()
1475 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()  local
1476 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1481 		*intermediate = *optimal;  in g4x_compute_intermediate_wm()
1488 	intermediate->cxsr = optimal->cxsr && active->cxsr &&  in g4x_compute_intermediate_wm()
1490 	intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&  in g4x_compute_intermediate_wm()
1492 	intermediate->fbc_en = optimal->fbc_en && active->fbc_en;  in g4x_compute_intermediate_wm()
1496 			max(optimal->wm.plane[plane_id],  in g4x_compute_intermediate_wm()
1503 	intermediate->sr.plane = max(optimal->sr.plane,  in g4x_compute_intermediate_wm()
1505 	intermediate->sr.cursor = max(optimal->sr.cursor,  in g4x_compute_intermediate_wm()
1507 	intermediate->sr.fbc = max(optimal->sr.fbc,  in g4x_compute_intermediate_wm()
1510 	intermediate->hpll.plane = max(optimal->hpll.plane,  in g4x_compute_intermediate_wm()
1512 	intermediate->hpll.cursor = max(optimal->hpll.cursor,  in g4x_compute_intermediate_wm()
1514 	intermediate->hpll.fbc = max(optimal->hpll.fbc,  in g4x_compute_intermediate_wm()
1542 	if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)  in g4x_compute_intermediate_wm()
1637 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_optimize_watermarks()
1912 	struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;  in vlv_compute_pipe_wm()
2119 	const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;  in vlv_compute_intermediate_wm()  local
2120 	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;  in vlv_compute_intermediate_wm()
2125 		*intermediate = *optimal;  in vlv_compute_intermediate_wm()
2131 	intermediate->num_levels = min(optimal->num_levels, active->num_levels);  in vlv_compute_intermediate_wm()
2132 	intermediate->cxsr = optimal->cxsr && active->cxsr &&  in vlv_compute_intermediate_wm()
2140 				min(optimal->wm[level].plane[plane_id],  in vlv_compute_intermediate_wm()
2144 		intermediate->sr[level].plane = min(optimal->sr[level].plane,  in vlv_compute_intermediate_wm()
2146 		intermediate->sr[level].cursor = min(optimal->sr[level].cursor,  in vlv_compute_intermediate_wm()
2157 	if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)  in vlv_compute_intermediate_wm()
2263 	crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;  in vlv_optimize_watermarks()
3176 	pipe_wm = &crtc_state->wm.ilk.optimal;  in ilk_compute_pipe_wm()
3248 	const struct intel_pipe_wm *b = &old_crtc_state->wm.ilk.optimal;  in ilk_compute_intermediate_wm()
3256 	*a = new_crtc_state->wm.ilk.optimal;  in ilk_compute_intermediate_wm()
3290 	if (memcmp(a, &new_crtc_state->wm.ilk.optimal, sizeof(*a)) != 0)  in ilk_compute_intermediate_wm()
3912 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
3934 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
3957 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
4025 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;  in intel_compute_sagv_mask()
5153 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5190 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5263 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5287 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_allocate_plane_ddb()
5866 	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;  in skl_build_pipe_wm()
5905 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_plane_wm()
5948 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_cursor_wm()
6210 		old_pipe_wm = &old_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
6211 		new_pipe_wm = &new_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
6404 						 &old_crtc_state->wm.skl.optimal,  in skl_wm_add_affected_planes()
6405 						 &new_crtc_state->wm.skl.optimal))  in skl_wm_add_affected_planes()
6529 	crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;  in ilk_optimize_watermarks()
6613 		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);  in skl_wm_get_hw_state()
6614 		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;  in skl_wm_get_hw_state()
6661 	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;  in ilk_pipe_wm_get_hw_state()
6871 		crtc_state->wm.g4x.optimal = *active;  in g4x_wm_get_hw_state()
6906 		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6939 			crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6940 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
7031 		crtc_state->wm.vlv.optimal = *active;  in vlv_wm_get_hw_state()
7062 		struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()
7088 			crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()
7089 		crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()