475 		dev_priv->wm.g4x.cxsr = enable;  in intel_set_memory_cxsr()
1215 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_set()
1234 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_fbc_wm_set()
1265 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_compute()
1307 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],  in g4x_raw_plane_wm_compute()
1308 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],  in g4x_raw_plane_wm_compute()
1309 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);  in g4x_raw_plane_wm_compute()
1314 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,  in g4x_raw_plane_wm_compute()
1315 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);  in g4x_raw_plane_wm_compute()
1324 	const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_is_valid()
1390 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_compute_pipe_wm()
1419 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1427 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1438 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1474 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;  in g4x_compute_intermediate_wm()
1475 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1476 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1559 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1581 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1594 	struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;  in g4x_program_watermarks()
1621 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;  in g4x_initial_watermarks()
1637 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_optimize_watermarks()
6807 	struct g4x_wm_values *wm = &dev_priv->wm.g4x;  in g4x_wm_get_hw_state()
6817 		struct g4x_wm_state *active = &crtc->wm.active.g4x;  in g4x_wm_get_hw_state()
6843 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6850 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6859 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6871 		crtc_state->wm.g4x.optimal = *active;  in g4x_wm_get_hw_state()
6872 		crtc_state->wm.g4x.intermediate = *active;  in g4x_wm_get_hw_state()
6906 		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6915 				&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6924 					&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6938 		crtc_state->wm.g4x.intermediate =  in g4x_wm_sanitize()
6939 			crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6940 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()