4060 			 struct skl_ddb_entry *ddb)  in skl_ddb_entry_for_slices()  argument
4065 		ddb->start = 0;  in skl_ddb_entry_for_slices()
4066 		ddb->end = 0;  in skl_ddb_entry_for_slices()
4070 	ddb->start = (ffs(slice_mask) - 1) * slice_size;  in skl_ddb_entry_for_slices()
4071 	ddb->end = fls(slice_mask) * slice_size;  in skl_ddb_entry_for_slices()
4073 	WARN_ON(ddb->start >= ddb->end);  in skl_ddb_entry_for_slices()
4074 	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);  in skl_ddb_entry_for_slices()
4079 	struct skl_ddb_entry ddb;  in mbus_ddb_offset()  local
4086 	skl_ddb_entry_for_slices(i915, slice_mask, &ddb);  in mbus_ddb_offset()
4088 	return ddb.start;  in mbus_ddb_offset()
4190 		new_dbuf_state->ddb[pipe].start = 0;  in skl_crtc_allocate_ddb()
4191 		new_dbuf_state->ddb[pipe].end = 0;  in skl_crtc_allocate_ddb()
4207 	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;  in skl_crtc_allocate_ddb()
4208 	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;  in skl_crtc_allocate_ddb()
4211 	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],  in skl_crtc_allocate_ddb()
4212 				&new_dbuf_state->ddb[pipe]))  in skl_crtc_allocate_ddb()
4227 	crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;  in skl_crtc_allocate_ddb()
4228 	crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;  in skl_crtc_allocate_ddb()
4234 		    old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,  in skl_crtc_allocate_ddb()
4235 		    new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,  in skl_crtc_allocate_ddb()
5107 	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];  in skl_allocate_plane_ddb()
5949 	const struct skl_ddb_entry *ddb =  in skl_write_cursor_wm()  local
5968 	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);  in skl_write_cursor_wm()
6019 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,  in skl_ddb_allocation_overlaps()  argument
6027 		    skl_ddb_entries_overlap(ddb, &entries[i]))  in skl_ddb_allocation_overlaps()
6616 		memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));  in skl_wm_get_hw_state()
6627 			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);  in skl_wm_get_hw_state()
6628 			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);  in skl_wm_get_hw_state()
6641 		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;  in skl_wm_get_hw_state()
6642 		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;  in skl_wm_get_hw_state()
6647 			    dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,  in skl_wm_get_hw_state()
6648 			    dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,  in skl_wm_get_hw_state()