1 // SPDX-License-Identifier: MIT
43 	return dimm->ranks * 64 / (dimm->width ?: 1);  in intel_dimm_num_devices()
82 	return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;  in icl_get_dimm_size()
116 	return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;  in skl_is_16gb_dimm()
125 		dimm->size = icl_get_dimm_size(val);  in skl_dram_get_dimm_info()
126 		dimm->width = icl_get_dimm_width(val);  in skl_dram_get_dimm_info()
127 		dimm->ranks = icl_get_dimm_ranks(val);  in skl_dram_get_dimm_info()
129 		dimm->size = skl_get_dimm_size(val);  in skl_dram_get_dimm_info()
130 		dimm->width = skl_get_dimm_width(val);  in skl_dram_get_dimm_info()
131 		dimm->ranks = skl_get_dimm_ranks(val);  in skl_dram_get_dimm_info()
134 	drm_dbg_kms(&i915->drm,  in skl_dram_get_dimm_info()
136 		    channel, dimm_name, dimm->size, dimm->width, dimm->ranks,  in skl_dram_get_dimm_info()
145 	skl_dram_get_dimm_info(i915, &ch->dimm_l,  in skl_dram_get_channel_info()
147 	skl_dram_get_dimm_info(i915, &ch->dimm_s,  in skl_dram_get_channel_info()
150 	if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {  in skl_dram_get_channel_info()
151 		drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);  in skl_dram_get_channel_info()
152 		return -EINVAL;  in skl_dram_get_channel_info()
155 	if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)  in skl_dram_get_channel_info()
156 		ch->ranks = 2;  in skl_dram_get_channel_info()
157 	else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)  in skl_dram_get_channel_info()
158 		ch->ranks = 2;  in skl_dram_get_channel_info()
160 		ch->ranks = 1;  in skl_dram_get_channel_info()
162 	ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||  in skl_dram_get_channel_info()
163 		skl_is_16gb_dimm(&ch->dimm_s);  in skl_dram_get_channel_info()
165 	drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",  in skl_dram_get_channel_info()
166 		    channel, ch->ranks, yesno(ch->is_16gb_dimm));  in skl_dram_get_channel_info()
172 intel_is_dram_symmetric(const struct dram_channel_info *ch0,  in intel_is_dram_symmetric()  argument
175 	return !memcmp(ch0, ch1, sizeof(*ch0)) &&  in intel_is_dram_symmetric()
176 		(ch0->dimm_s.size == 0 ||  in intel_is_dram_symmetric()
177 		 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));  in intel_is_dram_symmetric()
183 	struct dram_info *dram_info = &i915->dram_info;  in skl_dram_get_channels_info()
184 	struct dram_channel_info ch0 = {}, ch1 = {};  in skl_dram_get_channels_info()  local
188 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
190 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);  in skl_dram_get_channels_info()
192 		dram_info->num_channels++;  in skl_dram_get_channels_info()
194 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
198 		dram_info->num_channels++;  in skl_dram_get_channels_info()
200 	if (dram_info->num_channels == 0) {  in skl_dram_get_channels_info()
201 		drm_info(&i915->drm, "Number of memory channels is zero\n");  in skl_dram_get_channels_info()
202 		return -EINVAL;  in skl_dram_get_channels_info()
205 	if (ch0.ranks == 0 && ch1.ranks == 0) {  in skl_dram_get_channels_info()
206 		drm_info(&i915->drm, "couldn't get memory rank information\n");  in skl_dram_get_channels_info()
207 		return -EINVAL;  in skl_dram_get_channels_info()
210 	dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;  in skl_dram_get_channels_info()
212 	dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);  in skl_dram_get_channels_info()
214 	drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",  in skl_dram_get_channels_info()
215 		    yesno(dram_info->symmetric_memory));  in skl_dram_get_channels_info()
225 	val = intel_uncore_read(&i915->uncore,  in skl_get_dram_type()
246 	struct dram_info *dram_info = &i915->dram_info;  in skl_get_dram_info()
249 	dram_info->type = skl_get_dram_type(i915);  in skl_get_dram_info()
250 	drm_dbg_kms(&i915->drm, "DRAM type: %s\n",  in skl_get_dram_info()
251 		    intel_dram_type_str(dram_info->type));  in skl_get_dram_info()
299 		return 2;  in bxt_get_dimm_ranks()
328 	dimm->width = bxt_get_dimm_width(val);  in bxt_get_dimm_info()
329 	dimm->ranks = bxt_get_dimm_ranks(val);  in bxt_get_dimm_info()
333 	 * Gb to match the way we report this for non-LP platforms.  in bxt_get_dimm_info()
335 	dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);  in bxt_get_dimm_info()
340 	struct dram_info *dram_info = &i915->dram_info;  in bxt_get_dram_info()
352 		val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));  in bxt_get_dram_info()
356 		dram_info->num_channels++;  in bxt_get_dram_info()
361 		drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&  in bxt_get_dram_info()
362 			    dram_info->type != INTEL_DRAM_UNKNOWN &&  in bxt_get_dram_info()
363 			    dram_info->type != type);  in bxt_get_dram_info()
365 		drm_dbg_kms(&i915->drm,  in bxt_get_dram_info()
367 			    i - BXT_D_CR_DRP0_DUNIT_START,  in bxt_get_dram_info()
375 			dram_info->type = type;  in bxt_get_dram_info()
378 	if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {  in bxt_get_dram_info()
379 		drm_info(&i915->drm, "couldn't get memory information\n");  in bxt_get_dram_info()
380 		return -EINVAL;  in bxt_get_dram_info()
388 	struct dram_info *dram_info = &dev_priv->dram_info;  in icl_pcode_read_mem_global_info()
402 			dram_info->type = INTEL_DRAM_DDR4;  in icl_pcode_read_mem_global_info()
405 			dram_info->type = INTEL_DRAM_DDR5;  in icl_pcode_read_mem_global_info()
407 		case 2:  in icl_pcode_read_mem_global_info()
408 			dram_info->type = INTEL_DRAM_LPDDR5;  in icl_pcode_read_mem_global_info()
411 			dram_info->type = INTEL_DRAM_LPDDR4;  in icl_pcode_read_mem_global_info()
414 			dram_info->type = INTEL_DRAM_DDR3;  in icl_pcode_read_mem_global_info()
417 			dram_info->type = INTEL_DRAM_LPDDR3;  in icl_pcode_read_mem_global_info()
421 			return -1;  in icl_pcode_read_mem_global_info()
426 			dram_info->type = INTEL_DRAM_DDR4;  in icl_pcode_read_mem_global_info()
429 			dram_info->type = INTEL_DRAM_DDR3;  in icl_pcode_read_mem_global_info()
431 		case 2:  in icl_pcode_read_mem_global_info()
432 			dram_info->type = INTEL_DRAM_LPDDR3;  in icl_pcode_read_mem_global_info()
435 			dram_info->type = INTEL_DRAM_LPDDR4;  in icl_pcode_read_mem_global_info()
439 			return -1;  in icl_pcode_read_mem_global_info()
443 	dram_info->num_channels = (val & 0xf0) >> 4;  in icl_pcode_read_mem_global_info()
444 	dram_info->num_qgv_points = (val & 0xf00) >> 8;  in icl_pcode_read_mem_global_info()
445 	dram_info->num_psf_gv_points = (val & 0x3000) >> 12;  in icl_pcode_read_mem_global_info()
462 	i915->dram_info.wm_lv_0_adjust_needed = false;  in gen12_get_dram_info()
469 	struct dram_info *dram_info = &i915->dram_info;  in intel_dram_detect()
479 	dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);  in intel_dram_detect()
492 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);  in intel_dram_detect()
494 	drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",  in intel_dram_detect()
495 		    yesno(dram_info->wm_lv_0_adjust_needed));  in intel_dram_detect()
501 	static const u8 sets[4] = { 1, 1, 2, 2 };  in gen9_edram_size_mb()
515 	edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);  in intel_dram_edram_detect()
527 		i915->edram_size_mb = 128;  in intel_dram_edram_detect()
529 		i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);  in intel_dram_edram_detect()
531 	drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);  in intel_dram_edram_detect()