Lines Matching +full:dp +full:- +full:phy0
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
170 * REG_FIELD_GET() - Extract a u32 bitfield value
208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
212 * numbers, pick the 0-based __index'th value.
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
254 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
255 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
257 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
258 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
261 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
262 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
414 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
416 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
420 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
422 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
424 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
427 #define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
429 #define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
616 /* There are the 4 64-bit counter registers, one for each stream output */
634 /* There are the 16 64-bit CS General Purpose Registers */
1033 /* 11-bit array 0: pass-through, 1: negated */
1077 /* Same layout as CECX_Y + negate 11-bit array */
1414 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1760 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1763 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1764 (reg_ch1) - _BXT_PHY0_BASE))
1888 * ICL Port/COMBO-PHY Registers
2044 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2226 #define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
2280 /* The spec defines this only for BXT PHY0, but lets assume that this
2455 * [0-7] @ 0x2000 gen2,gen3
2456 * [8-15] @ 0x3000 945,g33,pnv
2458 * [0-15] @ 0x3000 gen4,gen5
2460 * [0-15] @ 0x100000 gen6,vlv,chv
2461 * [0-31] @ 0x100000 gen7+
2466 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2474 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2503 #define PRB0_BASE (0x2030 - 0x30)
2504 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2505 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2506 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2507 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2508 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2509 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2532 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2585 #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
2637 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2796 /* GM45+ chicken bits -- debug workaround bits that may be required
2807 /* Disables pipelining of read flushes past the SF-WIZ interface.
2808 * Required on all Ironlake steppings according to the B-Spec, but the
2895 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
3005 /* Enables non-sequential data reads through arbiter
3014 /* Arbiter time slice for non-isoch streams */
3172 * These defines should cover us well from SNB->HSW with minor exceptions
3211 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3246 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3346 /* The bit 28-8 is reserved */
3402 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3420 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3429 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3444 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3452 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3453 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3459 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3523 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3524 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
3533 /* i830, required in DVO non-gang */
3545 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3647 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3648 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3649 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3650 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3651 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3652 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3653 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3654 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3655 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3656 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3657 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3658 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3664 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3665 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3766 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3811 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3887 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3891 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3907 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3927 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3973 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3983 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3985 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3987 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3998 #define SWFREQ_MASK 0x0380 /* P0-7 */
4014 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
4026 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
4040 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
4066 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
4085 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
4126 * - Power context is saved elsewhere (LLC or stolen)
4127 * - Ring/execlist context is saved on SNB, not on IVB
4128 * - Extended context size already includes render context size
4129 * - We always need to follow the extended context size.
4133 * - Pipelined/VF state is saved on SNB/IVB respectively
4134 * - GT1 size just indicates how much of render context
4293 /* embedded DP port on the north display block, reserved on ivb */
4300 /* with DP port the pipe source is invalid */
4308 /* with DP/TV port the pipe source is invalid */
4515 #define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4554 0 : ((trans) - TRANSCODER_A + 1) * 8)
4620 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
4628 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4632 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << …
4635 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4639 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_P…
4720 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4723 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4726 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4729 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4748 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4751 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4754 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4757 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4773 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4776 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4779 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4782 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4798 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4801 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4804 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4807 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4824 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4893 * HDMI/DP bits are g4x+
4903 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4989 * Programmed value is multiplier - 1, up to 5x.
5080 /* Selects pipe B for LVDS data. Must be set on pre-965. */
5093 /* Enable border for unscaled (or aspect-scaled) display */
5096 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
5118 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
5119 * setting for whether we are in dual-channel mode. The B3 pair will
5130 * of the infoframe structure specified by CEA-861. */
5176 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
5186 * - PLL enabled
5187 * - pipe enabled
5188 * - LVDS/DVOB/DVOC on
5259 /* Pre-965 */
5336 /* New registers for PCH-split platforms. Safe where new bits show up, the
5417 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
5432 /* Read-only state that reports all features enabled */
5434 /* Read-only state that reports that Macrovision is disabled in hardware*/
5436 /* Read-only state that reports that TV-out is disabled in hardware. */
5440 /* Encoder test pattern 1 - combo pattern */
5442 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5444 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5446 /* Encoder test pattern 4 - random noise */
5448 /* Encoder test pattern 5 - linear color ramps */
5474 * Enables DAC state detection logic, for load-based TV detection.
5505 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5506 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5507 * -1 (0x3) being the only legal negative value.
5561 /* 2s-complement brightness adjustment */
5591 /* Enables the colorburst (needed for non-component color) */
5795 * (src width - 1) / ((oversample * dest width) - 1)
5802 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5804 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5809 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5818 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5820 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5827 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5887 /* Link training mode - select a suitable mode for each stage */
5911 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5922 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5999 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
6000 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
6007 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
6018 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
6019 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
6035 * (the DP spec calls pixel_clock the 'strm_clk')
6038 * Attributes and VB-ID.
6066 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
6067 #define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
6073 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
6074 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
6075 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
6076 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
6082 /* Note that pre-gen3 does not support interlaced display directly. Panel
6083 * fitting must be disabled on pre-ilk for interlaced. */
6101 #define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
6102 #define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
6103 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
6104 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
6135 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
6158 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
6207 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
6209 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
6351 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
6605 /* the unit of memory self-refresh latency time is 0.5us */
6652 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6770 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8…
6913 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 …
7061 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
7078 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)…
7088 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
7124 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
7128 * expanded to include bit 23 as well. However, the shift-24 based values
7144 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
7166 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
7175 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
7231 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
7234 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
7462 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7468 _SEL_FETCH_PLANE_CTL_1_A - \
7474 _SEL_FETCH_PLANE_POS_1_A - \
7479 _SEL_FETCH_PLANE_SIZE_1_A - \
7484 _SEL_FETCH_PLANE_OFFSET_1_A - \
7506 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
7507 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
7508 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
7509 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
7510 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
7796 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7807 /* MMIO address range for DMC program (0x80000 - 0x82FFF) */
7969 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
7970 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
8083 #define GEN11_VECS(x) (31 - (x))
8129 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
8235 * with gen13 display, the bspec switches to a 0-based numbering scheme
8237 * We'll just use the 0-based numbering here for all platforms since it's the
8254 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
8255 …F_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
8370 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8493 /* south display engine interrupt: CPT - CNP */
8574 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
8575 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
8576 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
8577 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
8578 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
8585 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
8586 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
8587 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
8588 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
8589 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
8596 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
8597 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
8598 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
8599 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
8600 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
8727 /* Per-transcoder DIP controls (PCH) */
8743 /* Per-transcoder DIP controls (VLV) */
8868 #define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
8889 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8900 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8901 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8946 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8948 /* SNB A-stepping */
8953 /* SNB B-stepping */
8961 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8978 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8983 /* train, dp width same as FDI_TX */
9079 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AU…
9080 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
9090 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
9105 /* SNB A-stepping */
9110 /* SNB B-stepping */
9165 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
9402 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
9618 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9619 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9637 /* These are the 4 32-bit write offset registers for each stream
9727 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
9742 * HSW - ICL power wells
9746 * - main (HSW_PWR_WELL_CTL[1-4])
9747 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9748 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9751 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9752 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9753 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9754 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9779 /* ICL/TGL - power wells */
9786 /* XE_LPD - power wells */
9838 /* HSW - power well misc debug registers */
9858 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9861 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9864 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9867 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9868 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9870 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
10138 /* Per-pipe DDI Function Control */
10157 …DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
10258 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
10270 /* DDI DP Compliance Control */
10283 /* DDI DP Compliance Pattern */
10356 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10529 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10530 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10538 (tc_port) - TC_PORT_4 + 21))
10618 /* ADL-P Type C PLL */
10848 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
11056 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
11139 /* Pipe WM_LINETIME - watermark line time */
11179 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
11388 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11631 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11645 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11704 /* MIPI DSI Controller and D-PHY registers */
11706 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
11707 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
11716 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
11717 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
11719 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
11720 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
11755 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
11756 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
11778 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
11779 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
11783 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
11784 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
11788 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
11789 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
11793 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
11794 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
11798 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
11799 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
11806 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
11807 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
11814 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
11815 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
11818 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
11819 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
11822 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
11823 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
11826 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
11827 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
11830 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
11831 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
11834 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
11835 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
11838 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
11839 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
11842 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
11843 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
11848 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
11849 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
11859 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
11860 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
11865 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
11866 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
11871 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
11872 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
11878 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
11879 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
11888 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
11889 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
11902 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
11903 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
11908 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
11909 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
11912 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
11913 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
11917 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
11918 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
11922 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
11923 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
11926 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
11927 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
11929 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
11930 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
11942 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
11943 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
11960 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
11961 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
11967 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
11968 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
12217 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
12218 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
12221 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
12222 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
12229 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
12230 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
12235 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
12236 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
12238 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
12239 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
12244 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
12258 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
12259 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
12291 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
12292 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
12298 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
12299 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
12304 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
12305 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
12313 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
12314 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
12319 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
12320 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
12323 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
12324 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
12387 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12390 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12408 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12411 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12422 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12425 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12437 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12440 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12452 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12455 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12467 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12470 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12482 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12485 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12499 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12502 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12514 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12517 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12529 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12532 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12544 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12547 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12561 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12564 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12574 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12577 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12587 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12590 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12600 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12603 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12613 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12616 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12626 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12629 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12649 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12652 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12655 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12658 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12674 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12677 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12680 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12683 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \