Lines Matching +full:0 +full:x62000

106  *  #define _FOO_A                      0xf000
107  *  #define _FOO_B                      0xf001
111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
121  * @__n: 0-based bit number
130 				 ((__n) < 0 || (__n) > 31))))
134  * @__high: 0-based high bit
135  * @__low: 0-based low bit
145 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
150 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
165 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
167 …ERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
187 #define INVALID_MMIO_REG _MMIO(0)
204 #define VLV_DISPLAY_BASE		0x180000
206 #define BXT_MIPI_BASE			0x60000
212  * numbers, pick the 0-based __index'th value.
219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
268 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
270 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
276 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
280 #define MCHBAR_I915 0x44
281 #define MCHBAR_I965 0x48
284 #define DEVEN 0x54
289 #define HPLLCC	0xc0 /* 85x only */
290 #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
291 #define   GC_CLOCK_133_200		(0 << 0)
292 #define   GC_CLOCK_100_200		(1 << 0)
293 #define   GC_CLOCK_100_133		(2 << 0)
294 #define   GC_CLOCK_133_266		(3 << 0)
295 #define   GC_CLOCK_133_200_2		(4 << 0)
296 #define   GC_CLOCK_133_266_2		(5 << 0)
297 #define   GC_CLOCK_166_266		(6 << 0)
298 #define   GC_CLOCK_166_250		(7 << 0)
300 #define I915_GDRST 0xc0 /* PCI config register */
301 #define   GRDOM_FULL		(0 << 2)
306 #define   GRDOM_RESET_ENABLE	(1 << 0)
309 #define I830_CLOCK_GATE	0xc8 /* device 0 */
312 #define GCDGMBUS 0xcc
314 #define GCFGC2	0xda
315 #define GCFGC	0xf0 /* 915+ only */
317 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
319 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
326 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
327 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
328 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
329 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
330 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
331 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
332 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
333 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
334 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
335 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
336 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
337 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
338 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
339 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
340 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
341 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
342 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
343 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
344 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
346 #define ASLE	0xe4
347 #define ASLS	0xfc
349 #define SWSCI	0xe8
351 #define   SWSCI_GSSCIE	(1 << 0)
353 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
356 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
357 #define  ILK_GRDOM_FULL		(0 << 1)
361 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
363 #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
366 #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
371 #define VLV_G3DCTL		_MMIO(0x9024)
372 #define VLV_GSCKGCTL		_MMIO(0x9028)
374 #define GEN6_MBCTL		_MMIO(0x0907c)
379 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
381 #define GEN6_GDRST	_MMIO(0x941c)
382 #define  GEN6_GRDOM_FULL		(1 << 0)
414 #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
415 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
416 #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
417 #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
420 #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
421 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
422 #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
423 #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
424 #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
425 #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
427 #define GEN12_HCP_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x2910)
428 #define   GEN12_HCP_SFC_FORCED_LOCK_BIT		REG_BIT(0)
429 #define GEN12_HCP_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x2914)
431 #define   GEN12_HCP_SFC_USAGE_BIT			REG_BIT(0)
433 #define GEN12_SFC_DONE(n)		_MMIO(0x1cc000 + (n) * 0x1000)
436 #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
437 #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
438 #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
439 #define   PP_DIR_DCLV_2G		0xffffffff
441 #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
442 #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
444 #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
448 #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
450 #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
453 #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
455 #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
456 #define   GEN8_RPCS_EU_MIN_SHIFT	0
457 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
459 #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
462 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
464 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
466 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
471 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
473 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
476 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIF…
478 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
481 #define GAM_ECOCHK			_MMIO(0x4090)
486 #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
487 #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
488 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
489 #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
490 #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
491 #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
492 #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
494 #define GEN8_RC6_CTX_INFO		_MMIO(0x8504)
496 #define GAC_ECO_BITS			_MMIO(0x14090)
499 #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
501 #define GAB_CTL				_MMIO(0x24000)
504 #define GU_CNTL				_MMIO(0x101010)
507 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
508 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
509 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
511 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
516 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
519 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
523 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
524 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
528 #define VGA_ST01_MDA 0x3ba
529 #define VGA_ST01_CGA 0x3da
531 #define _VGA_MSR_WRITE _MMIO(0x3c2)
532 #define VGA_MSR_WRITE 0x3c2
533 #define VGA_MSR_READ 0x3cc
535 #define   VGA_MSR_CGA_MODE (1 << 0)
537 #define VGA_SR_INDEX 0x3c4
539 #define VGA_SR_DATA 0x3c5
541 #define VGA_AR_INDEX 0x3c0
543 #define VGA_AR_DATA_WRITE 0x3c0
544 #define VGA_AR_DATA_READ 0x3c1
546 #define VGA_GR_INDEX 0x3ce
547 #define VGA_GR_DATA 0x3cf
552 #define   VGA_GR_MEM_MODE_MASK 0xc
554 #define   VGA_GR_MEM_A0000_AFFFF 0
559 #define VGA_DACMASK 0x3c6
560 #define VGA_DACRX 0x3c7
561 #define VGA_DACWX 0x3c8
562 #define VGA_DACDATA 0x3c9
564 #define VGA_CR_INDEX_MDA 0x3b4
565 #define VGA_CR_DATA_MDA 0x3b5
566 #define VGA_CR_INDEX_CGA 0x3d4
567 #define VGA_CR_DATA_CGA 0x3d5
569 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
570 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
571 #define MI_PREDICATE_SRC1	_MMIO(0x2408)
572 #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
573 #define MI_PREDICATE_DATA       _MMIO(0x2410)
574 #define MI_PREDICATE_RESULT     _MMIO(0x2418)
575 #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
576 #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
577 #define  LOWER_SLICE_ENABLED	(1 << 0)
578 #define  LOWER_SLICE_DISABLED	(0 << 0)
583 #define BCS_SWCTRL _MMIO(0x22200)
584 #define   BCS_SRC_Y REG_BIT(0)
588 #define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)
589 #define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)
591 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
592 #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
593 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
594 #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
595 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
596 #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
597 #define IA_VERTICES_COUNT               _MMIO(0x2310)
598 #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
599 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
600 #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
601 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
602 #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
603 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
604 #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
605 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
606 #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
607 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
608 #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
609 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
610 #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
611 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
612 #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
613 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
614 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
617 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
618 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
620 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
621 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
623 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
624 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
625 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
626 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
627 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
628 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
630 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
631 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
632 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
635 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
636 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
638 #define GEN7_OACONTROL _MMIO(0x2360)
639 #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
640 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
643 #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
653 #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
655 #define GEN8_OACTXID _MMIO(0x2364)
657 #define GEN8_OA_DEBUG _MMIO(0x2B04)
663 #define GEN8_OACONTROL _MMIO(0x2B00)
664 #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
670 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
672 #define GEN8_OACTXCONTROL _MMIO(0x2360)
673 #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
676 #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
678 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
682 #define  GEN7_OABUFFER_RESUME		    (1 << 0)
684 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
685 #define GEN8_OABUFFER _MMIO(0x2b14)
686 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
688 #define GEN7_OASTATUS1 _MMIO(0x2364)
689 #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
692 #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
694 #define GEN7_OASTATUS2 _MMIO(0x2368)
695 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
696 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
698 #define GEN8_OASTATUS _MMIO(0x2b08)
704 #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
706 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
707 #define GEN8_OAHEADPTR_MASK    0xffffffc0
708 #define GEN8_OATAILPTR _MMIO(0x2B10)
709 #define GEN8_OATAILPTR_MASK    0xffffffc0
711 #define OABUFFER_SIZE_128K  (0 << 3)
720 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
723 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
725 #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
727 #define GEN12_OACTXCONTROL _MMIO(0x2360)
728 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
731 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
732 #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
733 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
734 #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
736 #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
737 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
739 #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
741 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
744 #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
746 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
748 #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
750 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
756 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
759 #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
765 #define EU_PERF_CNTL0	    _MMIO(0xe458)
766 #define EU_PERF_CNTL1	    _MMIO(0xe558)
767 #define EU_PERF_CNTL2	    _MMIO(0xe658)
768 #define EU_PERF_CNTL3	    _MMIO(0xe758)
769 #define EU_PERF_CNTL4	    _MMIO(0xe45c)
770 #define EU_PERF_CNTL5	    _MMIO(0xe55c)
771 #define EU_PERF_CNTL6	    _MMIO(0xe65c)
777 #define OASTARTTRIG1 _MMIO(0x2710)
778 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
779 #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
781 #define OASTARTTRIG2 _MMIO(0x2714)
782 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
812 #define OASTARTTRIG3 _MMIO(0x2718)
813 #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
814 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
823 #define OASTARTTRIG4 _MMIO(0x271c)
824 #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
825 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
834 #define OASTARTTRIG5 _MMIO(0x2720)
835 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
836 #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
838 #define OASTARTTRIG6 _MMIO(0x2724)
839 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
869 #define OASTARTTRIG7 _MMIO(0x2728)
870 #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
871 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
880 #define OASTARTTRIG8 _MMIO(0x272c)
881 #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
882 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
891 #define OAREPORTTRIG1 _MMIO(0x2740)
892 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
893 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
895 #define OAREPORTTRIG2 _MMIO(0x2744)
896 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
922 #define OAREPORTTRIG3 _MMIO(0x2748)
923 #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
924 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
933 #define OAREPORTTRIG4 _MMIO(0x274c)
934 #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
935 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
944 #define OAREPORTTRIG5 _MMIO(0x2750)
945 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
946 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
948 #define OAREPORTTRIG6 _MMIO(0x2754)
949 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
975 #define OAREPORTTRIG7 _MMIO(0x2758)
976 #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
977 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
986 #define OAREPORTTRIG8 _MMIO(0x275c)
987 #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
988 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
998 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
999 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
1000 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
1001 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
1002 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
1003 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
1004 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
1005 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
1008 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
1009 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
1010 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
1011 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
1012 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
1013 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
1014 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
1015 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1024 #define OACEC_COMPARE_ANY_EQUAL		0
1026 #define OACEC_COMPARE_VALUE_MASK    0xffff
1029 #define OACEC_SELECT_NOA	(0 << 19)
1033 /* 11-bit array 0: pass-through, 1: negated */
1034 #define GEN12_OASCEC_NEGATE_MASK  0x7ff
1038 #define OACEC_MASK_MASK		    0xffff
1039 #define OACEC_CONSIDERATIONS_MASK   0xffff
1042 #define OACEC0_0 _MMIO(0x2770)
1043 #define OACEC0_1 _MMIO(0x2774)
1044 #define OACEC1_0 _MMIO(0x2778)
1045 #define OACEC1_1 _MMIO(0x277c)
1046 #define OACEC2_0 _MMIO(0x2780)
1047 #define OACEC2_1 _MMIO(0x2784)
1048 #define OACEC3_0 _MMIO(0x2788)
1049 #define OACEC3_1 _MMIO(0x278c)
1050 #define OACEC4_0 _MMIO(0x2790)
1051 #define OACEC4_1 _MMIO(0x2794)
1052 #define OACEC5_0 _MMIO(0x2798)
1053 #define OACEC5_1 _MMIO(0x279c)
1054 #define OACEC6_0 _MMIO(0x27a0)
1055 #define OACEC6_1 _MMIO(0x27a4)
1056 #define OACEC7_0 _MMIO(0x27a8)
1057 #define OACEC7_1 _MMIO(0x27ac)
1060 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1061 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1062 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1063 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1064 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1065 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1066 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1067 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1068 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1069 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1070 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1071 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1072 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1073 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1074 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1075 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1078 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1079 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1080 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1081 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1082 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1083 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1084 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1085 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1086 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1087 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1088 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1089 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1090 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1091 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1092 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1093 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1096 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
1097 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
1098 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
1099 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
1100 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
1101 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
1102 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
1103 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
1105 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
1106 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
1109 #define RPM_CONFIG0	    _MMIO(0x0D00)
1112 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
1115 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHI…
1116 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
1121 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_S…
1123 #define RPM_CONFIG1	    _MMIO(0x0D04)
1127 #define CTC_MODE			_MMIO(0xA26C)
1129 #define  CTC_SOURCE_CRYSTAL_CLOCK	0
1132 #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1135 #define RCP_CONFIG	    _MMIO(0x0D08)
1138 #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
1139 #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
1140 #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
1141 #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
1142 #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
1143 #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
1144 #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
1145 #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
1146 #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
1147 #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
1149 #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
1152 #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
1154 #define MICRO_BP0_0	    _MMIO(0x9800)
1155 #define MICRO_BP0_2	    _MMIO(0x9804)
1156 #define MICRO_BP0_1	    _MMIO(0x9808)
1158 #define MICRO_BP1_0	    _MMIO(0x980C)
1159 #define MICRO_BP1_2	    _MMIO(0x9810)
1160 #define MICRO_BP1_1	    _MMIO(0x9814)
1162 #define MICRO_BP2_0	    _MMIO(0x9818)
1163 #define MICRO_BP2_2	    _MMIO(0x981C)
1164 #define MICRO_BP2_1	    _MMIO(0x9820)
1166 #define MICRO_BP3_0	    _MMIO(0x9824)
1167 #define MICRO_BP3_2	    _MMIO(0x9828)
1168 #define MICRO_BP3_1	    _MMIO(0x982C)
1170 #define MICRO_BP_TRIGGER		_MMIO(0x9830)
1171 #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
1172 #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
1173 #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
1175 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1176 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1177 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1179 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1180 #define   GT_NOA_ENABLE	    0x00000080
1182 #define NOA_DATA	    _MMIO(0x986C)
1183 #define NOA_WRITE	    _MMIO(0x9888)
1184 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1186 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
1187 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
1193 #define DEBUG_RESET_I830		_MMIO(0x6070)
1201 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
1207 #define   IOSF_SB_BUSY				(1 << 0)
1208 #define   IOSF_PORT_BUNIT			0x03
1209 #define   IOSF_PORT_PUNIT			0x04
1210 #define   IOSF_PORT_NC				0x11
1211 #define   IOSF_PORT_DPIO			0x12
1212 #define   IOSF_PORT_GPIO_NC			0x13
1213 #define   IOSF_PORT_CCK				0x14
1214 #define   IOSF_PORT_DPIO_2			0x1a
1215 #define   IOSF_PORT_FLISDSI			0x1b
1216 #define   IOSF_PORT_GPIO_SC			0x48
1217 #define   IOSF_PORT_GPIO_SUS			0xa8
1218 #define   IOSF_PORT_CCU				0xa9
1219 #define   CHV_IOSF_PORT_GPIO_N			0x13
1220 #define   CHV_IOSF_PORT_GPIO_SE			0x48
1221 #define   CHV_IOSF_PORT_GPIO_E			0xa8
1222 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
1223 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
1224 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
1227 #define BUNIT_REG_BISOC				0x11
1230 #define   _SSPM0_SSC(val)			((val) << 0)
1231 #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
1232 #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
1233 #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
1234 #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
1235 #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
1237 #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
1238 #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
1239 #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
1240 #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
1241 #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
1245 #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
1247 #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
1248 #define   SSPM1_FREQ_SHIFT			0
1249 #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
1251 #define PUNIT_REG_VEDSSPM0			0x32
1252 #define PUNIT_REG_VEDSSPM1			0x33
1254 #define PUNIT_REG_DSPSSPM			0x36
1256 #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
1258 #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
1260 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
1262 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
1267 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
1268 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
1269 #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
1270 #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
1271 #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
1273 #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
1274 #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
1275 #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
1276 #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
1277 #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
1279 #define PUNIT_REG_ISPSSPM0			0x39
1280 #define PUNIT_REG_ISPSSPM1			0x3a
1282 #define PUNIT_REG_PWRGT_CTRL			0x60
1283 #define PUNIT_REG_PWRGT_STATUS			0x61
1285 #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
1290 #define PUNIT_PWGT_IDX_RENDER			0
1302 #define PUNIT_REG_GPU_LFM			0xd3
1303 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
1304 #define PUNIT_REG_GPU_FREQ_STS			0xd8
1306 #define   GENFREQSTATUS				(1 << 0)
1307 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
1308 #define PUNIT_REG_CZ_TIMESTAMP			0xce
1310 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
1311 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
1313 #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
1314 #define FB_GFX_FREQ_FUSE_MASK			0xff
1319 #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
1322 #define PUNIT_REG_DDR_SETUP2			0x139
1325 #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
1327 #define PUNIT_GPU_STATUS_REG			0xdb
1329 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
1331 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
1333 #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
1335 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
1337 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
1339 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
1341 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
1342 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
1343 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
1344 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
1346 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
1348 #define VLV_TURBO_SOC_OVERRIDE		0x04
1355 #define CCK_FUSE_REG				0x8
1356 #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
1357 #define CCK_REG_DSI_PLL_FUSE			0x44
1358 #define CCK_REG_DSI_PLL_CONTROL			0x48
1362 #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
1366 #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
1368 #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
1370 #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
1375 #define  DSI_PLL_LOCK				(1 << 0)
1376 #define CCK_REG_DSI_PLL_DIVIDER			0x4c
1382 #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
1385 #define  DSI_PLL_M1_DIV_SHIFT			0
1386 #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
1387 #define CCK_CZ_CLOCK_CONTROL			0x62
1388 #define CCK_GPLL_CLOCK_CONTROL			0x67
1389 #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
1390 #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
1393 #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
1395 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
1398 #define DPIO_DEVFN			0
1400 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
1404 #define  DPIO_CMNRST			(1 << 0)
1411 #define _VLV_PLL_DW3_CH0		0x800c
1413 #define   DPIO_POST_DIV_DAC		0
1423 #define   DPIO_M2DIV_MASK		0xff
1424 #define _VLV_PLL_DW3_CH1		0x802c
1427 #define _VLV_PLL_DW5_CH0		0x8014
1430 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
1433 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
1434 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
1435 #define _VLV_PLL_DW5_CH1		0x8034
1438 #define _VLV_PLL_DW7_CH0		0x801c
1439 #define _VLV_PLL_DW7_CH1		0x803c
1442 #define _VLV_PLL_DW8_CH0		0x8040
1443 #define _VLV_PLL_DW8_CH1		0x8060
1446 #define VLV_PLL_DW9_BCAST		0xc044
1447 #define _VLV_PLL_DW9_CH0		0x8044
1448 #define _VLV_PLL_DW9_CH1		0x8064
1451 #define _VLV_PLL_DW10_CH0		0x8048
1452 #define _VLV_PLL_DW10_CH1		0x8068
1455 #define _VLV_PLL_DW11_CH0		0x804c
1456 #define _VLV_PLL_DW11_CH1		0x806c
1460 #define VLV_REF_DW13			0x80ac
1462 #define VLV_CMN_DW0			0x8100
1468 #define _VLV_PCS_DW0_CH0		0x8200
1469 #define _VLV_PCS_DW0_CH1		0x8400
1476 #define _VLV_PCS01_DW0_CH0		0x200
1477 #define _VLV_PCS23_DW0_CH0		0x400
1478 #define _VLV_PCS01_DW0_CH1		0x2600
1479 #define _VLV_PCS23_DW0_CH1		0x2800
1483 #define _VLV_PCS_DW1_CH0		0x8204
1484 #define _VLV_PCS_DW1_CH1		0x8404
1492 #define _VLV_PCS01_DW1_CH0		0x204
1493 #define _VLV_PCS23_DW1_CH0		0x404
1494 #define _VLV_PCS01_DW1_CH1		0x2604
1495 #define _VLV_PCS23_DW1_CH1		0x2804
1499 #define _VLV_PCS_DW8_CH0		0x8220
1500 #define _VLV_PCS_DW8_CH1		0x8420
1505 #define _VLV_PCS01_DW8_CH0		0x0220
1506 #define _VLV_PCS23_DW8_CH0		0x0420
1507 #define _VLV_PCS01_DW8_CH1		0x2620
1508 #define _VLV_PCS23_DW8_CH1		0x2820
1512 #define _VLV_PCS_DW9_CH0		0x8224
1513 #define _VLV_PCS_DW9_CH1		0x8424
1514 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
1515 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
1517 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
1518 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
1522 #define _VLV_PCS01_DW9_CH0		0x224
1523 #define _VLV_PCS23_DW9_CH0		0x424
1524 #define _VLV_PCS01_DW9_CH1		0x2624
1525 #define _VLV_PCS23_DW9_CH1		0x2824
1529 #define _CHV_PCS_DW10_CH0		0x8228
1530 #define _CHV_PCS_DW10_CH1		0x8428
1533 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
1534 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
1536 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
1537 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
1541 #define _VLV_PCS01_DW10_CH0		0x0228
1542 #define _VLV_PCS23_DW10_CH0		0x0428
1543 #define _VLV_PCS01_DW10_CH1		0x2628
1544 #define _VLV_PCS23_DW10_CH1		0x2828
1548 #define _VLV_PCS_DW11_CH0		0x822c
1549 #define _VLV_PCS_DW11_CH1		0x842c
1553 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
1556 #define _VLV_PCS01_DW11_CH0		0x022c
1557 #define _VLV_PCS23_DW11_CH0		0x042c
1558 #define _VLV_PCS01_DW11_CH1		0x262c
1559 #define _VLV_PCS23_DW11_CH1		0x282c
1563 #define _VLV_PCS01_DW12_CH0		0x0230
1564 #define _VLV_PCS23_DW12_CH0		0x0430
1565 #define _VLV_PCS01_DW12_CH1		0x2630
1566 #define _VLV_PCS23_DW12_CH1		0x2830
1570 #define _VLV_PCS_DW12_CH0		0x8230
1571 #define _VLV_PCS_DW12_CH1		0x8430
1576 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
1579 #define _VLV_PCS_DW14_CH0		0x8238
1580 #define _VLV_PCS_DW14_CH1		0x8438
1583 #define _VLV_PCS_DW23_CH0		0x825c
1584 #define _VLV_PCS_DW23_CH1		0x845c
1587 #define _VLV_TX_DW2_CH0			0x8288
1588 #define _VLV_TX_DW2_CH1			0x8488
1590 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1594 #define _VLV_TX_DW3_CH0			0x828c
1595 #define _VLV_TX_DW3_CH1			0x848c
1599 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1602 #define _VLV_TX_DW4_CH0			0x8290
1603 #define _VLV_TX_DW4_CH1			0x8490
1605 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1607 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1610 #define _VLV_TX3_DW4_CH0		0x690
1611 #define _VLV_TX3_DW4_CH1		0x2a90
1614 #define _VLV_TX_DW5_CH0			0x8294
1615 #define _VLV_TX_DW5_CH1			0x8494
1619 #define _VLV_TX_DW11_CH0		0x82ac
1620 #define _VLV_TX_DW11_CH1		0x84ac
1623 #define _VLV_TX_DW14_CH0		0x82b8
1624 #define _VLV_TX_DW14_CH1		0x84b8
1628 #define _CHV_PLL_DW0_CH0		0x8000
1629 #define _CHV_PLL_DW0_CH1		0x8180
1632 #define _CHV_PLL_DW1_CH0		0x8004
1633 #define _CHV_PLL_DW1_CH1		0x8184
1635 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1638 #define _CHV_PLL_DW2_CH0		0x8008
1639 #define _CHV_PLL_DW2_CH1		0x8188
1642 #define _CHV_PLL_DW3_CH0		0x800c
1643 #define _CHV_PLL_DW3_CH1		0x818c
1645 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1647 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1648 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1651 #define _CHV_PLL_DW6_CH0		0x8018
1652 #define _CHV_PLL_DW6_CH1		0x8198
1655 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1658 #define _CHV_PLL_DW8_CH0		0x8020
1659 #define _CHV_PLL_DW8_CH1		0x81A0
1660 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1661 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1664 #define _CHV_PLL_DW9_CH0		0x8024
1665 #define _CHV_PLL_DW9_CH1		0x81A4
1668 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1671 #define _CHV_CMN_DW0_CH0               0x8100
1675 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1677 #define _CHV_CMN_DW5_CH0               0x8114
1678 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1682 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1687 #define _CHV_CMN_DW13_CH0		0x8134
1688 #define _CHV_CMN_DW0_CH1		0x8080
1694 #define   DPIO_PLL_LOCK			(1 << 0)
1697 #define _CHV_CMN_DW14_CH0		0x8138
1698 #define _CHV_CMN_DW1_CH1		0x8084
1701 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1705 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1711 #define _CHV_CMN_DW19_CH0		0x814c
1712 #define _CHV_CMN_DW6_CH1		0x8098
1720 #define CHV_CMN_DW28			0x8170
1723 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1724 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1725 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1726 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1728 #define CHV_CMN_DW30			0x8178
1732 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1733 					(lane) * 0x200 + (offset))
1735 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1736 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1737 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1738 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1739 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1740 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1741 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1742 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1743 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1744 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1745 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1746 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1748 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1752 #define _BXT_PHY0_BASE			0x6C000
1753 #define _BXT_PHY1_BASE			0x162000
1754 #define _BXT_PHY2_BASE			0x163000
1768 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1771 #define _BXT_PHY_CTL_DDI_A		0x64C00
1772 #define _BXT_PHY_CTL_DDI_B		0x64C10
1773 #define _BXT_PHY_CTL_DDI_C		0x64C20
1780 #define _PHY_CTL_FAMILY_EDP		0x64C80
1781 #define _PHY_CTL_FAMILY_DDI		0x64C90
1782 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
1789 #define _PORT_PLL_A			0x46074
1790 #define _PORT_PLL_B			0x46078
1791 #define _PORT_PLL_C			0x4607c
1799 #define _PORT_PLL_EBB_0_A		0x162034
1800 #define _PORT_PLL_EBB_0_B		0x6C034
1801 #define _PORT_PLL_EBB_0_C		0x6C340
1803 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1806 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1812 #define _PORT_PLL_EBB_4_A		0x162038
1813 #define _PORT_PLL_EBB_4_B		0x6C038
1814 #define _PORT_PLL_EBB_4_C		0x6C344
1821 #define _PORT_PLL_0_A			0x162100
1822 #define _PORT_PLL_0_B			0x6C100
1823 #define _PORT_PLL_0_C			0x6C380
1825 #define   PORT_PLL_M2_MASK		0xFF
1828 #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1831 #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1835 #define   PORT_PLL_PROP_COEFF_MASK	0xF
1836 #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1838 #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1841 #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1844 #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1848 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1857 #define _PORT_CL1CM_DW0_A		0x162000
1858 #define _PORT_CL1CM_DW0_BC		0x6C000
1863 #define _PORT_CL1CM_DW9_A		0x162024
1864 #define _PORT_CL1CM_DW9_BC		0x6C024
1866 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1869 #define _PORT_CL1CM_DW10_A		0x162028
1870 #define _PORT_CL1CM_DW10_BC		0x6C028
1872 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1875 #define _PORT_CL1CM_DW28_A		0x162070
1876 #define _PORT_CL1CM_DW28_BC		0x6C070
1879 #define   SUS_CLK_CONFIG		0x3
1882 #define _PORT_CL1CM_DW30_A		0x162078
1883 #define _PORT_CL1CM_DW30_BC		0x6C078
1890 #define _ICL_COMBOPHY_A			0x162000
1891 #define _ICL_COMBOPHY_B			0x6C000
1892 #define _EHL_COMBOPHY_C			0x160000
1893 #define _RKL_COMBOPHY_D			0x161000
1894 #define _ADL_COMBOPHY_E			0x16B000
1908 #define   SUS_CLOCK_CONFIG		(3 << 0)
1914 #define  PWR_UP_ALL_LANES		(0x0 << 4)
1915 #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
1916 #define  PWR_DOWN_LN_3_2		(0xc << 4)
1917 #define  PWR_DOWN_LN_3			(0x8 << 4)
1918 #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
1919 #define  PWR_DOWN_LN_1_0		(0x3 << 4)
1920 #define  PWR_DOWN_LN_3_1		(0xa << 4)
1921 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
1922 #define  PWR_DOWN_LN_MASK		(0xf << 4)
1928 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
1931 #define _ICL_PORT_COMP			0x100
1935 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
1941 #define   PROCESS_INFO_DOT_0		(0 << 26)
1946 #define   VOLTAGE_INFO_0_85V		(0 << 24)
1960 #define _ICL_PORT_PCS_AUX		0x300
1961 #define _ICL_PORT_PCS_GRP		0x600
1962 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
1971 #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1972 #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
1973 #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
1975 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
1979 #define _ICL_PORT_TX_AUX		0x380
1980 #define _ICL_PORT_TX_GRP		0x680
1981 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
1992 #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1995 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
1996 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
1997 #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
1999 #define   RCOMP_SCALAR(x)		((x) << 0)
2000 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
2004 #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2008 #define   POST_CURSOR_1_MASK		(0x3F << 12)
2010 #define   POST_CURSOR_2_MASK		(0x3F << 6)
2011 #define   CURSOR_COEFF(x)		((x) << 0)
2012 #define   CURSOR_COEFF_MASK		(0x3F << 0)
2016 #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2021 #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
2023 #define   RTERM_SELECT_MASK		(0x7 << 3)
2027 #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2030 #define   N_SCALAR_MASK			(0x7F << 24)
2034 #define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
2037 …   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2039 #define _ICL_DPHY_CHKN_REG			0x194
2046 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
2047 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
2048 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
2049 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
2050 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
2051 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
2052 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
2053 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
2059 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
2060 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
2061 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
2062 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
2063 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
2064 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
2065 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
2066 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
2073 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
2074 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
2075 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
2076 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
2077 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
2078 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
2079 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
2080 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
2086 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
2087 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
2088 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
2089 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
2090 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
2091 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
2092 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
2093 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
2100 #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
2101 #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
2102 #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
2103 #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
2104 #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
2105 #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
2106 #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
2107 #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
2113 #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
2114 #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
2115 #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
2116 #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
2117 #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
2118 #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
2119 #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
2120 #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
2125 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
2126 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
2128 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
2129 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
2130 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
2131 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
2132 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
2133 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
2134 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
2135 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
2141 #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
2142 #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
2143 #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
2144 #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
2145 #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
2146 #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
2147 #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
2148 #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
2154 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
2157 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
2159 #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
2161 #define MG_CLKHUB_LN0_PORT1			0x16839C
2162 #define MG_CLKHUB_LN1_PORT1			0x16879C
2163 #define MG_CLKHUB_LN0_PORT2			0x16939C
2164 #define MG_CLKHUB_LN1_PORT2			0x16979C
2165 #define MG_CLKHUB_LN0_PORT3			0x16A39C
2166 #define MG_CLKHUB_LN1_PORT3			0x16A79C
2167 #define MG_CLKHUB_LN0_PORT4			0x16B39C
2168 #define MG_CLKHUB_LN1_PORT4			0x16B79C
2175 #define MG_TX_DCC_TX1LN0_PORT1			0x168110
2176 #define MG_TX_DCC_TX1LN1_PORT1			0x168510
2177 #define MG_TX_DCC_TX1LN0_PORT2			0x169110
2178 #define MG_TX_DCC_TX1LN1_PORT2			0x169510
2179 #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
2180 #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
2181 #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
2182 #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
2187 #define MG_TX_DCC_TX2LN0_PORT1			0x168090
2188 #define MG_TX_DCC_TX2LN1_PORT1			0x168490
2189 #define MG_TX_DCC_TX2LN0_PORT2			0x169090
2190 #define MG_TX_DCC_TX2LN1_PORT2			0x169490
2191 #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
2192 #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
2193 #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
2194 #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
2200 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
2203 #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
2204 #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
2205 #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
2206 #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
2207 #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
2208 #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
2209 #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
2210 #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
2221 #define _SNPS_PHY_A_BASE			0x168000
2222 #define _SNPS_PHY_B_BASE			0x169000
2230 							     (reg) + (ln) * 0x10))
2232 #define SNPS_PHY_MPLLB_CP(phy)			_MMIO_SNPS(phy, 0x168000)
2238 #define SNPS_PHY_MPLLB_DIV(phy)			_MMIO_SNPS(phy, 0x168004)
2246 #define SNPS_PHY_MPLLB_FRACN1(phy)		_MMIO_SNPS(phy, 0x168008)
2249 #define   SNPS_PHY_MPLLB_FRACN_DEN		REG_GENMASK(15, 0)
2251 #define SNPS_PHY_MPLLB_FRACN2(phy)		_MMIO_SNPS(phy, 0x16800C)
2253 #define   SNPS_PHY_MPLLB_FRACN_QUOT		REG_GENMASK(15, 0)
2255 #define SNPS_PHY_MPLLB_SSCEN(phy)		_MMIO_SNPS(phy, 0x168014)
2260 #define SNPS_PHY_MPLLB_SSCSTEP(phy)		_MMIO_SNPS(phy, 0x168018)
2263 #define SNPS_PHY_MPLLB_DIV2(phy)		_MMIO_SNPS(phy, 0x16801C)
2267 #define   SNPS_PHY_MPLLB_MULTIPLIER		REG_GENMASK(11, 0)
2269 #define SNPS_PHY_REF_CONTROL(phy)		_MMIO_SNPS(phy, 0x168188)
2272 #define SNPS_PHY_TX_REQ(phy)			_MMIO_SNPS(phy, 0x168200)
2275 #define SNPS_PHY_TX_EQ(ln, phy)			_MMIO_SNPS_LN(ln, phy, 0x168300)
2283 #define _PORT_CL2CM_DW6_A		0x162358
2284 #define _PORT_CL2CM_DW6_BC		0x6C358
2288 #define FIA1_BASE			0x163000
2289 #define FIA2_BASE			0x16E000
2290 #define FIA3_BASE			0x16F000
2295 #define PORT_TX_DFLEXDPMLE1(fia)		_MMIO_FIA((fia),  0x008C0)
2296 #define   DFLEXDPMLE1_DPMLETC_MASK(idx)		(0xf << (4 * (idx)))
2304 #define _PORT_REF_DW3_A			0x16218C
2305 #define _PORT_REF_DW3_BC		0x6C18C
2309 #define _PORT_REF_DW6_A			0x162198
2310 #define _PORT_REF_DW6_BC		0x6C198
2312 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
2314 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
2316 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
2317 #define   GRC_CODE_NOM_MASK		0xFF
2320 #define _PORT_REF_DW8_A			0x1621A0
2321 #define _PORT_REF_DW8_BC		0x6C1A0
2327 #define _PORT_PCS_DW10_LN01_A		0x162428
2328 #define _PORT_PCS_DW10_LN01_B		0x6C428
2329 #define _PORT_PCS_DW10_LN01_C		0x6C828
2330 #define _PORT_PCS_DW10_GRP_A		0x162C28
2331 #define _PORT_PCS_DW10_GRP_B		0x6CC28
2332 #define _PORT_PCS_DW10_GRP_C		0x6CE28
2343 #define _PORT_PCS_DW12_LN01_A		0x162430
2344 #define _PORT_PCS_DW12_LN01_B		0x6C430
2345 #define _PORT_PCS_DW12_LN01_C		0x6C830
2346 #define _PORT_PCS_DW12_LN23_A		0x162630
2347 #define _PORT_PCS_DW12_LN23_B		0x6C630
2348 #define _PORT_PCS_DW12_LN23_C		0x6CA30
2349 #define _PORT_PCS_DW12_GRP_A		0x162c30
2350 #define _PORT_PCS_DW12_GRP_B		0x6CC30
2351 #define _PORT_PCS_DW12_GRP_C		0x6CE30
2353 #define   LANE_STAGGER_MASK		0x1F
2365 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
2366 					  ((lane) & 1) * 0x80)
2368 #define _PORT_TX_DW2_LN0_A		0x162508
2369 #define _PORT_TX_DW2_LN0_B		0x6C508
2370 #define _PORT_TX_DW2_LN0_C		0x6C908
2371 #define _PORT_TX_DW2_GRP_A		0x162D08
2372 #define _PORT_TX_DW2_GRP_B		0x6CD08
2373 #define _PORT_TX_DW2_GRP_C		0x6CF08
2381 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
2383 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
2385 #define _PORT_TX_DW3_LN0_A		0x16250C
2386 #define _PORT_TX_DW3_LN0_B		0x6C50C
2387 #define _PORT_TX_DW3_LN0_C		0x6C90C
2388 #define _PORT_TX_DW3_GRP_A		0x162D0C
2389 #define _PORT_TX_DW3_GRP_B		0x6CD0C
2390 #define _PORT_TX_DW3_GRP_C		0x6CF0C
2400 #define _PORT_TX_DW4_LN0_A		0x162510
2401 #define _PORT_TX_DW4_LN0_B		0x6C510
2402 #define _PORT_TX_DW4_LN0_C		0x6C910
2403 #define _PORT_TX_DW4_GRP_A		0x162D10
2404 #define _PORT_TX_DW4_GRP_B		0x6CD10
2405 #define _PORT_TX_DW4_GRP_C		0x6CF10
2413 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
2415 #define _PORT_TX_DW5_LN0_A		0x162514
2416 #define _PORT_TX_DW5_LN0_B		0x6C514
2417 #define _PORT_TX_DW5_LN0_C		0x6C914
2418 #define _PORT_TX_DW5_GRP_A		0x162D14
2419 #define _PORT_TX_DW5_GRP_B		0x6CD14
2420 #define _PORT_TX_DW5_GRP_C		0x6CF14
2430 #define _PORT_TX_DW14_LN0_A		0x162538
2431 #define _PORT_TX_DW14_LN0_B		0x6C538
2432 #define _PORT_TX_DW14_LN0_C		0x6C938
2441 #define UAIMI_SPR1			_MMIO(0x4F074)
2443 #define SKL_VCCIO_MASK			0x1
2445 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
2455  * [0-7]  @ 0x2000 gen2,gen3
2456  * [8-15] @ 0x3000 945,g33,pnv
2458  * [0-15] @ 0x3000 gen4,gen5
2460  * [0-15] @ 0x100000 gen6,vlv,chv
2461  * [0-31] @ 0x100000 gen7+
2463 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2464 #define   I830_FENCE_START_MASK		0x07f80000
2468 #define   I830_FENCE_REG_VALID		(1 << 0)
2473 #define   I915_FENCE_START_MASK		0x0ff00000
2476 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
2477 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2480 #define   I965_FENCE_REG_VALID		(1 << 0)
2481 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
2483 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
2484 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
2486 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2490 #define TILECTL				_MMIO(0x101000)
2491 #define   TILECTL_SWZCTL			(1 << 0)
2499 #define PGTBL_CTL	_MMIO(0x02020)
2500 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
2501 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
2502 #define PGTBL_ER	_MMIO(0x02024)
2503 #define PRB0_BASE	(0x2030 - 0x30)
2504 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
2505 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
2506 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
2507 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
2508 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
2509 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
2510 #define RENDER_RING_BASE	0x02000
2511 #define BSD_RING_BASE		0x04000
2512 #define GEN6_BSD_RING_BASE	0x12000
2513 #define GEN8_BSD2_RING_BASE	0x1c000
2514 #define GEN11_BSD_RING_BASE	0x1c0000
2515 #define GEN11_BSD2_RING_BASE	0x1c4000
2516 #define GEN11_BSD3_RING_BASE	0x1d0000
2517 #define GEN11_BSD4_RING_BASE	0x1d4000
2518 #define XEHP_BSD5_RING_BASE	0x1e0000
2519 #define XEHP_BSD6_RING_BASE	0x1e4000
2520 #define XEHP_BSD7_RING_BASE	0x1f0000
2521 #define XEHP_BSD8_RING_BASE	0x1f4000
2522 #define VEBOX_RING_BASE		0x1a000
2523 #define GEN11_VEBOX_RING_BASE		0x1c8000
2524 #define GEN11_VEBOX2_RING_BASE		0x1d8000
2525 #define XEHP_VEBOX3_RING_BASE		0x1e8000
2526 #define XEHP_VEBOX4_RING_BASE		0x1f8000
2527 #define BLT_RING_BASE		0x22000
2528 #define RING_TAIL(base)		_MMIO((base) + 0x30)
2529 #define RING_HEAD(base)		_MMIO((base) + 0x34)
2530 #define RING_START(base)	_MMIO((base) + 0x38)
2531 #define RING_CTL(base)		_MMIO((base) + 0x3c)
2533 #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
2534 #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
2535 #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
2549 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
2550 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
2551 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
2552 #define RING_ID(base)		_MMIO((base) + 0x8c)
2553 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
2554 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
2557 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2559 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2561 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
2562 #define   GTT_CACHE_EN_ALL	0xF0007FFF
2563 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
2564 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
2565 #define ARB_MODE		_MMIO(0x4030)
2568 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
2569 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
2571 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
2573 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
2574 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
2576 #define GAMTARBMODE		_MMIO(0x04a08)
2579 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
2581 #define _RING_FAULT_REG_RCS        0x4094
2582 #define _RING_FAULT_REG_VCS        0x4194
2583 #define _RING_FAULT_REG_BCS        0x4294
2584 #define _RING_FAULT_REG_VECS       0x4394
2590 #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
2591 #define GEN12_RING_FAULT_REG	_MMIO(0xcec4)
2592 #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
2594 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
2595 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2596 #define   RING_FAULT_VALID	(1 << 0)
2597 #define DONE_REG		_MMIO(0x40b0)
2598 #define GEN12_GAM_DONE		_MMIO(0xcf68)
2599 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
2600 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
2601 #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
2602 #define GEN12_PAT_INDEX(index)	_MMIO(0x4800 + (index) * 4)
2603 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
2604 #define GEN12_GFX_CCS_AUX_NV	_MMIO(0x4208)
2605 #define GEN12_VD0_AUX_NV	_MMIO(0x4218)
2606 #define GEN12_VD1_AUX_NV	_MMIO(0x4228)
2607 #define GEN12_VD2_AUX_NV	_MMIO(0x4298)
2608 #define GEN12_VD3_AUX_NV	_MMIO(0x42A8)
2609 #define GEN12_VE0_AUX_NV	_MMIO(0x4238)
2610 #define GEN12_VE1_AUX_NV	_MMIO(0x42B8)
2611 #define   AUX_INV		REG_BIT(0)
2612 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
2613 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
2614 #define RING_ACTHD(base)	_MMIO((base) + 0x74)
2615 #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
2616 #define RING_NOPID(base)	_MMIO((base) + 0x94)
2617 #define RING_IMR(base)		_MMIO((base) + 0xa8)
2618 #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
2619 #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
2620 #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
2621 #define   TAIL_ADDR		0x001FFFF8
2622 #define   HEAD_WRAP_COUNT	0xFFE00000
2623 #define   HEAD_WRAP_ONE		0x00200000
2624 #define   HEAD_ADDR		0x001FFFFC
2625 #define   RING_NR_PAGES		0x001FF000
2626 #define   RING_REPORT_MASK	0x00000006
2627 #define   RING_REPORT_64K	0x00000002
2628 #define   RING_REPORT_128K	0x00000004
2629 #define   RING_NO_REPORT	0x00000000
2630 #define   RING_VALID_MASK	0x00000001
2631 #define   RING_VALID		0x00000001
2632 #define   RING_INVALID		0x00000000
2633 #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
2638 #define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)
2639 #define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)
2641 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2643 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
2648 #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
2649 #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
2650 #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
2651 #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
2652 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
2658 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
2660 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2663 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2664 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2667 #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
2672 #if 0
2673 #define PRB0_TAIL	_MMIO(0x2030)
2674 #define PRB0_HEAD	_MMIO(0x2034)
2675 #define PRB0_START	_MMIO(0x2038)
2676 #define PRB0_CTL	_MMIO(0x203c)
2677 #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
2678 #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
2679 #define PRB1_START	_MMIO(0x2048) /* 915+ only */
2680 #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2682 #define IPEIR_I965	_MMIO(0x2064)
2683 #define IPEHR_I965	_MMIO(0x2068)
2684 #define GEN7_SC_INSTDONE	_MMIO(0x7100)
2685 #define GEN12_SC_INSTDONE_EXTRA		_MMIO(0x7104)
2686 #define GEN12_SC_INSTDONE_EXTRA2	_MMIO(0x7108)
2687 #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
2688 #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
2689 #define MCFG_MCR_SELECTOR		_MMIO(0xfd0)
2690 #define SF_MCR_SELECTOR			_MMIO(0xfd8)
2691 #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
2696 #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
2697 #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
2698 #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
2699 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
2700 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
2701 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
2702 #define RING_EIR(base)		_MMIO((base) + 0xb0)
2703 #define RING_EMR(base)		_MMIO((base) + 0xb4)
2704 #define RING_ESR(base)		_MMIO((base) + 0xb8)
2710 #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
2711 #define RING_INSTPS(base)	_MMIO((base) + 0x70)
2712 #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
2713 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
2714 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
2715 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
2716 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2717 #define INSTPS		_MMIO(0x2070) /* 965+ only */
2718 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2719 #define ACTHD_I965	_MMIO(0x2074)
2720 #define HWS_PGA		_MMIO(0x2080)
2721 #define HWS_ADDRESS_MASK	0xfffff000
2723 #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2724 #define   PWRCTX_EN	(1 << 0)
2725 #define IPEIR(base)	_MMIO((base) + 0x88)
2726 #define IPEHR(base)	_MMIO((base) + 0x8c)
2727 #define GEN2_INSTDONE	_MMIO(0x2090)
2728 #define NOPID		_MMIO(0x2094)
2729 #define HWSTAM		_MMIO(0x2098)
2730 #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
2731 #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
2733 #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
2734 #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
2735 #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
2736 #define RING_BBADDR(base)	_MMIO((base) + 0x140)
2737 #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
2738 #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
2739 #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
2740 #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
2741 #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
2743 #define VDBOX_CGCTL3F10(base)		_MMIO((base) + 0x3f10)
2746 #define ERROR_GEN6	_MMIO(0x40a0)
2747 #define GEN7_ERR_INT	_MMIO(0x44040)
2756 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
2759 #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
2760 #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
2761 #define GEN12_FAULT_TLB_DATA0		_MMIO(0xceb8)
2762 #define GEN12_FAULT_TLB_DATA1		_MMIO(0xcebc)
2763 #define   FAULT_VA_HIGH_BITS		(0xf << 0)
2766 #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
2768 #define FPGA_DBG		_MMIO(0x42300)
2771 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
2774 #define   CLAIM_ER_CTR_MASK	0xffff
2776 #define DERRMR		_MMIO(0x44050)
2778 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
2800 #define _3D_CHICKEN	_MMIO(0x2084)
2802 #define _3D_CHICKEN2	_MMIO(0x208c)
2804 #define FF_SLICE_CHICKEN	_MMIO(0x2088)
2812 #define _3D_CHICKEN3	_MMIO(0x2090)
2820 #define MI_MODE		_MMIO(0x209c)
2827 #define GEN6_GT_MODE	_MMIO(0x20d0)
2828 #define GEN7_GT_MODE	_MMIO(0x7008)
2830 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
2831 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
2832 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
2835 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
2839 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2844 #define GEN8_STATE_ACK		_MMIO(0x20F0)
2845 #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
2846 #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
2855 #define GFX_MODE	_MMIO(0x2520)
2856 #define GFX_MODE_GEN7	_MMIO(0x229c)
2857 #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
2868 #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
2874 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
2875 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
2876 #define SCPD0		_MMIO(0x209c) /* 915+ only */
2879 #define GEN2_IER	_MMIO(0x20a0)
2880 #define GEN2_IIR	_MMIO(0x20a4)
2881 #define GEN2_IMR	_MMIO(0x20a8)
2882 #define GEN2_ISR	_MMIO(0x20ac)
2883 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
2886 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
2887 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
2888 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
2889 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
2890 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
2891 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
2892 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
2896 #define EIR		_MMIO(0x20b0)
2897 #define EMR		_MMIO(0x20b4)
2898 #define ESR		_MMIO(0x20b8)
2904 #define   I915_ERROR_INSTRUCTION			(1 << 0)
2905 #define INSTPM	        _MMIO(0x20c0)
2913 #define ACTHD(base)	_MMIO((base) + 0xc8)
2914 #define MEM_MODE	_MMIO(0x20cc)
2918 #define FW_BLC		_MMIO(0x20d8)
2919 #define FW_BLC2		_MMIO(0x20dc)
2920 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2924 #define MM_BURST_LENGTH     0x00700000
2925 #define MM_FIFO_WATERMARK   0x0001F000
2926 #define LM_BURST_LENGTH     0x00000700
2927 #define LM_FIFO_WATERMARK   0x0000001F
2928 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2930 #define _MBUS_ABOX0_CTL			0x45038
2931 #define _MBUS_ABOX1_CTL			0x45048
2932 #define _MBUS_ABOX2_CTL			0x4504C
2938 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
2940 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
2942 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
2943 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
2945 #define _PIPEA_MBUS_DBOX_CTL		0x7003C
2946 #define _PIPEB_MBUS_DBOX_CTL		0x7103C
2951 #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
2953 #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
2954 #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
2956 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
2957 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
2958 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
2960 #define MBUS_CTL			_MMIO(0x4438C)
2963 #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
2969 #define HDPORT_STATE			_MMIO(0x45050)
2972 #define   HDPORT_ENABLED		REG_BIT(0)
2989 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
3016 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
3026 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
3033 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
3034 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
3036 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
3038 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
3040 #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
3048 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3049 #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
3050 #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
3051 #define   GFX_FLSH_CNTL_EN	(1 << 0)
3052 #define ECOSKPD		_MMIO(0x21d0)
3055 #define   ECO_FLIP_DONE		(1 << 0)
3057 #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
3058 #define RC_OP_FLUSH_ENABLE (1 << 0)
3060 #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
3065 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
3069 #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
3070 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
3075 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3076 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3078 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
3082 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
3084 #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
3085 #define   HSW_F1_EU_DIS_10EUS		0
3089 #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
3093 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3095 #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3097 #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3099 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3101 #define GEN8_FUSE2			_MMIO(0x9120)
3103 #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
3105 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
3108 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
3111 #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
3113 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
3115 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
3117 #define GEN10_L3BANK_MASK   0x0F
3120 #define GEN12_MEML3_EN_MASK 0x0F
3122 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
3123 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
3125 #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
3127 #define GEN8_EU_DISABLE1		_MMIO(0x9138)
3128 #define   GEN8_EU_DIS1_S1_MASK		0xffff
3130 #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
3132 #define GEN8_EU_DISABLE2		_MMIO(0x913c)
3133 #define   GEN8_EU_DIS2_S2_MASK		0xff
3135 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
3137 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
3138 #define   GEN10_EU_DIS_SS_MASK		0xff
3140 #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
3141 #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
3143 #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3145 #define GEN11_EU_DISABLE _MMIO(0x9134)
3146 #define GEN11_EU_DIS_MASK 0xFF
3148 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3149 #define GEN11_GT_S_ENA_MASK 0xFF
3151 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3153 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3155 #define XEHP_EU_ENABLE			_MMIO(0x9134)
3156 #define XEHP_EU_ENA_MASK		0xFF
3158 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
3159 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
3188 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
3195 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3233 #define I915_ASLE_INTERRUPT				(1 << 0)
3236 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
3237 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
3240 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
3241 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
3243 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
3244 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
3245 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
3252 #define GEN6_BSD_RNCID			_MMIO(0x12198)
3254 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
3255 #define   GEN7_FF_SCHED_MASK		0x0077070
3258 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
3259 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
3260 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
3261 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
3263 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
3264 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
3265 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
3266 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
3267 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
3268 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
3269 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
3270 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
3276 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
3277 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
3278 #define FBC_CONTROL		_MMIO(0x3208)
3288 #define   FBC_CTL_FENCENO_MASK	REG_GENMASK(3, 0)
3290 #define FBC_COMMAND		_MMIO(0x320c)
3291 #define   FBC_CMD_COMPRESS	(1 << 0)
3292 #define FBC_STATUS		_MMIO(0x3210)
3296 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
3297 #define FBC_CONTROL2		_MMIO(0x3214)
3298 #define   FBC_CTL_FENCE_DBL	(0 << 4)
3299 #define   FBC_CTL_IDLE_IMM	(0 << 2)
3304 #define   FBC_CTL_PLANE(plane)	((plane) << 0)
3305 #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
3306 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
3310 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
3314 #define DPFC_CB_BASE		_MMIO(0x3200)
3315 #define DPFC_CONTROL		_MMIO(0x3208)
3323 #define   DPFC_CTL_LIMIT_1X	(0 << 6)
3326 #define DPFC_RECOMP_CTL		_MMIO(0x320c)
3329 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3330 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3331 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3332 #define DPFC_STATUS		_MMIO(0x3210)
3334 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
3335 #define   DPFC_COMP_SEG_SHIFT	(0)
3336 #define   DPFC_COMP_SEG_MASK	(0x000007ff)
3337 #define DPFC_STATUS2		_MMIO(0x3214)
3338 #define DPFC_FENCE_YOFF		_MMIO(0x3218)
3339 #define DPFC_CHICKEN		_MMIO(0x3224)
3343 #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
3344 #define ILK_DPFC_CONTROL	_MMIO(0x43208)
3347 #define   DPFC_RESERVED		(0x1FFFFF00)
3348 #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
3349 #define ILK_DPFC_STATUS		_MMIO(0x43210)
3350 #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3351 #define IVB_FBC_STATUS2		_MMIO(0x43214)
3352 #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3353 #define  BDW_FBC_COMP_SEG_MASK	0xfff
3354 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
3355 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
3359 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
3360 #define   ILK_FBC_RT_VALID	(1 << 0)
3363 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
3368 #define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
3373 #define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
3384 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
3386 #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
3389 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
3390 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
3392 #define IPS_CTL		_MMIO(0x43408)
3395 #define MSG_FBC_REND_STATE	_MMIO(0x50380)
3402 #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3405 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
3406 # define GPIO_CLOCK_DIR_IN		(0 << 1)
3413 # define GPIO_DATA_DIR_IN		(0 << 9)
3420 #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3422 #define   GMBUS_RATE_100KHZ	(0 << 8)
3429 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3433 #define   GMBUS_CYCLE_NONE	(0 << 25)
3442 #define   GMBUS_SLAVE_READ	(1 << 0)
3443 #define   GMBUS_SLAVE_WRITE	(0 << 0)
3444 #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3452 #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3453 #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3458 #define   GMBUS_HW_RDY_EN	(1 << 0)
3459 #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3465 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3466 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3467 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3470 #define VGA0	_MMIO(0x6000)
3471 #define VGA1	_MMIO(0x6004)
3472 #define VGA_PD	_MMIO(0x6010)
3475 #define   VGA0_PD_P1_SHIFT	0
3476 #define   VGA0_PD_P1_MASK	(0x1f << 0)
3480 #define   VGA1_PD_P1_MASK	(0x1f << 8)
3491 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3493 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
3495 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
3496 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
3497 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3502 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
3503 #define   DPLL_PORTB_READY_MASK		(0xf)
3505 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
3508 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
3509 #define   DPLL_PORTD_READY_MASK		(0xf)
3510 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3512 #define   PHY_LDO_DELAY_0NS			0x0
3513 #define   PHY_LDO_DELAY_200NS			0x1
3514 #define   PHY_LDO_DELAY_600NS			0x2
3517 #define   PHY_CH_SU_PSR				0x1
3518 #define   PHY_CH_DEEP_PSR			0x7
3521 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3530 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
3536 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
3546 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3547 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3555 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3560 #define   SDVO_MULTIPLIER_MASK			0x000000ff
3562 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
3564 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3565 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3566 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3574 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
3577 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
3596 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
3603 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
3604 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3606 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
3608 #define _FPA0	0x6040
3609 #define _FPA1	0x6044
3610 #define _FPB0	0x6048
3611 #define _FPB1	0x604c
3614 #define   FP_N_DIV_MASK		0x003f0000
3615 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
3617 #define   FP_M1_DIV_MASK	0x00003f00
3619 #define   FP_M2_DIV_MASK	0x0000003f
3620 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
3621 #define   FP_M2_DIV_SHIFT		 0
3622 #define DPLL_TEST	_MMIO(0x606c)
3623 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
3632 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
3633 #define D_STATE		_MMIO(0x6104)
3637 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
3638 #define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3675 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
3676 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
3678 #define RENCLK_GATE_D1		_MMIO(0x6204)
3694 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
3711 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
3740 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
3742 #define RENCLK_GATE_D2		_MMIO(0x6208)
3747 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
3750 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
3751 #define DEUC			_MMIO(0x6214)          /* CRL only */
3753 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3756 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
3758 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
3760 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
3761 #define   CZCLK_FREQ_MASK	0xf
3763 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
3770 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
3775 #define _PALETTE_A		0xa000
3776 #define _PALETTE_B		0xa800
3777 #define _CHV_PALETTE_C		0xc000
3780 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
3792  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3798 #define MCHBAR_MIRROR_BASE	0x10000
3800 #define MCHBAR_MIRROR_BASE_SNB	0x140000
3802 #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
3803 #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
3804 #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
3805 #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
3806 #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
3809 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3812 #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
3813 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
3814 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
3815 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
3816 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
3819 #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
3823 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3827 #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
3828 #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
3831 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3832 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3833 #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3834 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
3835 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
3836 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
3837 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
3838 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
3839 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
3840 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
3841 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
3842 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
3843 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
3844 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
3845 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
3848 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
3849 #define   MAD_DIMM_A_SIZE_SHIFT		0
3850 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
3853 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3854 #define   MCH_SSKPD_WM0_MASK		0x3f
3855 #define   MCH_SSKPD_WM0_VAL		0xc
3858 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3859 #define CLKCFG_FSB_400					(0 << 0)	/* hrawclk 100 */
3860 #define CLKCFG_FSB_400_ALT				(5 << 0)	/* hrawclk 100 */
3861 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
3862 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
3863 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
3864 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
3865 #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
3866 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
3867 #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
3868 #define CLKCFG_FSB_1600_ALT				(6 << 0)	/* hrawclk 400 */
3869 #define CLKCFG_FSB_MASK					(7 << 0)
3875 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3876 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3878 #define TSC1			_MMIO(0x11001)
3879 #define   TSE			(1 << 0)
3880 #define TR1			_MMIO(0x11006)
3881 #define TSFS			_MMIO(0x11020)
3882 #define   TSFS_SLOPE_MASK	0x0000ff00
3884 #define   TSFS_INTR_MASK	0x000000ff
3886 #define CRSTANDVID		_MMIO(0x11100)
3887 #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3888 #define   PXVFREQ_PX_MASK	0x7f000000
3890 #define VIDFREQ_BASE		_MMIO(0x11110)
3891 #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3892 #define VIDFREQ2		_MMIO(0x11114)
3893 #define VIDFREQ3		_MMIO(0x11118)
3894 #define VIDFREQ4		_MMIO(0x1111c)
3895 #define   VIDFREQ_P0_MASK	0x1f000000
3897 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
3899 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
3901 #define   VIDFREQ_P1_MASK	0x00001f00
3903 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
3905 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
3906 #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
3907 #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3909 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
3911 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
3913 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
3914 #define   INTTOEXT_MAP0_SHIFT	0
3915 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
3916 #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
3917 #define   MEMCTL_CMD_MASK	0xe000
3919 #define   MEMCTL_CMD_RCLK_OFF	0
3927 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
3930 #define   MEMCTL_TGT_VID_MASK	0x007f
3931 #define MEMIHYST		_MMIO(0x1117c)
3932 #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
3941 #define   MEMINT_SW_CMD_EN	(1 << 0)
3942 #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
3943 #define   MEM_RSEXIT_MASK	0xc000
3945 #define   MEM_CONT_BUSY_MASK	0x3000
3947 #define   MEM_AVG_BUSY_MASK	0x0c00
3949 #define   MEM_EVAL_CHG_MASK	0x0300
3951 #define   MEM_MON_IDLE_MASK	0x00c0
3953 #define   MEM_UP_EVAL_MASK	0x0030
3955 #define   MEM_DOWN_EVAL_MASK	0x000c
3957 #define   MEM_SW_CMD_MASK	0x0003
3958 #define   MEM_INT_STEER_GFX	0
3962 #define MEMINTRSTS		_MMIO(0x11184)
3970 #define   MEMINT_SW_CMD		(1 << 0)
3971 #define MEMMODECTL		_MMIO(0x11190)
3973 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3975 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3977 #define   MEMMODE_IDLE_MODE_EVAL 0
3983 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
3985 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
3987 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
3988 #define RCBMAXAVG		_MMIO(0x1119c)
3989 #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
3990 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
3998 #define   SWFREQ_MASK		0x0380 /* P0-7 */
4000 #define   TARVID_MASK		0x001f
4001 #define MEMSTAT_CTG		_MMIO(0x111a0)
4002 #define RCBMINAVG		_MMIO(0x111a0)
4003 #define RCUPEI			_MMIO(0x111b0)
4004 #define RCDNEI			_MMIO(0x111b4)
4005 #define RSTDBYCTL		_MMIO(0x111b8)
4016 #define   RSX_STATUS_ON		(0 << 20)
4029 #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
4034 #define   SLOW_RS123		(0 << 12)
4038 #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
4041 #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
4043 #define   RS_CSTATE_C367_RS1	(0 << 4)
4049 #define VIDCTL			_MMIO(0x111c0)
4050 #define VIDSTS			_MMIO(0x111c8)
4051 #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
4052 #define MEMSTAT_ILK		_MMIO(0x111f8)
4053 #define   MEMSTAT_VID_MASK	0x7f00
4055 #define   MEMSTAT_PSTATE_MASK	0x00f8
4058 #define   MEMSTAT_SRC_CTL_MASK	0x0003
4059 #define   MEMSTAT_SRC_CTL_CORE	0
4063 #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
4064 #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
4065 #define PMMISC			_MMIO(0x11214)
4066 #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
4067 #define SDEW			_MMIO(0x1124c)
4068 #define CSIEW0			_MMIO(0x11250)
4069 #define CSIEW1			_MMIO(0x11254)
4070 #define CSIEW2			_MMIO(0x11258)
4071 #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
4072 #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
4073 #define MCHAFE			_MMIO(0x112c0)
4074 #define CSIEC			_MMIO(0x112e0)
4075 #define DMIEC			_MMIO(0x112e4)
4076 #define DDREC			_MMIO(0x112e8)
4077 #define PEG0EC			_MMIO(0x112ec)
4078 #define PEG1EC			_MMIO(0x112f0)
4079 #define GFXEC			_MMIO(0x112f4)
4080 #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
4081 #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
4082 #define ECR			_MMIO(0x11600)
4085 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
4086 #define OGW0			_MMIO(0x11608)
4087 #define OGW1			_MMIO(0x1160c)
4088 #define EG0			_MMIO(0x11610)
4089 #define EG1			_MMIO(0x11614)
4090 #define EG2			_MMIO(0x11618)
4091 #define EG3			_MMIO(0x1161c)
4092 #define EG4			_MMIO(0x11620)
4093 #define EG5			_MMIO(0x11624)
4094 #define EG6			_MMIO(0x11628)
4095 #define EG7			_MMIO(0x1162c)
4096 #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
4097 #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
4098 #define LCFUSE02		_MMIO(0x116c0)
4099 #define   LCFUSE_HIV_MASK	0x000000ff
4100 #define CSIPLL0			_MMIO(0x12c10)
4101 #define DDRMPLL1		_MMIO(0X12c20)
4102 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
4104 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4105 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4107 #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4108 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4109 #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4110 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4111 #define   RP0_CAP_MASK		REG_GENMASK(7, 0)
4114 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
4115 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
4120 #define CCID(base)			_MMIO((base) + 0x180)
4121 #define   CCID_EN			BIT(0)
4137 #define CXT_SIZE		_MMIO(0x21a0)
4138 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
4139 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
4140 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
4141 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
4142 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
4146 #define GEN7_CXT_SIZE		_MMIO(0x21a8)
4147 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
4148 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
4149 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
4150 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
4151 #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
4152 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
4157 	INTEL_ADVANCED_CONTEXT = 0,
4164 	FAULT_AND_HANG = 0,
4171 #define GEN8_CTX_VALID (1 << 0)
4192 #define CHV_CLK_CTL1			_MMIO(0x101100)
4193 #define VLV_CLK_CTL2			_MMIO(0x101104)
4200 #define OVADD			_MMIO(0x30000)
4201 #define DOVSTA			_MMIO(0x30008)
4202 #define OC_BUF			(0x3 << 20)
4203 #define OGAMC5			_MMIO(0x30010)
4204 #define OGAMC4			_MMIO(0x30014)
4205 #define OGAMC3			_MMIO(0x30018)
4206 #define OGAMC2			_MMIO(0x3001c)
4207 #define OGAMC1			_MMIO(0x30020)
4208 #define OGAMC0			_MMIO(0x30024)
4213 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
4218 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
4222 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
4225 #define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
4228 #define _CLKGATE_DIS_PSL_A		0x46520
4229 #define _CLKGATE_DIS_PSL_B		0x46524
4230 #define _CLKGATE_DIS_PSL_C		0x46528
4244 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
4251 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
4254 #define SUBSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x9528)
4257 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
4262 #define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
4266 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
4274 #define _PIPE_CRC_CTL_A			0x60050
4277 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
4286 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
4290 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
4297 #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
4305 #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
4317 #define _PIPE_CRC_RES_1_A_IVB		0x60064
4318 #define _PIPE_CRC_RES_2_A_IVB		0x60068
4319 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
4320 #define _PIPE_CRC_RES_4_A_IVB		0x60070
4321 #define _PIPE_CRC_RES_5_A_IVB		0x60074
4323 #define _PIPE_CRC_RES_RED_A		0x60060
4324 #define _PIPE_CRC_RES_GREEN_A		0x60064
4325 #define _PIPE_CRC_RES_BLUE_A		0x60068
4326 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
4327 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4330 #define _PIPE_CRC_RES_1_B_IVB		0x61064
4331 #define _PIPE_CRC_RES_2_B_IVB		0x61068
4332 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
4333 #define _PIPE_CRC_RES_4_B_IVB		0x61070
4334 #define _PIPE_CRC_RES_5_B_IVB		0x61074
4350 #define _HTOTAL_A	0x60000
4351 #define _HBLANK_A	0x60004
4352 #define _HSYNC_A	0x60008
4353 #define _VTOTAL_A	0x6000c
4354 #define _VBLANK_A	0x60010
4355 #define _VSYNC_A	0x60014
4356 #define _EXITLINE_A	0x60018
4357 #define _PIPEASRC	0x6001c
4358 #define _BCLRPAT_A	0x60020
4359 #define _VSYNCSHIFT_A	0x60028
4360 #define _PIPE_MULT_A	0x6002c
4363 #define _HTOTAL_B	0x61000
4364 #define _HBLANK_B	0x61004
4365 #define _HSYNC_B	0x61008
4366 #define _VTOTAL_B	0x6100c
4367 #define _VBLANK_B	0x61010
4368 #define _VSYNC_B	0x61014
4369 #define _PIPEBSRC	0x6101c
4370 #define _BCLRPAT_B	0x61020
4371 #define _VSYNCSHIFT_B	0x61028
4372 #define _PIPE_MULT_B	0x6102c
4374 /* DSI 0 timing regs */
4375 #define _HTOTAL_DSI0		0x6b000
4376 #define _HSYNC_DSI0		0x6b008
4377 #define _VTOTAL_DSI0		0x6b00c
4378 #define _VSYNC_DSI0		0x6b014
4379 #define _VSYNCSHIFT_DSI0	0x6b028
4382 #define _HTOTAL_DSI1		0x6b800
4383 #define _HSYNC_DSI1		0x6b808
4384 #define _VTOTAL_DSI1		0x6b80c
4385 #define _VSYNC_DSI1		0x6b814
4386 #define _VSYNCSHIFT_DSI1	0x6b828
4388 #define TRANSCODER_A_OFFSET 0x60000
4389 #define TRANSCODER_B_OFFSET 0x61000
4390 #define TRANSCODER_C_OFFSET 0x62000
4391 #define CHV_TRANSCODER_C_OFFSET 0x63000
4392 #define TRANSCODER_D_OFFSET 0x63000
4393 #define TRANSCODER_EDP_OFFSET 0x6f000
4394 #define TRANSCODER_DSI0_OFFSET	0x6b000
4395 #define TRANSCODER_DSI1_OFFSET	0x6b800
4410 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
4411 #define   EXITLINE_SHIFT	0
4414 #define _TRANS_VRR_CTL_A		0x60420
4415 #define _TRANS_VRR_CTL_B		0x61420
4416 #define _TRANS_VRR_CTL_C		0x62420
4417 #define _TRANS_VRR_CTL_D		0x63420
4424 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
4425 #define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
4428 #define _TRANS_VRR_VMAX_A		0x60424
4429 #define _TRANS_VRR_VMAX_B		0x61424
4430 #define _TRANS_VRR_VMAX_C		0x62424
4431 #define _TRANS_VRR_VMAX_D		0x63424
4433 #define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
4435 #define _TRANS_VRR_VMIN_A		0x60434
4436 #define _TRANS_VRR_VMIN_B		0x61434
4437 #define _TRANS_VRR_VMIN_C		0x62434
4438 #define _TRANS_VRR_VMIN_D		0x63434
4440 #define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
4442 #define _TRANS_VRR_VMAXSHIFT_A		0x60428
4443 #define _TRANS_VRR_VMAXSHIFT_B		0x61428
4444 #define _TRANS_VRR_VMAXSHIFT_C		0x62428
4445 #define _TRANS_VRR_VMAXSHIFT_D		0x63428
4450 #define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
4452 #define _TRANS_VRR_STATUS_A		0x6042C
4453 #define _TRANS_VRR_STATUS_B		0x6142C
4454 #define _TRANS_VRR_STATUS_C		0x6242C
4455 #define _TRANS_VRR_STATUS_D		0x6342C
4464 #define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4472 #define _TRANS_VRR_VTOTAL_PREV_A	0x60480
4473 #define _TRANS_VRR_VTOTAL_PREV_B	0x61480
4474 #define _TRANS_VRR_VTOTAL_PREV_C	0x62480
4475 #define _TRANS_VRR_VTOTAL_PREV_D	0x63480
4481 #define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
4483 #define _TRANS_VRR_FLIPLINE_A		0x60438
4484 #define _TRANS_VRR_FLIPLINE_B		0x61438
4485 #define _TRANS_VRR_FLIPLINE_C		0x62438
4486 #define _TRANS_VRR_FLIPLINE_D		0x63438
4489 #define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
4491 #define _TRANS_VRR_STATUS2_A		0x6043C
4492 #define _TRANS_VRR_STATUS2_B		0x6143C
4493 #define _TRANS_VRR_STATUS2_C		0x6243C
4494 #define _TRANS_VRR_STATUS2_D		0x6343C
4496 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
4498 #define _TRANS_PUSH_A			0x60A70
4499 #define _TRANS_PUSH_B			0x61A70
4500 #define _TRANS_PUSH_C			0x62A70
4501 #define _TRANS_PUSH_D			0x63A70
4509  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4512 #define _HSW_EDP_PSR_BASE			0x64800
4513 #define _SRD_CTL_A				0x60800
4514 #define _SRD_CTL_EDP				0x6f800
4522 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
4528 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
4531 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
4536 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
4540 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
4543  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4547 #define EDP_PSR_IMR				_MMIO(0x64834)
4548 #define EDP_PSR_IIR				_MMIO(0x64838)
4549 #define _PSR_IMR_A				0x60814
4550 #define _PSR_IIR_A				0x60818
4554 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
4555 #define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4556 #define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4557 #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4558 #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4560 #define _SRD_AUX_CTL_A				0x60810
4561 #define _SRD_AUX_CTL_EDP			0x6f810
4564 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
4565 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
4567 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
4569 #define _SRD_AUX_DATA_A				0x60814
4570 #define _SRD_AUX_DATA_EDP			0x6f814
4573 #define _SRD_STATUS_A				0x60840
4574 #define _SRD_STATUS_EDP				0x6f840
4578 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
4586 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
4590 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
4592 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
4598 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
4600 #define _SRD_PERF_CNT_A			0x60844
4601 #define _SRD_PERF_CNT_EDP		0x6f844
4603 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
4606 #define _SRD_DEBUG_A				0x60860
4607 #define _SRD_DEBUG_EDP				0x6f860
4616 #define _PSR2_CTL_A				0x60900
4617 #define _PSR2_CTL_EDP				0x6f900
4621 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
4626 #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
4641 #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
4647 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK		(0xf << 4)
4649 #define   EDP_PSR2_IDLE_FRAME_MASK		0xf
4650 #define   EDP_PSR2_IDLE_FRAME_SHIFT		0
4652 #define _PSR_EVENT_TRANS_A			0x60848
4653 #define _PSR_EVENT_TRANS_B			0x61848
4654 #define _PSR_EVENT_TRANS_C			0x62848
4655 #define _PSR_EVENT_TRANS_D			0x63848
4656 #define _PSR_EVENT_TRANS_EDP			0x6f848
4673 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
4675 #define _PSR2_STATUS_A			0x60940
4676 #define _PSR2_STATUS_EDP		0x6f940
4678 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4681 #define _PSR2_SU_STATUS_A		0x60914
4682 #define _PSR2_SU_STATUS_EDP		0x6f914
4686 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4689 #define _PSR2_MAN_TRK_CTL_A					0x60910
4690 #define _PSR2_MAN_TRK_CTL_EDP					0x6f910
4702 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
4708 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
4709 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
4710 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
4711 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
4712 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
4713 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
4714 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
4715 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
4716 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
4717 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
4718 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
4719 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
4734 #define RC_MIN_QP_SHIFT				0
4736 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
4737 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
4738 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
4739 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
4740 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
4741 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
4742 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
4743 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
4744 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
4745 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
4746 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
4747 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
4761 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
4762 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
4763 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
4764 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
4765 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
4766 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
4767 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
4768 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
4769 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
4770 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
4771 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
4772 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
4786 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
4787 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
4788 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
4789 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
4790 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
4791 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
4792 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
4793 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
4794 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
4795 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
4796 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
4797 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
4812 #define ADPA			_MMIO(0x61100)
4813 #define PCH_ADPA                _MMIO(0xe1100)
4814 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
4817 #define   ADPA_DAC_DISABLE	0
4824 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4825 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4830 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4832 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4834 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4836 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4840 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4844 #define   ADPA_SETS_HVPOLARITY	0
4846 #define   ADPA_VSYNC_CNTL_ENABLE 0
4848 #define   ADPA_HSYNC_CNTL_ENABLE 0
4850 #define   ADPA_VSYNC_ACTIVE_LOW	0
4852 #define   ADPA_HSYNC_ACTIVE_LOW	0
4854 #define   ADPA_DPMS_ON		(0 << 10)
4861 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4876 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
4879 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
4881 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
4886 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
4888 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
4891 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4922 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4957 #define _GEN3_SDVOB	0x61140
4958 #define _GEN3_SDVOC	0x61160
4963 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
4964 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
4965 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
4966 #define PCH_SDVOB	_MMIO(0xe1140)
4968 #define PCH_HDMIC	_MMIO(0xe1150)
4969 #define PCH_HDMID	_MMIO(0xe1160)
4971 #define PORT_DFT_I9XX				_MMIO(0x61150)
4973 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4975 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
4978 #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
5007 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
5009 #define   SDVO_ENCODING_SDVO			(0 << 10)
5012 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
5035 #define _DVOA			0x61120
5037 #define _DVOB			0x61140
5039 #define _DVOC			0x61160
5045 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
5050 #define   DVO_DATA_ORDER_I740		(0 << 14)
5058 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
5059 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
5065 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
5066 #define   DVO_PRESERVE_MASK		(0x7 << 24)
5067 #define DVOA_SRCDIM		_MMIO(0x61124)
5068 #define DVOB_SRCDIM		_MMIO(0x61144)
5069 #define DVOC_SRCDIM		_MMIO(0x61164)
5071 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
5074 #define LVDS			_MMIO(0x61180)
5100 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
5108 #define   LVDS_A3_POWER_DOWN		(0 << 6)
5115 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
5123 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
5127 #define VIDEO_DIP_DATA		_MMIO(0x61178)
5135 #define VIDEO_DIP_CTL		_MMIO(0x61170)
5145 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
5150 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
5157 #define   VSC_SELECT_MASK		(0x3 << 25)
5159 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
5169 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
5172 #define PPS_BASE			0x61200
5174 #define PCH_PPS_BASE			0xC7200
5178 					      (pps_idx) * 0x100)
5180 #define _PP_STATUS			0x61200
5192 #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5196 #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
5197 #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5198 #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5199 #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5200 #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5201 #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5202 #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5203 #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5204 #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5205 #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
5207 #define _PP_CONTROL			0x61204
5210 #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
5215 #define  PANEL_POWER_ON			REG_BIT(0)
5217 #define _PP_ON_DELAYS			0x61208
5220 #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5226 #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
5228 #define _PP_OFF_DELAYS			0x6120C
5231 #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
5233 #define _PP_DIVISOR			0x61210
5236 #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
5239 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
5244 #define   VERT_INTERP_DISABLE	(0 << 10)
5248 #define   HORIZ_INTERP_DISABLE	(0 << 6)
5253 #define   PFIT_FILTER_FUZZY	(0 << 24)
5254 #define   PFIT_SCALING_AUTO	(0 << 26)
5258 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
5261 #define		PFIT_VERT_SCALE_MASK		0xfff00000
5263 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
5266 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
5267 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
5268 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
5270 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
5272 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5273 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
5277 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5278 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
5282 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5283 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
5288 #define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
5293 #define   BLM_PIPE_A			(0 << 29)
5306 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
5308 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
5309 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
5310 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
5311 #define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5319 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
5328 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
5329 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
5330 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
5331 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
5333 #define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5338 #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
5339 #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
5341 #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
5345 #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
5349 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
5351 #define UTIL_PIN_CTL			_MMIO(0x48400)
5355 #define   UTIL_PIN_MODE_MASK		(0xf << 24)
5356 #define   UTIL_PIN_MODE_DATA		(0 << 24)
5367 #define _BXT_BLC_PWM_CTL1			0xC8250
5370 #define _BXT_BLC_PWM_FREQ1			0xC8254
5371 #define _BXT_BLC_PWM_DUTY1			0xC8258
5373 #define _BXT_BLC_PWM_CTL2			0xC8350
5374 #define _BXT_BLC_PWM_FREQ2			0xC8354
5375 #define _BXT_BLC_PWM_DUTY2			0xC8358
5384 #define PCH_GTC_CTL		_MMIO(0xe7000)
5388 #define TV_CTL			_MMIO(0x68000)
5396 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
5407 # define TV_OVERSAMPLE_4X		(0 << 18)
5430 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5433 # define TV_FUSE_STATE_ENABLED		(0 << 4)
5439 # define TV_TEST_MODE_NORMAL		(0 << 0)
5441 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
5443 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
5445 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
5447 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
5449 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
5455 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
5456 # define TV_TEST_MODE_MASK		(7 << 0)
5458 #define TV_DAC			_MMIO(0x68004)
5459 # define TV_DAC_SAVE		0x00ffff00
5490 # define DAC_A_1_3_V			(0 << 4)
5494 # define DAC_B_1_3_V			(0 << 2)
5498 # define DAC_C_1_3_V			(0 << 0)
5499 # define DAC_C_1_1_V			(1 << 0)
5500 # define DAC_C_0_7_V			(2 << 0)
5501 # define DAC_C_MASK			(3 << 0)
5507  * -1 (0x3) being the only legal negative value.
5509 #define TV_CSC_Y		_MMIO(0x68010)
5510 # define TV_RY_MASK			0x07ff0000
5512 # define TV_GY_MASK			0x00000fff
5513 # define TV_GY_SHIFT			0
5515 #define TV_CSC_Y2		_MMIO(0x68014)
5516 # define TV_BY_MASK			0x07ff0000
5523 # define TV_AY_MASK			0x000003ff
5524 # define TV_AY_SHIFT			0
5526 #define TV_CSC_U		_MMIO(0x68018)
5527 # define TV_RU_MASK			0x07ff0000
5529 # define TV_GU_MASK			0x000007ff
5530 # define TV_GU_SHIFT			0
5532 #define TV_CSC_U2		_MMIO(0x6801c)
5533 # define TV_BU_MASK			0x07ff0000
5540 # define TV_AU_MASK			0x000003ff
5541 # define TV_AU_SHIFT			0
5543 #define TV_CSC_V		_MMIO(0x68020)
5544 # define TV_RV_MASK			0x0fff0000
5546 # define TV_GV_MASK			0x000007ff
5547 # define TV_GV_SHIFT			0
5549 #define TV_CSC_V2		_MMIO(0x68024)
5550 # define TV_BV_MASK			0x07ff0000
5557 # define TV_AV_MASK			0x000007ff
5558 # define TV_AV_SHIFT			0
5560 #define TV_CLR_KNOBS		_MMIO(0x68028)
5562 # define TV_BRIGHTNESS_MASK		0xff000000
5565 # define TV_CONTRAST_MASK		0x00ff0000
5568 # define TV_SATURATION_MASK		0x0000ff00
5571 # define TV_HUE_MASK			0x000000ff
5572 # define TV_HUE_SHIFT			0
5574 #define TV_CLR_LEVEL		_MMIO(0x6802c)
5576 # define TV_BLACK_LEVEL_MASK		0x01ff0000
5579 # define TV_BLANK_LEVEL_MASK		0x000001ff
5580 # define TV_BLANK_LEVEL_SHIFT		0
5582 #define TV_H_CTL_1		_MMIO(0x68030)
5584 # define TV_HSYNC_END_MASK		0x1fff0000
5587 # define TV_HTOTAL_MASK			0x00001fff
5588 # define TV_HTOTAL_SHIFT		0
5590 #define TV_H_CTL_2		_MMIO(0x68034)
5595 # define TV_HBURST_START_MASK		0x1fff0000
5597 # define TV_HBURST_LEN_SHIFT		0
5598 # define TV_HBURST_LEN_MASK		0x0001fff
5600 #define TV_H_CTL_3		_MMIO(0x68038)
5603 # define TV_HBLANK_END_MASK		0x1fff0000
5605 # define TV_HBLANK_START_SHIFT		0
5606 # define TV_HBLANK_START_MASK		0x0001fff
5608 #define TV_V_CTL_1		_MMIO(0x6803c)
5611 # define TV_NBR_END_MASK		0x07ff0000
5614 # define TV_VI_END_F1_MASK		0x00003f00
5616 # define TV_VI_END_F2_SHIFT		0
5617 # define TV_VI_END_F2_MASK		0x0000003f
5619 #define TV_V_CTL_2		_MMIO(0x68040)
5621 # define TV_VSYNC_LEN_MASK		0x07ff0000
5626 # define TV_VSYNC_START_F1_MASK		0x00007f00
5632 # define TV_VSYNC_START_F2_MASK		0x0000007f
5633 # define TV_VSYNC_START_F2_SHIFT	0
5635 #define TV_V_CTL_3		_MMIO(0x68044)
5639 # define TV_VEQ_LEN_MASK		0x007f0000
5644 # define TV_VEQ_START_F1_MASK		0x0007f00
5650 # define TV_VEQ_START_F2_MASK		0x000007f
5651 # define TV_VEQ_START_F2_SHIFT		0
5653 #define TV_V_CTL_4		_MMIO(0x68048)
5658 # define TV_VBURST_START_F1_MASK	0x003f0000
5664 # define TV_VBURST_END_F1_MASK		0x000000ff
5665 # define TV_VBURST_END_F1_SHIFT		0
5667 #define TV_V_CTL_5		_MMIO(0x6804c)
5672 # define TV_VBURST_START_F2_MASK	0x003f0000
5678 # define TV_VBURST_END_F2_MASK		0x000000ff
5679 # define TV_VBURST_END_F2_SHIFT		0
5681 #define TV_V_CTL_6		_MMIO(0x68050)
5686 # define TV_VBURST_START_F3_MASK	0x003f0000
5692 # define TV_VBURST_END_F3_MASK		0x000000ff
5693 # define TV_VBURST_END_F3_SHIFT		0
5695 #define TV_V_CTL_7		_MMIO(0x68054)
5700 # define TV_VBURST_START_F4_MASK	0x003f0000
5706 # define TV_VBURST_END_F4_MASK		0x000000ff
5707 # define TV_VBURST_END_F4_SHIFT		0
5709 #define TV_SC_CTL_1		_MMIO(0x68060)
5717 # define TV_SC_RESET_EVERY_2		(0 << 24)
5725 # define TV_BURST_LEVEL_MASK		0x00ff0000
5728 # define TV_SCDDA1_INC_MASK		0x00000fff
5729 # define TV_SCDDA1_INC_SHIFT		0
5731 #define TV_SC_CTL_2		_MMIO(0x68064)
5733 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
5736 # define TV_SCDDA2_INC_MASK		0x00007fff
5737 # define TV_SCDDA2_INC_SHIFT		0
5739 #define TV_SC_CTL_3		_MMIO(0x68068)
5741 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
5744 # define TV_SCDDA3_INC_MASK		0x00007fff
5745 # define TV_SCDDA3_INC_SHIFT		0
5747 #define TV_WIN_POS		_MMIO(0x68070)
5749 # define TV_XPOS_MASK			0x1fff0000
5752 # define TV_YPOS_MASK			0x00000fff
5753 # define TV_YPOS_SHIFT			0
5755 #define TV_WIN_SIZE		_MMIO(0x68074)
5757 # define TV_XSIZE_MASK			0x1fff0000
5764 # define TV_YSIZE_MASK			0x00000fff
5765 # define TV_YSIZE_SHIFT			0
5767 #define TV_FILTER_CTL_1		_MMIO(0x68080)
5784 # define TV_VADAPT_MODE_LEAST		(0 << 26)
5797 # define TV_HSCALE_FRAC_MASK		0x00003fff
5798 # define TV_HSCALE_FRAC_SHIFT		0
5800 #define TV_FILTER_CTL_2		_MMIO(0x68084)
5806 # define TV_VSCALE_INT_MASK		0x00038000
5813 # define TV_VSCALE_FRAC_MASK		0x00007fff
5814 # define TV_VSCALE_FRAC_SHIFT		0
5816 #define TV_FILTER_CTL_3		_MMIO(0x68088)
5824 # define TV_VSCALE_IP_INT_MASK		0x00038000
5833 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
5834 # define TV_VSCALE_IP_FRAC_SHIFT		0
5836 #define TV_CC_CONTROL		_MMIO(0x68090)
5841  * CC data is usually sent in field 0.
5846 # define TV_CC_HOFF_MASK		0x03ff0000
5849 # define TV_CC_LINE_MASK		0x0000003f
5850 # define TV_CC_LINE_SHIFT		0
5852 #define TV_CC_DATA		_MMIO(0x68094)
5855 # define TV_CC_DATA_2_MASK		0x007f0000
5858 # define TV_CC_DATA_1_MASK		0x0000007f
5859 # define TV_CC_DATA_1_SHIFT		0
5861 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
5862 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
5863 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
5864 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
5867 #define DP_A			_MMIO(0x64000) /* eDP */
5868 #define DP_B			_MMIO(0x64100)
5869 #define DP_C			_MMIO(0x64200)
5870 #define DP_D			_MMIO(0x64300)
5872 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
5873 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
5874 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
5888 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
5896 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
5904 #define   DP_VOLTAGE_0_4		(0 << 25)
5914 #define   DP_PRE_EMPHASIS_0		(0 << 22)
5930 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
5964 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5965 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5967 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5968 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5977 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
5983 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5985 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5992 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5993 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5998 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
6015 #define _PIPEA_DATA_M_G4X	0x70050
6016 #define _PIPEB_DATA_M_G4X	0x71050
6018 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
6021 #define  TU_SIZE_MASK           (0x3f << 25)
6023 #define  DATA_LINK_M_N_MASK	(0xffffff)
6024 #define  DATA_LINK_N_MAX	(0x800000)
6026 #define _PIPEA_DATA_N_G4X	0x70054
6027 #define _PIPEB_DATA_N_G4X	0x71054
6028 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
6041 #define _PIPEA_LINK_M_G4X	0x70060
6042 #define _PIPEB_LINK_M_G4X	0x71060
6043 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
6045 #define _PIPEA_LINK_N_G4X	0x70064
6046 #define _PIPEB_LINK_N_G4X	0x71064
6047 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
6057 #define _PIPEADSL		0x70000
6058 #define   DSL_LINEMASK_GEN2	0x00000fff
6059 #define   DSL_LINEMASK_GEN3	0x00001fff
6060 #define _PIPEACONF		0x70008
6062 #define   PIPECONF_DISABLE	0
6067 #define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
6068 #define   PIPECONF_SINGLE_WIDE	0
6069 #define   PIPECONF_PIPE_UNLOCKED 0
6074 #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
6084 #define   PIPECONF_PROGRESSIVE			(0 << 21)
6102 #define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
6106 #define   PIPECONF_BPC_MASK	(0x7 << 5)
6107 #define   PIPECONF_8BPC		(0 << 5)
6112 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
6113 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
6117 #define _PIPEASTAT		0x70024
6162 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
6163 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
6165 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
6166 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
6168 #define PIPE_A_OFFSET		0x70000
6169 #define PIPE_B_OFFSET		0x71000
6170 #define PIPE_C_OFFSET		0x72000
6171 #define PIPE_D_OFFSET		0x73000
6172 #define CHV_PIPE_C_OFFSET	0x74000
6179 #define PIPE_EDP_OFFSET	0x7f000
6181 /* ICL DSI 0 and 1 */
6182 #define PIPE_DSI0_OFFSET	0x7b000
6183 #define PIPE_DSI1_OFFSET	0x7b800
6191 #define  _PIPEAGCMAX           0x70010
6192 #define  _PIPEBGCMAX           0x71010
6195 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
6199 #define _PIPE_MISC_A			0x70030
6200 #define _PIPE_MISC_B			0x71030
6213 #define   PIPEMISC_8_BPC		(0 << 5)
6219 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
6222 #define _PIPE_MISC2_A					0x7002C
6223 #define _PIPE_MISC2_B					0x7102C
6224 #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
6225 #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
6226 #define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
6230 #define _SKL_BOTTOM_COLOR_A		0x70034
6235 #define _ICL_PIPE_A_STATUS			0x70058
6242 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
6263 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
6276 #define   DPINVGTT_EN_MASK			0xff0000
6277 #define   DPINVGTT_EN_MASK_CHV			0xfff0000
6289 #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
6290 #define   DPINVGTT_STATUS_MASK			0xff
6291 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
6293 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
6294 #define   DSPARB_CSTART_MASK	(0x7f << 7)
6296 #define   DSPARB_BSTART_MASK	(0x7f)
6297 #define   DSPARB_BSTART_SHIFT	0
6299 #define   DSPARB_AEND_SHIFT	0
6300 #define   DSPARB_SPRITEA_SHIFT_VLV	0
6301 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
6303 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
6305 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
6307 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
6308 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
6309 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
6310 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
6312 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
6314 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
6316 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
6318 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
6320 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
6321 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
6322 #define   DSPARB_SPRITEE_SHIFT_VLV	0
6323 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
6325 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
6328 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
6330 #define   DSPFW_SR_MASK			(0x1ff << 23)
6332 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
6334 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
6335 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
6336 #define   DSPFW_PLANEA_SHIFT		0
6337 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
6338 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
6339 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
6342 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
6344 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
6346 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
6347 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
6349 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
6350 #define   DSPFW_PLANEC_OLD_SHIFT	0
6351 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
6352 #define   DSPFW_SPRITEA_SHIFT		0
6353 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
6354 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
6355 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6359 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
6361 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
6362 #define   DSPFW_HPLL_SR_SHIFT		0
6363 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
6366 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
6368 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
6370 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
6371 #define   DSPFW_SPRITEA_WM1_SHIFT	0
6372 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
6373 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
6375 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
6377 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
6379 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
6380 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
6381 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
6382 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
6383 #define   DSPFW_SR_WM1_SHIFT		0
6384 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
6385 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
6386 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6388 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
6390 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
6392 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
6393 #define   DSPFW_SPRITEC_SHIFT		0
6394 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
6395 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
6397 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
6399 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
6401 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
6402 #define   DSPFW_SPRITEE_SHIFT		0
6403 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
6404 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6406 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
6408 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
6410 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
6411 #define   DSPFW_CURSORC_SHIFT		0
6412 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
6415 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
6434 #define   DSPFW_PLANEA_HI_SHIFT		0
6435 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
6436 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
6455 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
6456 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
6459 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6462 #define DDL_PLANE_SHIFT			0
6464 #define DDL_PRECISION_LOW		(0 << 7)
6465 #define DRAIN_LATENCY_MASK		0x7f
6467 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
6471 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
6487 #define VALLEYVIEW_MAX_WM	0xff
6488 #define G4X_MAX_WM		0x3f
6489 #define I915_MAX_WM		0x3f
6493 #define PINEVIEW_MAX_WM		0x1ff
6494 #define PINEVIEW_DFT_WM		0x3f
6495 #define PINEVIEW_DFT_HPLLOFF_WM	0
6498 #define PINEVIEW_CURSOR_MAX_WM	0x3f
6499 #define PINEVIEW_CURSOR_DFT_WM	0
6508 #define _CUR_WM_A_0		0x70140
6509 #define _CUR_WM_B_0		0x71140
6510 #define _CUR_WM_SAGV_A		0x70158
6511 #define _CUR_WM_SAGV_B		0x71158
6512 #define _CUR_WM_SAGV_TRANS_A	0x7015C
6513 #define _CUR_WM_SAGV_TRANS_B	0x7115C
6514 #define _CUR_WM_TRANS_A		0x70168
6515 #define _CUR_WM_TRANS_B		0x71168
6516 #define _PLANE_WM_1_A_0		0x70240
6517 #define _PLANE_WM_1_B_0		0x71240
6518 #define _PLANE_WM_2_A_0		0x70340
6519 #define _PLANE_WM_2_B_0		0x71340
6520 #define _PLANE_WM_SAGV_1_A	0x70258
6521 #define _PLANE_WM_SAGV_1_B	0x71258
6522 #define _PLANE_WM_SAGV_2_A	0x70358
6523 #define _PLANE_WM_SAGV_2_B	0x71358
6524 #define _PLANE_WM_SAGV_TRANS_1_A	0x7025C
6525 #define _PLANE_WM_SAGV_TRANS_1_B	0x7125C
6526 #define _PLANE_WM_SAGV_TRANS_2_A	0x7035C
6527 #define _PLANE_WM_SAGV_TRANS_2_B	0x7135C
6528 #define _PLANE_WM_TRANS_1_A	0x70268
6529 #define _PLANE_WM_TRANS_1_B	0x71268
6530 #define _PLANE_WM_TRANS_2_A	0x70368
6531 #define _PLANE_WM_TRANS_2_B	0x71368
6535 #define   PLANE_WM_BLOCKS_MASK	REG_GENMASK(11, 0)
6568 #define _WM0_PIPEA_ILK		0x45100
6569 #define _WM0_PIPEB_ILK		0x45104
6570 #define _WM0_PIPEC_IVB		0x45200
6573 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
6575 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
6577 #define  WM0_PIPE_CURSOR_MASK	(0xff)
6578 #define WM1_LP_ILK		_MMIO(0x45108)
6581 #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
6582 #define  WM1_LP_FBC_MASK	(0xf << 20)
6585 #define  WM1_LP_SR_MASK		(0x7ff << 8)
6587 #define  WM1_LP_CURSOR_MASK	(0xff)
6588 #define WM2_LP_ILK		_MMIO(0x4510c)
6590 #define WM3_LP_ILK		_MMIO(0x45110)
6592 #define WM1S_LP_ILK		_MMIO(0x45120)
6593 #define WM2S_LP_IVB		_MMIO(0x45124)
6594 #define WM3S_LP_IVB		_MMIO(0x45128)
6602 #define MLTR_ILK		_MMIO(0x11222)
6603 #define  MLTR_WM1_SHIFT		0
6606 #define  ILK_SRLT_MASK		0x3f
6610 #define SSKPD			_MMIO(0x5d10)
6611 #define SSKPD_WM_MASK		0x3f
6612 #define SSKPD_WM0_SHIFT		0
6632 #define _PIPEAFRAMEHIGH          0x70040
6633 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6634 #define   PIPE_FRAME_HIGH_SHIFT   0
6635 #define _PIPEAFRAMEPIXEL         0x70044
6636 #define   PIPE_FRAME_LOW_MASK     0xff000000
6638 #define   PIPE_PIXEL_MASK         0x00ffffff
6639 #define   PIPE_PIXEL_SHIFT        0
6641 #define _PIPEA_FRMCOUNT_G4X	0x70040
6642 #define _PIPEA_FLIPCOUNT_G4X	0x70044
6647 #define _CURACNTR		0x70080
6649 #define   CURSOR_ENABLE		0x80000000
6650 #define   CURSOR_GAMMA_ENABLE	0x40000000
6654 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
6655 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
6656 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
6657 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
6658 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
6659 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
6661 #define   MCURSOR_MODE		0x27
6662 #define   MCURSOR_MODE_DISABLE   0x00
6663 #define   MCURSOR_MODE_128_32B_AX 0x02
6664 #define   MCURSOR_MODE_256_32B_AX 0x03
6665 #define   MCURSOR_MODE_64_32B_AX 0x07
6671 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
6678 #define _CURABASE		0x70084
6679 #define _CURAPOS		0x70088
6680 #define   CURSOR_POS_MASK       0x007FF
6681 #define   CURSOR_POS_SIGN       0x8000
6682 #define   CURSOR_X_SHIFT        0
6684 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
6685 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
6687 #define _CURASURFLIVE		0x700ac /* g4x+ */
6688 #define _CURBCNTR		0x700c0
6689 #define _CURBBASE		0x700c4
6690 #define _CURBPOS		0x700c8
6692 #define _CURBCNTR_IVB		0x71080
6693 #define _CURBBASE_IVB		0x71084
6694 #define _CURBPOS_IVB		0x71088
6702 #define CURSOR_A_OFFSET 0x70080
6703 #define CURSOR_B_OFFSET 0x700c0
6704 #define CHV_CURSOR_C_OFFSET 0x700e0
6705 #define IVB_CURSOR_B_OFFSET 0x71080
6706 #define IVB_CURSOR_C_OFFSET 0x72080
6707 #define TGL_CURSOR_D_OFFSET 0x73080
6710 #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
6711 #define _DSPACNTR				0x70180
6713 #define   DISPLAY_PLANE_DISABLE			0
6715 #define   DISPPLANE_GAMMA_DISABLE		0
6716 #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
6717 #define   DISPPLANE_YUV422			(0x0 << 26)
6718 #define   DISPPLANE_8BPP			(0x2 << 26)
6719 #define   DISPPLANE_BGRA555			(0x3 << 26)
6720 #define   DISPPLANE_BGRX555			(0x4 << 26)
6721 #define   DISPPLANE_BGRX565			(0x5 << 26)
6722 #define   DISPPLANE_BGRX888			(0x6 << 26)
6723 #define   DISPPLANE_BGRA888			(0x7 << 26)
6724 #define   DISPPLANE_RGBX101010			(0x8 << 26)
6725 #define   DISPPLANE_RGBA101010			(0x9 << 26)
6726 #define   DISPPLANE_BGRX101010			(0xa << 26)
6727 #define   DISPPLANE_BGRA101010			(0xb << 26)
6728 #define   DISPPLANE_RGBX161616			(0xc << 26)
6729 #define   DISPPLANE_RGBX888			(0xe << 26)
6730 #define   DISPPLANE_RGBA888			(0xf << 26)
6732 #define   DISPPLANE_STEREO_DISABLE		0
6738 #define   DISPPLANE_SRC_KEY_DISABLE		0
6740 #define   DISPPLANE_NO_LINE_DOUBLE		0
6741 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
6749 #define _DSPAADDR				0x70184
6750 #define _DSPASTRIDE				0x70188
6751 #define _DSPAPOS				0x7018C /* reserved */
6752 #define _DSPASIZE				0x70190
6753 #define _DSPASURF				0x7019C /* 965+ only */
6754 #define _DSPATILEOFF				0x701A4 /* 965+ only */
6755 #define _DSPAOFFSET				0x701A4 /* HSW */
6756 #define _DSPASURFLIVE				0x701AC
6757 #define _DSPAGAMC				0x701E0
6773 #define _CHV_BLEND_A		0x60a00
6774 #define   CHV_BLEND_LEGACY		(0 << 30)
6778 #define _CHV_CANVAS_A		0x60a04
6779 #define _PRIMPOS_A		0x60a08
6780 #define _PRIMSIZE_A		0x60a0c
6781 #define _PRIMCNSTALPHA_A	0x60a10
6791 #define DISP_BASEADDR_MASK	(0xfffff000)
6802  * [00:0f] all
6806 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6807 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6808 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6809 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
6812 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6813 #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6814 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6815 #define _PIPEBFRAMEHIGH		0x71040
6816 #define _PIPEBFRAMEPIXEL	0x71044
6817 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6818 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6822 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6824 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
6825 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
6827 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6828 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6829 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6830 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6831 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6832 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6833 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6834 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6836 /* ICL DSI 0 and 1 */
6837 #define _PIPEDSI0CONF		0x7b008
6838 #define _PIPEDSI1CONF		0x7b808
6841 #define _DVSACNTR		0x72180
6846 #define   DVS_FORMAT_YUV422	(0 << 25)
6855 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
6863 #define _DVSALINOFF		0x72184
6864 #define _DVSASTRIDE		0x72188
6865 #define _DVSAPOS		0x7218c
6866 #define _DVSASIZE		0x72190
6867 #define _DVSAKEYVAL		0x72194
6868 #define _DVSAKEYMSK		0x72198
6869 #define _DVSASURF		0x7219c
6870 #define _DVSAKEYMAXVAL		0x721a0
6871 #define _DVSATILEOFF		0x721a4
6872 #define _DVSASURFLIVE		0x721ac
6873 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
6874 #define _DVSASCALE		0x72204
6877 #define   DVS_FILTER_MEDIUM	(0 << 29)
6882 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
6883 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
6885 #define _DVSBCNTR		0x73180
6886 #define _DVSBLINOFF		0x73184
6887 #define _DVSBSTRIDE		0x73188
6888 #define _DVSBPOS		0x7318c
6889 #define _DVSBSIZE		0x73190
6890 #define _DVSBKEYVAL		0x73194
6891 #define _DVSBKEYMSK		0x73198
6892 #define _DVSBSURF		0x7319c
6893 #define _DVSBKEYMAXVAL		0x731a0
6894 #define _DVSBTILEOFF		0x731a4
6895 #define _DVSBSURFLIVE		0x731ac
6896 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
6897 #define _DVSBSCALE		0x73204
6898 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
6899 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
6917 #define _SPRA_CTL		0x70280
6922 #define   SPRITE_FORMAT_YUV422		(0 << 25)
6932 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
6934 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
6943 #define _SPRA_LINOFF		0x70284
6944 #define _SPRA_STRIDE		0x70288
6945 #define _SPRA_POS		0x7028c
6946 #define _SPRA_SIZE		0x70290
6947 #define _SPRA_KEYVAL		0x70294
6948 #define _SPRA_KEYMSK		0x70298
6949 #define _SPRA_SURF		0x7029c
6950 #define _SPRA_KEYMAX		0x702a0
6951 #define _SPRA_TILEOFF		0x702a4
6952 #define _SPRA_OFFSET		0x702a4
6953 #define _SPRA_SURFLIVE		0x702ac
6954 #define _SPRA_SCALE		0x70304
6957 #define   SPRITE_FILTER_MEDIUM	(0 << 29)
6962 #define _SPRA_GAMC		0x70400
6963 #define _SPRA_GAMC16		0x70440
6964 #define _SPRA_GAMC17		0x7044c
6966 #define _SPRB_CTL		0x71280
6967 #define _SPRB_LINOFF		0x71284
6968 #define _SPRB_STRIDE		0x71288
6969 #define _SPRB_POS		0x7128c
6970 #define _SPRB_SIZE		0x71290
6971 #define _SPRB_KEYVAL		0x71294
6972 #define _SPRB_KEYMSK		0x71298
6973 #define _SPRB_SURF		0x7129c
6974 #define _SPRB_KEYMAX		0x712a0
6975 #define _SPRB_TILEOFF		0x712a4
6976 #define _SPRB_OFFSET		0x712a4
6977 #define _SPRB_SURFLIVE		0x712ac
6978 #define _SPRB_SCALE		0x71304
6979 #define _SPRB_GAMC		0x71400
6980 #define _SPRB_GAMC16		0x71440
6981 #define _SPRB_GAMC17		0x7144c
7000 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
7003 #define   SP_PIXFORMAT_MASK		(0xf << 26)
7004 #define   SP_FORMAT_YUV422		(0x0 << 26)
7005 #define   SP_FORMAT_8BPP		(0x2 << 26)
7006 #define   SP_FORMAT_BGR565		(0x5 << 26)
7007 #define   SP_FORMAT_BGRX8888		(0x6 << 26)
7008 #define   SP_FORMAT_BGRA8888		(0x7 << 26)
7009 #define   SP_FORMAT_RGBX1010102		(0x8 << 26)
7010 #define   SP_FORMAT_RGBA1010102		(0x9 << 26)
7011 #define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
7012 #define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
7013 #define   SP_FORMAT_RGBX8888		(0xe << 26)
7014 #define   SP_FORMAT_RGBA8888		(0xf << 26)
7019 #define   SP_YUV_ORDER_YUYV		(0 << 16)
7026 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
7027 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
7028 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
7029 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
7030 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
7031 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
7032 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
7033 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
7034 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
7035 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
7037 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
7039 #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
7040 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
7041 #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
7043 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
7045 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
7046 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
7047 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
7048 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
7049 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
7050 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
7051 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
7052 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
7053 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
7054 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
7055 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
7056 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
7057 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
7058 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
7088 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
7090 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
7091 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
7092 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
7093 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
7094 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
7096 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
7097 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
7098 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
7099 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
7100 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
7101 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
7102 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
7104 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
7105 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
7106 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
7107 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
7108 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
7110 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
7111 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
7112 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
7114 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
7118 #define _PLANE_CTL_1_A				0x70180
7119 #define _PLANE_CTL_2_A				0x70280
7120 #define _PLANE_CTL_3_A				0x70380
7129  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
7131 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
7132 #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
7143 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
7150 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
7151 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
7154 #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
7158 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
7159 #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
7167 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
7168 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
7175 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
7176 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
7179 #define   PLANE_CTL_ROTATE_MASK			0x3
7180 #define   PLANE_CTL_ROTATE_0			0x0
7181 #define   PLANE_CTL_ROTATE_90			0x1
7182 #define   PLANE_CTL_ROTATE_180			0x2
7183 #define   PLANE_CTL_ROTATE_270			0x3
7184 #define _PLANE_STRIDE_1_A			0x70188
7185 #define _PLANE_STRIDE_2_A			0x70288
7186 #define _PLANE_STRIDE_3_A			0x70388
7187 #define _PLANE_POS_1_A				0x7018c
7188 #define _PLANE_POS_2_A				0x7028c
7189 #define _PLANE_POS_3_A				0x7038c
7190 #define _PLANE_SIZE_1_A				0x70190
7191 #define _PLANE_SIZE_2_A				0x70290
7192 #define _PLANE_SIZE_3_A				0x70390
7193 #define _PLANE_SURF_1_A				0x7019c
7194 #define _PLANE_SURF_2_A				0x7029c
7195 #define _PLANE_SURF_3_A				0x7039c
7196 #define _PLANE_OFFSET_1_A			0x701a4
7197 #define _PLANE_OFFSET_2_A			0x702a4
7198 #define _PLANE_OFFSET_3_A			0x703a4
7199 #define _PLANE_KEYVAL_1_A			0x70194
7200 #define _PLANE_KEYVAL_2_A			0x70294
7201 #define _PLANE_KEYMSK_1_A			0x70198
7202 #define _PLANE_KEYMSK_2_A			0x70298
7204 #define _PLANE_KEYMAX_1_A			0x701a0
7205 #define _PLANE_KEYMAX_2_A			0x702a0
7207 #define _PLANE_CC_VAL_1_A			0x701b4
7208 #define _PLANE_CC_VAL_2_A			0x702b4
7209 #define _PLANE_AUX_DIST_1_A			0x701c0
7210 #define _PLANE_AUX_DIST_2_A			0x702c0
7211 #define _PLANE_AUX_OFFSET_1_A			0x701c4
7212 #define _PLANE_AUX_OFFSET_2_A			0x702c4
7213 #define _PLANE_CUS_CTL_1_A			0x701c8
7214 #define _PLANE_CUS_CTL_2_A			0x702c8
7216 #define  PLANE_CUS_PLANE_4_RKL			(0 << 30)
7218 #define  PLANE_CUS_PLANE_6			(0 << 30)
7221 #define  PLANE_CUS_HPHASE_0			(0 << 16)
7225 #define  PLANE_CUS_VPHASE_0			(0 << 12)
7228 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
7229 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
7230 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
7235 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
7241 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
7242 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
7245 #define _PLANE_BUF_CFG_1_A			0x7027c
7246 #define _PLANE_BUF_CFG_2_A			0x7037c
7247 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
7248 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
7250 #define _PLANE_CC_VAL_1_B			0x711b4
7251 #define _PLANE_CC_VAL_2_B			0x712b4
7258 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
7259 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
7261 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
7262 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
7275 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
7276 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
7278 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
7279 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
7291 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
7292 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
7294 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
7295 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
7307 #define _PLANE_CTL_1_B				0x71180
7308 #define _PLANE_CTL_2_B				0x71280
7309 #define _PLANE_CTL_3_B				0x71380
7316 #define _PLANE_STRIDE_1_B			0x71188
7317 #define _PLANE_STRIDE_2_B			0x71288
7318 #define _PLANE_STRIDE_3_B			0x71388
7327 #define PLANE_STRIDE_MASK		REG_GENMASK(10, 0)
7328 #define PLANE_STRIDE_MASK_XELPD		REG_GENMASK(11, 0)
7330 #define _PLANE_POS_1_B				0x7118c
7331 #define _PLANE_POS_2_B				0x7128c
7332 #define _PLANE_POS_3_B				0x7138c
7339 #define _PLANE_SIZE_1_B				0x71190
7340 #define _PLANE_SIZE_2_B				0x71290
7341 #define _PLANE_SIZE_3_B				0x71390
7348 #define _PLANE_SURF_1_B				0x7119c
7349 #define _PLANE_SURF_2_B				0x7129c
7350 #define _PLANE_SURF_3_B				0x7139c
7357 #define _PLANE_OFFSET_1_B			0x711a4
7358 #define _PLANE_OFFSET_2_B			0x712a4
7364 #define _PLANE_KEYVAL_1_B			0x71194
7365 #define _PLANE_KEYVAL_2_B			0x71294
7371 #define _PLANE_KEYMSK_1_B			0x71198
7372 #define _PLANE_KEYMSK_2_B			0x71298
7378 #define _PLANE_KEYMAX_1_B			0x711a0
7379 #define _PLANE_KEYMAX_2_B			0x712a0
7385 #define _PLANE_BUF_CFG_1_B			0x7127c
7386 #define _PLANE_BUF_CFG_2_B			0x7137c
7387 #define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
7396 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
7397 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
7405 #define _PLANE_AUX_DIST_1_B		0x711c0
7406 #define _PLANE_AUX_DIST_2_B		0x712c0
7414 #define _PLANE_AUX_OFFSET_1_B		0x711c4
7415 #define _PLANE_AUX_OFFSET_2_B		0x712c4
7423 #define _PLANE_CUS_CTL_1_B		0x711c8
7424 #define _PLANE_CUS_CTL_2_B		0x712c8
7432 #define _PLANE_COLOR_CTL_1_B			0x711CC
7433 #define _PLANE_COLOR_CTL_2_B			0x712CC
7434 #define _PLANE_COLOR_CTL_3_B			0x713CC
7442 #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
7443 #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
7444 #define _SEL_FETCH_PLANE_BASE_3_A		0x708D0
7445 #define _SEL_FETCH_PLANE_BASE_4_A		0x708F0
7446 #define _SEL_FETCH_PLANE_BASE_5_A		0x70920
7447 #define _SEL_FETCH_PLANE_BASE_6_A		0x70940
7448 #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
7449 #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
7450 #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
7466 #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
7472 #define _SEL_FETCH_PLANE_POS_1_A		0x70894
7477 #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
7482 #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
7488 #define _CUR_BUF_CFG_A				0x7017c
7489 #define _CUR_BUF_CFG_B				0x7117c
7493 #define VGACNTRL		_MMIO(0x71400)
7498 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
7502 #define CPU_VGACNTRL	_MMIO(0x41000)
7504 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
7506 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
7511 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
7512 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
7513 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
7514 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
7517 #define RR_HW_CTL       _MMIO(0x45300)
7518 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
7519 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
7521 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
7522 #define  FDI_PLL_FB_CLOCK_MASK  0xff
7523 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
7524 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
7525 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
7526 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
7527 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
7529 #define PCH_3DCGDIS0		_MMIO(0x46020)
7533 #define PCH_3DCGDIS1		_MMIO(0x46024)
7536 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
7538 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
7539 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
7542 #define _PIPEA_DATA_M1		0x60030
7543 #define  PIPE_DATA_M1_OFFSET    0
7544 #define _PIPEA_DATA_N1		0x60034
7545 #define  PIPE_DATA_N1_OFFSET    0
7547 #define _PIPEA_DATA_M2		0x60038
7548 #define  PIPE_DATA_M2_OFFSET    0
7549 #define _PIPEA_DATA_N2		0x6003c
7550 #define  PIPE_DATA_N2_OFFSET    0
7552 #define _PIPEA_LINK_M1		0x60040
7553 #define  PIPE_LINK_M1_OFFSET    0
7554 #define _PIPEA_LINK_N1		0x60044
7555 #define  PIPE_LINK_N1_OFFSET    0
7557 #define _PIPEA_LINK_M2		0x60048
7558 #define  PIPE_LINK_M2_OFFSET    0
7559 #define _PIPEA_LINK_N2		0x6004c
7560 #define  PIPE_LINK_N2_OFFSET    0
7562 /* PIPEB timing regs are same start from 0x61000 */
7564 #define _PIPEB_DATA_M1		0x61030
7565 #define _PIPEB_DATA_N1		0x61034
7566 #define _PIPEB_DATA_M2		0x61038
7567 #define _PIPEB_DATA_N2		0x6103c
7568 #define _PIPEB_LINK_M1		0x61040
7569 #define _PIPEB_LINK_N1		0x61044
7570 #define _PIPEB_LINK_M2		0x61048
7571 #define _PIPEB_LINK_N2		0x6104c
7583 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7584 #define _PFA_CTL_1               0x68080
7585 #define _PFB_CTL_1               0x68880
7590 #define  PF_FILTER_PROGRAMMED	(0 << 23)
7594 #define _PFA_WIN_SZ		0x68074
7595 #define _PFB_WIN_SZ		0x68874
7596 #define _PFA_WIN_POS		0x68070
7597 #define _PFB_WIN_POS		0x68870
7598 #define _PFA_VSCALE		0x68084
7599 #define _PFB_VSCALE		0x68884
7600 #define _PFA_HSCALE		0x68090
7601 #define _PFB_HSCALE		0x68890
7609 #define _PSA_CTL		0x68180
7610 #define _PSB_CTL		0x68980
7612 #define _PSA_WIN_SZ		0x68174
7613 #define _PSB_WIN_SZ		0x68974
7614 #define _PSA_WIN_POS		0x68170
7615 #define _PSB_WIN_POS		0x68970
7624 #define _PS_1A_CTRL      0x68180
7625 #define _PS_2A_CTRL      0x68280
7626 #define _PS_1B_CTRL      0x68980
7627 #define _PS_2B_CTRL      0x68A80
7628 #define _PS_1C_CTRL      0x69180
7631 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7635 #define PS_SCALER_MODE_NORMAL (0 << 29)
7639 #define PS_FILTER_MEDIUM       (0 << 23)
7644 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7650 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7660 #define _PS_PWR_GATE_1A     0x68160
7661 #define _PS_PWR_GATE_2A     0x68260
7662 #define _PS_PWR_GATE_1B     0x68960
7663 #define _PS_PWR_GATE_2B     0x68A60
7664 #define _PS_PWR_GATE_1C     0x69160
7666 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7670 #define PS_PWR_GATE_SLPEN_8             0
7675 #define _PS_WIN_POS_1A      0x68170
7676 #define _PS_WIN_POS_2A      0x68270
7677 #define _PS_WIN_POS_1B      0x68970
7678 #define _PS_WIN_POS_2B      0x68A70
7679 #define _PS_WIN_POS_1C      0x69170
7681 #define _PS_WIN_SZ_1A       0x68174
7682 #define _PS_WIN_SZ_2A       0x68274
7683 #define _PS_WIN_SZ_1B       0x68974
7684 #define _PS_WIN_SZ_2B       0x68A74
7685 #define _PS_WIN_SZ_1C       0x69174
7687 #define _PS_VSCALE_1A       0x68184
7688 #define _PS_VSCALE_2A       0x68284
7689 #define _PS_VSCALE_1B       0x68984
7690 #define _PS_VSCALE_2B       0x68A84
7691 #define _PS_VSCALE_1C       0x69184
7693 #define _PS_HSCALE_1A       0x68190
7694 #define _PS_HSCALE_2A       0x68290
7695 #define _PS_HSCALE_1B       0x68990
7696 #define _PS_HSCALE_2B       0x68A90
7697 #define _PS_HSCALE_1C       0x69190
7699 #define _PS_VPHASE_1A       0x68188
7700 #define _PS_VPHASE_2A       0x68288
7701 #define _PS_VPHASE_1B       0x68988
7702 #define _PS_VPHASE_2B       0x68A88
7703 #define _PS_VPHASE_1C       0x69188
7705 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
7706 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
7707 #define   PS_PHASE_TRIP	(1 << 0)
7709 #define _PS_HPHASE_1A       0x68194
7710 #define _PS_HPHASE_2A       0x68294
7711 #define _PS_HPHASE_1B       0x68994
7712 #define _PS_HPHASE_2B       0x68A94
7713 #define _PS_HPHASE_1C       0x69194
7715 #define _PS_ECC_STAT_1A     0x681D0
7716 #define _PS_ECC_STAT_2A     0x682D0
7717 #define _PS_ECC_STAT_1B     0x689D0
7718 #define _PS_ECC_STAT_2B     0x68AD0
7719 #define _PS_ECC_STAT_1C     0x691D0
7721 #define _PS_COEF_SET0_INDEX_1A	   0x68198
7722 #define _PS_COEF_SET0_INDEX_2A	   0x68298
7723 #define _PS_COEF_SET0_INDEX_1B	   0x68998
7724 #define _PS_COEF_SET0_INDEX_2B	   0x68A98
7727 #define _PS_COEF_SET0_DATA_1A	   0x6819C
7728 #define _PS_COEF_SET0_DATA_2A	   0x6829C
7729 #define _PS_COEF_SET0_DATA_1B	   0x6899C
7730 #define _PS_COEF_SET0_DATA_2B	   0x68A9C
7768 #define _LGC_PALETTE_A           0x4a000
7769 #define _LGC_PALETTE_B           0x4a800
7772 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
7776 #define _PREC_PALETTE_A           0x4b000
7777 #define _PREC_PALETTE_B           0x4c000
7780 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
7783 #define  _PREC_PIPEAGCMAX              0x4d000
7784 #define  _PREC_PIPEBGCMAX              0x4d010
7787 #define _GAMMA_MODE_A		0x4a480
7788 #define _GAMMA_MODE_B		0x4ac80
7792 #define  GAMMA_MODE_MODE_MASK	(3 << 0)
7793 #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
7794 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
7795 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
7796 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
7797 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
7801 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
7802 #define DMC_HTP_ADDR_SKL	0x00500034
7803 #define DMC_SSP_BASE		_MMIO(0x8F074)
7804 #define DMC_HTP_SKL		_MMIO(0x8F004)
7805 #define DMC_LAST_WRITE		_MMIO(0x8F034)
7806 #define DMC_LAST_WRITE_VALUE	0xc003b400
7807 /* MMIO address range for DMC program (0x80000 - 0x82FFF) */
7808 #define DMC_MMIO_START_RANGE	0x80000
7809 #define DMC_MMIO_END_RANGE	0x8FFFF
7810 #define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
7811 #define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
7812 #define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
7813 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
7814 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
7815 #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
7817 #define DMC_DEBUG3		_MMIO(0x101090)
7820 #define RM_TIMEOUT		_MMIO(0x42060)
7821 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
7853 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7872 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
7875 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7878 #define DEISR   _MMIO(0x44000)
7879 #define DEIMR   _MMIO(0x44004)
7880 #define DEIIR   _MMIO(0x44008)
7881 #define DEIER   _MMIO(0x4400c)
7883 #define GTISR   _MMIO(0x44010)
7884 #define GTIMR   _MMIO(0x44014)
7885 #define GTIIR   _MMIO(0x44018)
7886 #define GTIER   _MMIO(0x4401c)
7888 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
7904 #define  GEN8_GT_RCS_IRQ		(1 << 0)
7906 #define XELPD_DISPLAY_ERR_FATAL_MASK	_MMIO(0x4421c)
7908 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7909 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7910 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7911 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7913 #define GEN8_RCS_IRQ_SHIFT 0
7915 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7917 #define GEN8_VECS_IRQ_SHIFT 0
7920 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7921 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7922 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7923 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7936 #define  GEN8_PIPE_VBLANK		(1 << 0)
7972 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7973 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7974 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7975 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7991 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
8002 #define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
8004 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
8005 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
8006 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
8007 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
8011 #define GEN8_PCU_ISR _MMIO(0x444e0)
8012 #define GEN8_PCU_IMR _MMIO(0x444e4)
8013 #define GEN8_PCU_IIR _MMIO(0x444e8)
8014 #define GEN8_PCU_IER _MMIO(0x444ec)
8016 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
8017 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
8018 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
8019 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
8022 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
8029 #define  GEN11_GT_DW0_IRQ		(1 << 0)
8031 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
8035 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
8046 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
8047 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
8048 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
8049 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
8065 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
8066 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
8070 #define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
8072 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
8080 #define  GEN11_RCS0			(0)
8082 #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
8086 #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
8088 #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
8089 #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
8093 #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
8095 #define OTHER_GUC_INSTANCE	0
8098 #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
8100 #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
8101 #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
8103 #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
8105 #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
8106 #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
8107 #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
8108 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
8109 #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
8110 #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
8112 #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
8113 #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
8114 #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
8115 #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
8116 #define GEN12_VCS4_VCS5_INTR_MASK	_MMIO(0x1900b0)
8117 #define GEN12_VCS6_VCS7_INTR_MASK	_MMIO(0x1900b4)
8118 #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
8119 #define GEN12_VECS2_VECS3_INTR_MASK	_MMIO(0x1900d4)
8120 #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
8121 #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
8122 #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
8123 #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
8126 #define   ENGINE0_MASK			REG_GENMASK(15, 0)
8128 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
8133 #define FUSE_STRAP			_MMIO(0x42014)
8144 #define FUSE_STRAP3			_MMIO(0x42020)
8147 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
8154 #define IVB_CHICKEN3	_MMIO(0x4200c)
8158 #define CHICKEN_PAR1_1			_MMIO(0x42080)
8168 #define CHICKEN_PAR2_1		_MMIO(0x42090)
8171 #define CHICKEN_MISC_2		_MMIO(0x42084)
8178 #define CHICKEN_MISC_4		_MMIO(0x4208c)
8180 #define   FBC_STRIDE_MASK	0x1FFF
8182 #define _CHICKEN_PIPESL_1_A	0x420b0
8183 #define _CHICKEN_PIPESL_1_B	0x420b4
8185 #define  HSW_PRI_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
8190 #define  HSW_SPR_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
8195 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
8196 #define  SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
8197 #define  SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
8203 #define _CHICKEN_TRANS_A	0x420c0
8204 #define _CHICKEN_TRANS_B	0x420c4
8205 #define _CHICKEN_TRANS_C	0x420c8
8206 #define _CHICKEN_TRANS_EDP	0x420cc
8207 #define _CHICKEN_TRANS_D	0x420d8
8225 #define DISP_ARB_CTL	_MMIO(0x45000)
8229 #define DISP_ARB_CTL2	_MMIO(0x45004)
8235  * with gen13 display, the bspec switches to a 0-based numbering scheme
8237  * We'll just use the 0-based numbering here for all platforms since it's the
8241 #define _DBUF_CTL_S0				0x45008
8242 #define _DBUF_CTL_S1				0x44FE8
8243 #define _DBUF_CTL_S2				0x44300
8244 #define _DBUF_CTL_S3				0x44304
8257 #define GEN7_MSG_CTL	_MMIO(0x45010)
8259 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
8261 #define _BW_BUDDY0_CTL			0x45130
8262 #define _BW_BUDDY1_CTL			0x45140
8270 #define _BW_BUDDY0_PAGE_MASK		0x45134
8271 #define _BW_BUDDY1_PAGE_MASK		0x45144
8276 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
8279 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
8284 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
8290 #define SKL_DFSM			_MMIO(0x51000)
8294 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
8305 #define SKL_DSSM				_MMIO(0x51004)
8307 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
8311 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
8314 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
8318 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
8320 #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
8323 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
8324 #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
8326 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8327 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8328 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8332 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
8336 #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
8340   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
8342 #define GEN8_L3CNTLREG	_MMIO(0x7034)
8345 #define GEN11_COMMON_SLICE_CHICKEN3			_MMIO(0x7304)
8350 #define HIZ_CHICKEN					_MMIO(0x7018)
8355 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
8358 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
8361 #define GEN7_SARCHKMD				_MMIO(0xB000)
8365 #define GEN7_L3SQCREG1				_MMIO(0xB010)
8366 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
8368 #define GEN8_L3SQCREG1				_MMIO(0xB100)
8377 #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
8379 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
8380 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
8382 #define GEN7_L3CNTLREG2				_MMIO(0xB020)
8383 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
8385 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
8386 #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
8387 #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
8390 #define GEN7_L3SQCREG4				_MMIO(0xb034)
8393 #define GEN11_SCRATCH2					_MMIO(0xb140)
8396 #define GEN8_L3SQCREG4				_MMIO(0xb118)
8403 #define HDC_CHICKEN0				_MMIO(0x7300)
8404 #define ICL_HDC_MODE				_MMIO(0xE5F4)
8412 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
8415 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
8418 #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
8422 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
8425 #define HSW_SCRATCH1				_MMIO(0xb038)
8428 #define BDW_SCRATCH1					_MMIO(0xb11c)
8432 #define _PIPEA_CHICKEN				0x70038
8433 #define _PIPEB_CHICKEN				0x71038
8434 #define _PIPEC_CHICKEN				0x72038
8442 #define FF_MODE2			_MMIO(0x6604)
8450 #define PCH_DISPLAY_BASE	0xc0000u
8490 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
8491 #define SDE_TRANS_MASK		(0x3f)
8530 #define SDE_FDI_RXA_CPT		(1 << 0)
8556 #define SDEISR  _MMIO(0xc4000)
8557 #define SDEIMR  _MMIO(0xc4004)
8558 #define SDEIIR  _MMIO(0xc4008)
8559 #define SDEIER  _MMIO(0xc400c)
8561 #define SERR_INT			_MMIO(0xc4040)
8566 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
8570 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
8574 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
8580 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
8585 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
8591 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
8596 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
8601 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
8602 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
8603 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
8604 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
8609 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
8611 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
8612 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
8613 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
8614 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
8621 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
8622 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
8623 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8624 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
8625 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
8626 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
8627 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8629 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
8634 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
8635 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
8637 #define _PCH_DPLL_A              0xc6014
8638 #define _PCH_DPLL_B              0xc6018
8639 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8641 #define _PCH_FPA0                0xc6040
8642 #define  FP_CB_TUNE		(0x3 << 22)
8643 #define _PCH_FPA1                0xc6044
8644 #define _PCH_FPB0                0xc6048
8645 #define _PCH_FPB1                0xc604c
8646 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8647 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8649 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8651 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8652 #define  DREF_CONTROL_MASK      0x7fc3
8653 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8657 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8660 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8664 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8667 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8669 #define  DREF_SSC1_DISABLE                      (0 << 1)
8671 #define  DREF_SSC4_DISABLE                      (0)
8674 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8679 #define  RAWCLK_FREQ_MASK       0x3ff
8680 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
8682 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
8686 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8688 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8689 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8691 #define PCH_DPLL_SEL		_MMIO(0xc7000)
8693 #define	 TRANS_DPLLA_SEL(pipe)		0
8698 #define _PCH_TRANS_HTOTAL_A		0xe0000
8700 #define  TRANS_HACTIVE_SHIFT		0
8701 #define _PCH_TRANS_HBLANK_A		0xe0004
8703 #define  TRANS_HBLANK_START_SHIFT	0
8704 #define _PCH_TRANS_HSYNC_A		0xe0008
8706 #define  TRANS_HSYNC_START_SHIFT	0
8707 #define _PCH_TRANS_VTOTAL_A		0xe000c
8709 #define  TRANS_VACTIVE_SHIFT		0
8710 #define _PCH_TRANS_VBLANK_A		0xe0010
8712 #define  TRANS_VBLANK_START_SHIFT	0
8713 #define _PCH_TRANS_VSYNC_A		0xe0014
8715 #define  TRANS_VSYNC_START_SHIFT	0
8716 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
8718 #define _PCH_TRANSA_DATA_M1	0xe0030
8719 #define _PCH_TRANSA_DATA_N1	0xe0034
8720 #define _PCH_TRANSA_DATA_M2	0xe0038
8721 #define _PCH_TRANSA_DATA_N2	0xe003c
8722 #define _PCH_TRANSA_LINK_M1	0xe0040
8723 #define _PCH_TRANSA_LINK_N1	0xe0044
8724 #define _PCH_TRANSA_LINK_M2	0xe0048
8725 #define _PCH_TRANSA_LINK_N2	0xe004c
8728 #define _VIDEO_DIP_CTL_A         0xe0200
8729 #define _VIDEO_DIP_DATA_A        0xe0208
8730 #define _VIDEO_DIP_GCP_A         0xe0210
8733 #define  GCP_AV_MUTE			(1 << 0)
8735 #define _VIDEO_DIP_CTL_B         0xe1200
8736 #define _VIDEO_DIP_DATA_B        0xe1208
8737 #define _VIDEO_DIP_GCP_B         0xe1210
8744 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
8745 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
8746 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
8748 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
8749 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
8750 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
8752 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
8753 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
8754 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
8768 #define _HSW_VIDEO_DIP_CTL_A		0x60200
8769 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
8770 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
8771 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
8772 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
8773 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
8774 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
8775 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
8776 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
8777 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
8778 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
8779 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
8780 #define _HSW_VIDEO_DIP_GCP_A		0x60210
8782 #define _HSW_VIDEO_DIP_CTL_B		0x61200
8783 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
8784 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
8785 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
8786 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
8787 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
8788 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
8789 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
8790 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
8791 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
8792 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
8793 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
8794 #define _HSW_VIDEO_DIP_GCP_B		0x61210
8802 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
8803 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
8804 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
8805 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
8818 #define _HSW_STEREO_3D_CTL_A		0x70020
8820 #define _HSW_STEREO_3D_CTL_B		0x71020
8824 #define _PCH_TRANS_HTOTAL_B          0xe1000
8825 #define _PCH_TRANS_HBLANK_B          0xe1004
8826 #define _PCH_TRANS_HSYNC_B           0xe1008
8827 #define _PCH_TRANS_VTOTAL_B          0xe100c
8828 #define _PCH_TRANS_VBLANK_B          0xe1010
8829 #define _PCH_TRANS_VSYNC_B           0xe1014
8830 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8840 #define _PCH_TRANSB_DATA_M1	0xe1030
8841 #define _PCH_TRANSB_DATA_N1	0xe1034
8842 #define _PCH_TRANSB_DATA_M2	0xe1038
8843 #define _PCH_TRANSB_DATA_N2	0xe103c
8844 #define _PCH_TRANSB_LINK_M1	0xe1040
8845 #define _PCH_TRANSB_LINK_N1	0xe1044
8846 #define _PCH_TRANSB_LINK_M2	0xe1048
8847 #define _PCH_TRANSB_LINK_N2	0xe104c
8858 #define _PCH_TRANSACONF              0xf0008
8859 #define _PCH_TRANSBCONF              0xf1008
8862 #define  TRANS_DISABLE          (0 << 31)
8865 #define  TRANS_STATE_DISABLE    (0 << 30)
8868 #define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
8870 #define  TRANS_PROGRESSIVE      (0 << 21)
8873 #define  TRANS_8BPC             (0 << 5)
8878 #define _TRANSA_CHICKEN1	 0xf0060
8879 #define _TRANSB_CHICKEN1	 0xf1060
8883 #define _TRANSA_CHICKEN2	 0xf0064
8884 #define _TRANSB_CHICKEN2	 0xf1064
8889 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)		((x) << 27) /* 0-3 */
8893 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
8903 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
8906 #define  SPT_PWM_GRANULARITY		(1 << 0)
8907 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
8911 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
8913 #define _FDI_RXA_CHICKEN        0xc200c
8914 #define _FDI_RXB_CHICKEN        0xc2010
8916 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
8919 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
8929 #define _FDI_TXA_CTL            0x60100
8930 #define _FDI_TXB_CTL            0x61100
8932 #define  FDI_TX_DISABLE         (0 << 31)
8934 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8938 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8942 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8946 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8949 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8950 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8951 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8952 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8954 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8955 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8956 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8957 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8958 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
8967 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8975 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8979 #define _FDI_RXA_CTL             0xf000c
8980 #define _FDI_RXB_CTL             0xf100c
8987 #define  FDI_8BPC                       (0 << 16)
9002 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
9008 #define _FDI_RXA_MISC			0xf0010
9009 #define _FDI_RXB_MISC			0xf1010
9016 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
9019 #define _FDI_RXA_TUSIZE1        0xf0030
9020 #define _FDI_RXA_TUSIZE2        0xf0038
9021 #define _FDI_RXB_TUSIZE1        0xf1030
9022 #define _FDI_RXB_TUSIZE2        0xf1038
9037 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
9039 #define _FDI_RXA_IIR            0xf0014
9040 #define _FDI_RXA_IMR            0xf0018
9041 #define _FDI_RXB_IIR            0xf1014
9042 #define _FDI_RXB_IMR            0xf1018
9046 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
9047 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
9049 #define PCH_LVDS	_MMIO(0xe1180)
9052 #define _PCH_DP_B		0xe4100
9054 #define _PCH_DPB_AUX_CH_CTL	0xe4110
9055 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
9056 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
9057 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
9058 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
9059 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
9061 #define _PCH_DP_C		0xe4200
9063 #define _PCH_DPC_AUX_CH_CTL	0xe4210
9064 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
9065 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
9066 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
9067 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
9068 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
9070 #define _PCH_DP_D		0xe4300
9072 #define _PCH_DPD_AUX_CH_CTL	0xe4310
9073 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
9074 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
9075 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
9076 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
9077 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
9083 #define _TRANS_DP_CTL_A		0xe0300
9084 #define _TRANS_DP_CTL_B		0xe1300
9085 #define _TRANS_DP_CTL_C		0xe2300
9093 #define  TRANS_DP_8BPC		(0 << 9)
9099 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
9101 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
9106 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
9107 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
9108 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
9109 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
9111 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
9112 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
9113 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
9114 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
9115 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
9116 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
9119 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
9120 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
9121 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
9122 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
9123 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
9124 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
9125 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
9128 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
9129 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
9130 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
9131 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
9132 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
9134 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
9136 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
9138 #define  RC6_LOCATION				_MMIO(0xD40)
9139 #define	   RC6_CTX_IN_DRAM			(1 << 0)
9140 #define  RC6_CTX_BASE				_MMIO(0xD48)
9141 #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
9142 #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
9143 #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
9144 #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
9145 #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
9146 #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
9147 #define    IDLE_TIME_MASK			0xFFFFF
9148 #define  FORCEWAKE				_MMIO(0xA18C)
9149 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
9150 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
9151 #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
9152 #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
9153 #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
9154 #define  FORCEWAKE_ACK				_MMIO(0x130090)
9155 #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
9158 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
9160 #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
9161 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
9165 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
9166 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
9167 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
9168 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
9169 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
9170 #define  FORCEWAKE_GT_GEN9			_MMIO(0xa188)
9171 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
9172 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
9173 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
9174 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
9175 #define  FORCEWAKE_ACK_GT_GEN9			_MMIO(0x130044)
9176 #define   FORCEWAKE_KERNEL			BIT(0)
9179 #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
9180 #define  ECOBUS					_MMIO(0xa180)
9182 #define  VLV_SPAREG2H				_MMIO(0xA194)
9183 #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
9184 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
9187 #define  GTFIFODBG				_MMIO(0x120000)
9188 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
9189 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
9196 #define    GT_FIFO_IARDERR			(1 << 0)
9198 #define  GTFIFOCTL				_MMIO(0x120008)
9199 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
9204 #define  HSW_IDICR				_MMIO(0x9008)
9205 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
9206 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
9207 #define    EDRAM_ENABLED			0x1
9208 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
9209 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
9210 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
9212 #define GEN6_UCGCTL1				_MMIO(0x9400)
9218 #define GEN6_UCGCTL2				_MMIO(0x9404)
9226 #define GEN6_UCGCTL3				_MMIO(0x9408)
9229 #define GEN7_UCGCTL4				_MMIO(0x940c)
9233 #define GEN6_RCGCTL1				_MMIO(0x9410)
9234 #define GEN6_RCGCTL2				_MMIO(0x9414)
9235 #define GEN6_RSTCTL				_MMIO(0x9420)
9237 #define GEN8_UCGCTL6				_MMIO(0x9430)
9242 #define GEN6_GFXPAUSE				_MMIO(0xA000)
9243 #define GEN6_RPNSWREQ				_MMIO(0xA008)
9249 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
9252 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
9253 #define GEN6_RC_CONTROL				_MMIO(0xA090)
9263 #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
9264 #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
9265 #define GEN6_RPSTAT1				_MMIO(0xA01C)
9269 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
9270 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
9271 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
9272 #define GEN6_RP_CONTROL				_MMIO(0xA024)
9278 #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
9281 #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
9282 #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
9283 #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
9284 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
9285 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
9286 #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
9287 #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
9288 #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
9289 #define   GEN6_RP_EI_MASK			0xffffff
9291 #define GEN6_RP_CUR_UP				_MMIO(0xA054)
9293 #define GEN6_RP_PREV_UP				_MMIO(0xA058)
9294 #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
9296 #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
9297 #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
9298 #define GEN6_RP_UP_EI				_MMIO(0xA068)
9299 #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
9300 #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
9301 #define GEN6_RPDEUHWTC				_MMIO(0xA080)
9302 #define GEN6_RPDEUC				_MMIO(0xA084)
9303 #define GEN6_RPDEUCSW				_MMIO(0xA088)
9304 #define GEN6_RC_STATE				_MMIO(0xA094)
9307 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
9308 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
9309 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9310 #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9311 #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
9312 #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
9313 #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
9314 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
9315 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
9316 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
9317 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
9318 #define VLV_RCEDATA				_MMIO(0xA0BC)
9319 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
9320 #define GEN6_PMINTRMSK				_MMIO(0xA168)
9323 #define GEN8_MISC_CTRL0				_MMIO(0xA180)
9324 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
9325 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
9326 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
9327 #define GEN9_PG_ENABLE				_MMIO(0xA210)
9328 #define   GEN9_RENDER_PG_ENABLE			REG_BIT(0)
9333 #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
9334 #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
9335 #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
9337 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
9341 #define GEN6_PMISR				_MMIO(0x44020)
9342 #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
9343 #define GEN6_PMIIR				_MMIO(0x44028)
9344 #define GEN6_PMIER				_MMIO(0x4402C)
9363 #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
9366 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
9370 #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
9371 #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
9376 #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
9377 #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
9378 #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
9379 #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
9381 #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
9382 #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
9383 #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
9384 #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
9386 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
9388 #define   GEN6_PCODE_ERROR_MASK			0xFF
9389 #define     GEN6_PCODE_SUCCESS			0x0
9390 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
9391 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9392 #define     GEN6_PCODE_TIMEOUT			0x3
9393 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
9394 #define     GEN7_PCODE_TIMEOUT			0x2
9395 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
9396 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
9397 #define     GEN11_PCODE_LOCKED			0x6
9398 #define     GEN11_PCODE_REJECTED		0x11
9399 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
9400 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
9401 #define   GEN6_PCODE_READ_RC6VIDS		0x5
9404 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
9405 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
9406 #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
9410 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
9411 #define   SKL_PCODE_CDCLK_CONTROL		0x7
9412 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
9413 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
9414 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
9415 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
9416 #define   GEN6_READ_OC_PARAMS			0xc
9417 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
9418 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
9419 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
9420 #define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
9421 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
9422 #define     ICL_PCODE_POINTS_RESTRICTED		0x0
9423 #define     ICL_PCODE_POINTS_RESTRICTED_MASK	0xf
9425 #define   ADLS_QGV_PT_MASK			REG_GENMASK(7, 0)
9427 #define   GEN6_PCODE_READ_D_COMP		0x10
9428 #define   GEN6_PCODE_WRITE_D_COMP		0x11
9429 #define   ICL_PCODE_EXIT_TCCOLD			0x12
9430 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
9431 #define   DISPLAY_IPS_CONTROL			0x19
9432 #define   TGL_PCODE_TCCOLD			0x26
9433 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
9434 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
9435 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
9438 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
9439 #define   GEN9_PCODE_SAGV_CONTROL		0x21
9440 #define     GEN9_SAGV_DISABLE			0x0
9441 #define     GEN9_SAGV_IS_DISABLED		0x1
9442 #define     GEN9_SAGV_ENABLE			0x3
9443 #define   DG1_PCODE_STATUS			0x7E
9444 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
9445 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
9446 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
9447 #define GEN6_PCODE_DATA				_MMIO(0x138128)
9450 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
9452 #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
9455 #define   GEN6_RC0			0
9460 #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
9461 #define   GEN8_LSLICESTAT_MASK		0x7
9463 #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
9464 #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
9470 #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
9471 #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
9474 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
9475 #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
9476 					      ((slice) % 3) * 0x4)
9477 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
9479 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9481 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
9482 #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
9483 					      ((slice) % 3) * 0x8)
9484 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
9485 #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9486 					      ((slice) % 3) * 0x8)
9487 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
9496 #define GEN7_MISCCPCTL				_MMIO(0x9424)
9497 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
9502 #define GEN8_GARBCNTL				_MMIO(0xB004)
9504 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
9505 #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
9506 #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
9508 #define GEN11_GLBLINVL				_MMIO(0xB404)
9509 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
9512 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
9515 #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
9516 #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
9517 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
9520 #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
9524 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
9529 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9530 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
9542 #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9543 #define GEN7_L3LOG_SIZE			0x80
9545 #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
9546 #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
9552 #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
9556 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
9563 #define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
9567 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
9568 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
9572 #define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
9576 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
9579 #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
9582 #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
9588 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
9594 #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9595 #define   INTEL_AUDIO_DEVCL		0x808629FB
9596 #define   INTEL_AUDIO_DEVBLC		0x80862801
9597 #define   INTEL_AUDIO_DEVCTG		0x80862802
9599 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
9602 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
9604 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
9606 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
9607 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
9610 #define _IBX_AUD_CNTL_ST_A		0xE20B4
9611 #define _IBX_AUD_CNTL_ST_B		0xE21B4
9614 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
9615 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
9617 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
9619 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
9621 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
9622 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
9624 #define _CPT_AUD_CNTL_ST_A		0xE50B4
9625 #define _CPT_AUD_CNTL_ST_B		0xE51B4
9627 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
9629 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
9630 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
9632 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
9633 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
9635 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
9641 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
9643 #define _IBX_AUD_CONFIG_A		0xe2000
9644 #define _IBX_AUD_CONFIG_B		0xe2100
9646 #define _CPT_AUD_CONFIG_A		0xe5000
9647 #define _CPT_AUD_CONFIG_B		0xe5100
9649 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
9650 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
9656 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
9658 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
9661 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
9662 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9664 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
9665 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
9682 #define _HSW_AUD_CONFIG_A		0x65000
9683 #define _HSW_AUD_CONFIG_B		0x65100
9686 #define _HSW_AUD_MISC_CTRL_A		0x65010
9687 #define _HSW_AUD_MISC_CTRL_B		0x65110
9690 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
9691 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
9695 #define   AUD_CONFIG_M_MASK		0xfffff
9697 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
9698 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
9702 #define _HSW_AUD_DIG_CNVT_1		0x65080
9703 #define _HSW_AUD_DIG_CNVT_2		0x65180
9705 #define DIP_PORT_SEL_MASK		0x3
9707 #define _HSW_AUD_EDID_DATA_A		0x65050
9708 #define _HSW_AUD_EDID_DATA_B		0x65150
9711 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
9712 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
9716 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
9718 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
9721 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
9722 #define AUD_PIN_BUF_CTL		_MMIO(0x48414)
9726 #define AUD_CONFIG_BE			_MMIO(0x65ef0)
9727 #define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
9728 #define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
9729 #define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
9730 #define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
9731 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
9732 #define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
9734 #define HBLANK_START_COUNT_8	0
9756 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
9757 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
9758 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
9759 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
9760 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
9761 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
9777 #define   SKL_PW_CTL_IDX_MISC_IO		0
9784 #define   ICL_PW_CTL_IDX_PW_1			0
9792 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
9793 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
9794 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
9818 #define   ICL_PW_CTL_IDX_AUX_A			0
9820 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
9821 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
9822 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
9836 #define   ICL_PW_CTL_IDX_DDI_A			0
9839 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
9843 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
9854 #define SKL_FUSE_STATUS				_MMIO(0x42000)
9871 #define _ICL_AUX_ANAOVRD1_A		0x162398
9872 #define _ICL_AUX_ANAOVRD1_B		0x6C398
9877 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
9880 #define HDCP_KEY_CONF			_MMIO(0x66c00)
9884 #define HDCP_KEY_STATUS			_MMIO(0x66c04)
9889 #define  HDCP_KEY_LOAD_DONE		BIT(0)
9890 #define HDCP_AKSV_LO			_MMIO(0x66c10)
9891 #define HDCP_AKSV_HI			_MMIO(0x66c14)
9894 #define HDCP_REP_CTL			_MMIO(0x66d00)
9925 #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
9926 #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
9927 #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
9928 #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
9929 #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9930 #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
9931 #define HDCP_SHA_TEXT			_MMIO(0x66d18)
9934 #define _PORTA_HDCP_AUTHENC		0x66800
9935 #define _PORTB_HDCP_AUTHENC		0x66500
9936 #define _PORTC_HDCP_AUTHENC		0x66600
9937 #define _PORTD_HDCP_AUTHENC		0x66700
9938 #define _PORTE_HDCP_AUTHENC		0x66A00
9939 #define _PORTF_HDCP_AUTHENC		0x66900
9947 #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
9948 #define _TRANSA_HDCP_CONF		0x66400
9949 #define _TRANSB_HDCP_CONF		0x66500
9957 #define  HDCP_CONF_CAPTURE_AN		BIT(0)
9958 #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
9959 #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
9960 #define _TRANSA_HDCP_ANINIT		0x66404
9961 #define _TRANSB_HDCP_ANINIT		0x66504
9970 #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
9971 #define _TRANSA_HDCP_ANLO		0x66408
9972 #define _TRANSB_HDCP_ANLO		0x66508
9980 #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
9981 #define _TRANSA_HDCP_ANHI		0x6640C
9982 #define _TRANSB_HDCP_ANHI		0x6650C
9990 #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
9991 #define _TRANSA_HDCP_BKSVLO		0x66410
9992 #define _TRANSB_HDCP_BKSVLO		0x66510
10001 #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
10002 #define _TRANSA_HDCP_BKSVHI		0x66414
10003 #define _TRANSB_HDCP_BKSVHI		0x66514
10012 #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
10013 #define _TRANSA_HDCP_RPRIME		0x66418
10014 #define _TRANSB_HDCP_RPRIME		0x66518
10023 #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
10024 #define _TRANSA_HDCP_STATUS		0x6641C
10025 #define _TRANSB_HDCP_STATUS		0x6651C
10044 #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
10047 #define _PORTA_HDCP2_BASE		0x66800
10048 #define _PORTB_HDCP2_BASE		0x66500
10049 #define _PORTC_HDCP2_BASE		0x66600
10050 #define _PORTD_HDCP2_BASE		0x66700
10051 #define _PORTE_HDCP2_BASE		0x66A00
10052 #define _PORTF_HDCP2_BASE		0x66900
10061 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
10062 #define _TRANSA_HDCP2_AUTH		0x66498
10063 #define _TRANSB_HDCP2_AUTH		0x66598
10075 #define PORT_HDCP2_CTL(port)		_PORT_HDCP2_BASE(port, 0xB0)
10076 #define _TRANSA_HDCP2_CTL		0x664B0
10077 #define _TRANSB_HDCP2_CTL		0x665B0
10086 #define PORT_HDCP2_STATUS(port)		_PORT_HDCP2_BASE(port, 0xB4)
10087 #define _TRANSA_HDCP2_STATUS		0x664B4
10088 #define _TRANSB_HDCP2_STATUS		0x665B4
10100 #define _PIPEA_HDCP2_STREAM_STATUS	0x668C0
10101 #define _PIPEB_HDCP2_STREAM_STATUS	0x665C0
10102 #define _PIPEC_HDCP2_STREAM_STATUS	0x666C0
10103 #define _PIPED_HDCP2_STREAM_STATUS	0x667C0
10110 #define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
10111 #define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
10122 #define _PORTA_HDCP2_AUTH_STREAM		0x66F00
10123 #define _PORTB_HDCP2_AUTH_STREAM		0x66F04
10127 #define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
10128 #define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
10139 #define _TRANS_DDI_FUNC_CTL_A		0x60400
10140 #define _TRANS_DDI_FUNC_CTL_B		0x61400
10141 #define _TRANS_DDI_FUNC_CTL_C		0x62400
10142 #define _TRANS_DDI_FUNC_CTL_D		0x63400
10143 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
10144 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
10145 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
10153 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
10159 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
10165 #define  TRANS_DDI_BPC_8		(0 << 20)
10175 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
10190 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
10195 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
10196 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
10197 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
10198 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
10199 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
10200 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
10203 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
10206 #define TRANS_CMTG_CHICKEN		_MMIO(0x6fa90)
10210 #define _DP_TP_CTL_A			0x64040
10211 #define _DP_TP_CTL_B			0x64140
10212 #define _TGL_DP_TP_CTL_A		0x60540
10217 #define  DP_TP_CTL_MODE_SST			(0 << 27)
10223 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
10232 #define _DP_TP_STATUS_A			0x64044
10233 #define _DP_TP_STATUS_B			0x64144
10234 #define _TGL_DP_TP_STATUS_A		0x60544
10244 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
10247 #define _DDI_BUF_CTL_A				0x64000
10248 #define _DDI_BUF_CTL_B				0x64100
10252 #define  DDI_BUF_EMP_MASK			(0xf << 24)
10261 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
10264 #define _DDI_BUF_TRANS_A		0x64E00
10265 #define _DDI_BUF_TRANS_B		0x64E60
10271 #define _DDI_DP_COMP_CTL_A			0x605F0
10272 #define _DDI_DP_COMP_CTL_B			0x615F0
10275 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
10281 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
10284 #define _DDI_DP_COMP_PAT_A			0x605F4
10285 #define _DDI_DP_COMP_PAT_B			0x615F4
10291 #define SBI_ADDR			_MMIO(0xC6000)
10292 #define SBI_DATA			_MMIO(0xC6004)
10293 #define SBI_CTL_STAT			_MMIO(0xC6008)
10294 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
10295 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
10296 #define  SBI_CTL_OP_IORD		(0x2 << 8)
10297 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
10298 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
10299 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
10300 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
10301 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
10302 #define  SBI_BUSY			(0x1 << 0)
10303 #define  SBI_READY			(0x0 << 0)
10306 #define  SBI_SSCDIVINTPHASE			0x0200
10307 #define  SBI_SSCDIVINTPHASE6			0x0600
10309 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
10312 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
10315 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
10316 #define  SBI_SSCDITHPHASE			0x0204
10317 #define  SBI_SSCCTL				0x020c
10318 #define  SBI_SSCCTL6				0x060C
10320 #define   SBI_SSCCTL_DISABLE			(1 << 0)
10321 #define  SBI_SSCAUXDIV6				0x0610
10325 #define  SBI_DBUFF0				0x2a00
10326 #define  SBI_GEN0				0x1f00
10327 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
10330 #define PIXCLK_GATE			_MMIO(0xC6020)
10331 #define  PIXCLK_GATE_UNGATE		(1 << 0)
10332 #define  PIXCLK_GATE_GATE		(0 << 0)
10335 #define SPLL_CTL			_MMIO(0x46020)
10337 #define  SPLL_REF_BCLK			(0 << 28)
10343 #define  SPLL_FREQ_810MHz		(0 << 26)
10349 #define _WRPLL_CTL1			0x46040
10350 #define _WRPLL_CTL2			0x46060
10353 #define  WRPLL_REF_BCLK			(0 << 28)
10360 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
10361 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
10363 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
10367 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
10370 #define _PORT_CLK_SEL_A			0x46100
10371 #define _PORT_CLK_SEL_B			0x46104
10373 #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
10385 #define  DDI_CLK_SEL_NONE		(0x0 << 28)
10386 #define  DDI_CLK_SEL_MG			(0x8 << 28)
10387 #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
10388 #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
10389 #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
10390 #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
10391 #define  DDI_CLK_SEL_MASK		(0xF << 28)
10394 #define _TRANS_CLK_SEL_A		0x46140
10395 #define _TRANS_CLK_SEL_B		0x46144
10398 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
10400 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
10404 #define CDCLK_FREQ			_MMIO(0x46200)
10406 #define _TRANSA_MSA_MISC		0x60410
10407 #define _TRANSB_MSA_MISC		0x61410
10408 #define _TRANSC_MSA_MISC		0x62410
10409 #define _TRANS_EDP_MSA_MISC		0x6f410
10413 #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
10414 #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
10415 #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
10416 #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
10418 #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
10422 #define LCPLL_CTL			_MMIO(0x130040)
10425 #define  LCPLL_REF_NON_SSC		(0 << 28)
10430 #define  LCPLL_CLK_FREQ_450		(0 << 26)
10446 #define CDCLK_CTL			_MMIO(0x46000)
10448 #define  CDCLK_FREQ_450_432		(0 << 26)
10453 #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
10460 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
10465 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
10468 #define LCPLL1_CTL		_MMIO(0x46010)
10469 #define LCPLL2_CTL		_MMIO(0x46014)
10473 #define DPLL_CTRL1		_MMIO(0x6C058)
10480 #define  DPLL_CTRL1_LINK_RATE_2700		0
10488 #define DPLL_CTRL2				_MMIO(0x6C05C)
10496 #define DPLL_STATUS	_MMIO(0x6C060)
10500 #define _DPLL1_CFGCR1	0x6C040
10501 #define _DPLL2_CFGCR1	0x6C048
10502 #define _DPLL3_CFGCR1	0x6C050
10504 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
10506 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
10508 #define _DPLL1_CFGCR2	0x6C044
10509 #define _DPLL2_CFGCR2	0x6C04C
10510 #define _DPLL3_CFGCR2	0x6C054
10511 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
10516 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
10522 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
10533 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
10542 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
10554 #define _DG1_DPCLKA_CFGCR0				0x164280
10555 #define _DG1_DPCLKA1_CFGCR0				0x16C280
10564 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10567 #define _ADLS_DPCLKA_CFGCR0			0x164280
10568 #define _ADLS_DPCLKA_CFGCR1			0x1642BC
10576 #define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
10579 #define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
10588 #define DPLL0_ENABLE		0x46010
10589 #define DPLL1_ENABLE		0x46014
10590 #define _ADLS_DPLL2_ENABLE	0x46018
10591 #define _ADLS_DPLL3_ENABLE	0x46030
10599 #define _DG2_PLL3_ENABLE	0x4601C
10604 #define TBT_PLL_ENABLE		_MMIO(0x46020)
10606 #define _MG_PLL1_ENABLE		0x46030
10607 #define _MG_PLL2_ENABLE		0x46034
10608 #define _MG_PLL3_ENABLE		0x46038
10609 #define _MG_PLL4_ENABLE		0x4603C
10619 #define PORTTC1_PLL_ENABLE	0x46038
10620 #define PORTTC2_PLL_ENABLE	0x46040
10626 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
10627 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
10628 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
10629 #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
10631 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
10636 #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
10637 #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
10638 #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
10639 #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
10641 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
10643 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
10648 #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
10649 #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
10650 #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
10651 #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
10653 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
10655 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
10656 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
10657 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
10663 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
10668 #define _MG_PLL_DIV0_PORT1				0x168A00
10669 #define _MG_PLL_DIV0_PORT2				0x169A00
10670 #define _MG_PLL_DIV0_PORT3				0x16AA00
10671 #define _MG_PLL_DIV0_PORT4				0x16BA00
10673 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
10676 #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
10677 #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
10681 #define _MG_PLL_DIV1_PORT1				0x168A04
10682 #define _MG_PLL_DIV1_PORT2				0x169A04
10683 #define _MG_PLL_DIV1_PORT3				0x16AA04
10684 #define _MG_PLL_DIV1_PORT4				0x16BA04
10686 #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
10691 #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
10692 #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
10696 #define _MG_PLL_LF_PORT1				0x168A08
10697 #define _MG_PLL_LF_PORT2				0x169A08
10698 #define _MG_PLL_LF_PORT3				0x16AA08
10699 #define _MG_PLL_LF_PORT4				0x16BA08
10701 #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
10705 #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
10709 #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
10710 #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
10711 #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
10712 #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
10718 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
10723 #define _MG_PLL_SSC_PORT1				0x168A10
10724 #define _MG_PLL_SSC_PORT2				0x169A10
10725 #define _MG_PLL_SSC_PORT3				0x16AA10
10726 #define _MG_PLL_SSC_PORT4				0x16BA10
10732 #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
10736 #define _MG_PLL_BIAS_PORT1				0x168A14
10737 #define _MG_PLL_BIAS_PORT2				0x169A14
10738 #define _MG_PLL_BIAS_PORT3				0x16AA14
10739 #define _MG_PLL_BIAS_PORT4				0x16BA14
10741 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
10743 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
10745 #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
10748 #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
10750 #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
10751 #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
10752 #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
10756 #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
10757 #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
10758 #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
10759 #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
10764 #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
10769 #define _ICL_DPLL0_CFGCR0		0x164000
10770 #define _ICL_DPLL1_CFGCR0		0x164080
10776 #define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
10777 #define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
10785 #define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
10788 #define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
10790 #define _ICL_DPLL0_CFGCR1		0x164004
10791 #define _ICL_DPLL1_CFGCR1		0x164084
10794 #define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
10805 #define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
10812 #define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
10813 #define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
10814 #define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
10816 #define _TGL_DPLL0_CFGCR0		0x164284
10817 #define _TGL_DPLL1_CFGCR0		0x16428C
10818 #define _TGL_TBTPLL_CFGCR0		0x16429C
10825 #define _TGL_DPLL0_CFGCR1		0x164288
10826 #define _TGL_DPLL1_CFGCR1		0x164290
10827 #define _TGL_TBTPLL_CFGCR1		0x1642A0
10834 #define _DG1_DPLL2_CFGCR0		0x16C284
10835 #define _DG1_DPLL3_CFGCR0		0x16C28C
10841 #define _DG1_DPLL2_CFGCR1               0x16C288
10842 #define _DG1_DPLL3_CFGCR1               0x16C290
10849 #define _ADLS_DPLL3_CFGCR0		0x1642C0
10850 #define _ADLS_DPLL4_CFGCR0		0x164294
10856 #define _ADLS_DPLL3_CFGCR1		0x1642C4
10857 #define _ADLS_DPLL4_CFGCR1		0x164298
10863 #define _DKL_PHY1_BASE			0x168000
10864 #define _DKL_PHY2_BASE			0x169000
10865 #define _DKL_PHY3_BASE			0x16A000
10866 #define _DKL_PHY4_BASE			0x16B000
10867 #define _DKL_PHY5_BASE			0x16C000
10868 #define _DKL_PHY6_BASE			0x16D000
10871 #define _DKL_PLL_DIV0			0x200
10873 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
10875 #define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
10878 #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10879 #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
10880 #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
10885 #define _DKL_PLL_DIV1				0x204
10887 #define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
10888 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
10889 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
10894 #define _DKL_PLL_SSC				0x210
10896 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
10898 #define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
10900 #define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
10906 #define _DKL_PLL_BIAS			0x214
10910 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10915 #define _DKL_PLL_TDC_COLDST_BIAS		0x218
10917 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
10918 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
10919 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
10925 #define _DKL_REFCLKIN_CTL		0x12C
10932 #define _DKL_CLKTOP2_HSCLKCTL		0xD4
10939 #define _DKL_CLKTOP2_CORECLKCTL1		0xD8
10946 #define _DKL_TX_DPCNTL0				0x2C0
10948 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
10950 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK		(0x1f << 8)
10951 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
10952 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
10958 #define _DKL_TX_DPCNTL1				0x2C4
10965 #define _DKL_TX_DPCNTL2				0x2C8
10973 #define _DKL_TX_FW_CALIB				0x2F8
10980 #define _DKL_TX_PMD_LANE_SUS				0xD00
10986 #define _DKL_TX_DW17					0xDC4
10992 #define _DKL_TX_DW18					0xDC8
10998 #define _DKL_DP_MODE					0xA0
11004 #define _DKL_CMN_UC_DW27			0x36C
11005 #define  DKL_CMN_UC_DW27_UC_HEALTH		(0x1 << 15)
11017 #define _HIP_INDEX_REG0			0x1010A0
11018 #define _HIP_INDEX_REG1			0x1010A4
11025 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
11027 #define   BXT_DE_PLL_RATIO_MASK		0xff
11029 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
11035 #define   ICL_CDCLK_PLL_RATIO_MASK	0xff
11038 #define DC_STATE_EN			_MMIO(0x45504)
11039 #define  DC_STATE_DISABLE		0
11042 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
11044 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
11045 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
11047 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
11048 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
11051 #define BXT_D_CR_DRP0_DUNIT8			0x1000
11052 #define BXT_D_CR_DRP0_DUNIT9			0x1200
11058 #define  BXT_DRAM_RANK_MASK			0x3
11059 #define  BXT_DRAM_RANK_SINGLE			0x1
11060 #define  BXT_DRAM_RANK_DUAL			0x3
11061 #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
11063 #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
11064 #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
11065 #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
11066 #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
11067 #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
11069 #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
11070 #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
11071 #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
11072 #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
11073 #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
11074 #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
11076 #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
11077 #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
11078 #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
11079 #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
11081 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
11084 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
11085 #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
11086 #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
11087 #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
11088 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
11089 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
11091 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
11092 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
11094 #define  SKL_DRAM_SIZE_MASK			0x3F
11095 #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
11097 #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
11098 #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
11099 #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
11100 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
11102 #define  SKL_DRAM_RANK_1			(0x0 << 10)
11103 #define  SKL_DRAM_RANK_2			(0x1 << 10)
11104 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
11105 #define  ICL_DRAM_SIZE_MASK			0x7F
11106 #define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
11108 #define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
11109 #define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
11110 #define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
11111 #define  ICL_DRAM_RANK_MASK			(0x3 << 9)
11113 #define  ICL_DRAM_RANK_1			(0x0 << 9)
11114 #define  ICL_DRAM_RANK_2			(0x1 << 9)
11115 #define  ICL_DRAM_RANK_3			(0x2 << 9)
11116 #define  ICL_DRAM_RANK_4			(0x3 << 9)
11118 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
11122 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
11124 #define   DG1_DRAM_T_RP_MASK			REG_GENMASK(6, 0)
11125 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
11133 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
11134 #define D_COMP_BDW			_MMIO(0x138144)
11137 #define  D_COMP_COMP_DISABLE		(1 << 0)
11140 #define _WM_LINETIME_A		0x45270
11141 #define _WM_LINETIME_B		0x45274
11143 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
11149 #define SFUSE_STRAP			_MMIO(0xc2014)
11157 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
11159 #define WM_MISC				_MMIO(0x45260)
11160 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
11162 #define WM_DBG				_MMIO(0x45280)
11163 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
11168 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
11169 #define _PIPE_A_CSC_COEFF_BY	0x49014
11170 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
11171 #define _PIPE_A_CSC_COEFF_BU	0x4901c
11172 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
11173 #define _PIPE_A_CSC_COEFF_BV	0x49024
11175 #define _PIPE_A_CSC_MODE	0x49028
11180 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
11182 #define _PIPE_A_CSC_PREOFF_HI	0x49030
11183 #define _PIPE_A_CSC_PREOFF_ME	0x49034
11184 #define _PIPE_A_CSC_PREOFF_LO	0x49038
11185 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
11186 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
11187 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
11189 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
11190 #define _PIPE_B_CSC_COEFF_BY	0x49114
11191 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
11192 #define _PIPE_B_CSC_COEFF_BU	0x4911c
11193 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
11194 #define _PIPE_B_CSC_COEFF_BV	0x49124
11195 #define _PIPE_B_CSC_MODE	0x49128
11196 #define _PIPE_B_CSC_PREOFF_HI	0x49130
11197 #define _PIPE_B_CSC_PREOFF_ME	0x49134
11198 #define _PIPE_B_CSC_PREOFF_LO	0x49138
11199 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
11200 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
11201 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
11218 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
11219 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
11220 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
11221 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
11222 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
11223 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
11224 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
11225 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
11226 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
11227 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
11228 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
11229 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
11231 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
11232 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
11233 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
11234 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
11235 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
11236 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
11237 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
11238 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
11239 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
11240 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
11241 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
11242 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
11282 #define _PAL_PREC_INDEX_A	0x4A400
11283 #define _PAL_PREC_INDEX_B	0x4AC00
11284 #define _PAL_PREC_INDEX_C	0x4B400
11285 #define   PAL_PREC_10_12_BIT		(0 << 31)
11288 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
11289 #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
11290 #define _PAL_PREC_DATA_A	0x4A404
11291 #define _PAL_PREC_DATA_B	0x4AC04
11292 #define _PAL_PREC_DATA_C	0x4B404
11293 #define _PAL_PREC_GC_MAX_A	0x4A410
11294 #define _PAL_PREC_GC_MAX_B	0x4AC10
11295 #define _PAL_PREC_GC_MAX_C	0x4B410
11298 #define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
11299 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
11300 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
11301 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
11302 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
11303 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
11304 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
11312 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
11313 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
11314 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
11316 #define _PRE_CSC_GAMC_DATA_A	0x4A488
11317 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
11318 #define _PRE_CSC_GAMC_DATA_C	0x4B488
11324 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
11325 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
11327 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
11329 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
11330 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
11336 #define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
11346 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
11347 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
11348 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
11349 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
11350 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
11351 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
11352 #define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
11354 #define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
11355 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
11356 #define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
11358 #define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
11359 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
11362 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
11364 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
11365 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
11366 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
11367 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
11368 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
11369 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
11370 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
11371 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
11391 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
11392 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
11393 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
11394 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
11396 #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
11397 #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
11401 #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
11402 #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
11406 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
11408 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
11409 #define  ICL_ESC_CLK_DIV_SHIFT			0
11412 #define _ADL_MIPIO_REG			0x180
11416 #define   TX_ESC_CLK_DIV_PHY		REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
11418 #define _DSI_CMD_FRMCTL_0		0x6b034
11419 #define _DSI_CMD_FRMCTL_1		0x6b834
11426 #define   DSI_FRAME_IN_PROGRESS			(1 << 0)
11428 #define _DSI_INTR_MASK_REG_0		0x6b070
11429 #define _DSI_INTR_MASK_REG_1		0x6b870
11434 #define _DSI_INTR_IDENT_REG_0		0x6b074
11435 #define _DSI_INTR_IDENT_REG_1		0x6b874
11467 #define   DSI_SOT_ERROR				(1 << 0)
11470 #define GEN4_TIMESTAMP		_MMIO(0x2358)
11471 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
11472 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
11474 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
11475 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
11476 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
11478 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
11480 #define _PIPE_FRMTMSTMP_A		0x70048
11487 #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
11500 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
11501 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
11506 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
11535 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
11540 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
11547 #define RX_DIVIDER_BIT_1_2                     0x3
11548 #define RX_DIVIDER_BIT_3_4                     0xC
11551 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
11552 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
11556 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
11557 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
11561 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
11562 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
11566 #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
11570 #define  BXT_DSIC_16X_BY1		(0 << 10)
11575 #define  BXT_DSIA_16X_BY1		(0 << 8)
11581 #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
11583 #define BXT_DSI_PLL_RATIO_MAX		0x7D
11584 #define BXT_DSI_PLL_RATIO_MIN		0x22
11585 #define GLK_DSI_PLL_RATIO_MAX		0x6F
11586 #define GLK_DSI_PLL_RATIO_MIN		0x22
11587 #define BXT_DSI_PLL_RATIO_MASK		0xFF
11590 #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
11594 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
11595 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
11599 #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
11600 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
11604 #define _ICL_DSI_IO_MODECTL_0				0x6B094
11605 #define _ICL_DSI_IO_MODECTL_1				0x6B894
11609 #define  COMBO_PHY_MODE_DSI				(1 << 0)
11612 #define DSS_CTL1				_MMIO(0x67400)
11616 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
11617 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
11619 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11620 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11621 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
11623 #define DSS_CTL2				_MMIO(0x67404)
11626 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11627 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11629 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
11630 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
11638 #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
11643 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
11644 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
11649 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
11650 #define  STAP_SELECT					(1 << 0)
11652 #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
11653 #define  HS_IO_CTRL_SELECT				(1 << 0)
11657 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
11660 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
11666 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
11672 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
11675 #define  CSB_20MHZ					(0 << 9)
11679 #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
11686 #define  TEARING_EFFECT_OFF				(0 << 2)
11689 #define  LANE_CONFIGURATION_SHIFT			0
11690 #define  LANE_CONFIGURATION_MASK			(3 << 0)
11691 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
11692 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
11693 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
11695 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
11696 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
11698 #define  TEARING_EFFECT_DELAY_SHIFT			0
11699 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
11702 #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
11706 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
11707 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
11713 #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
11714 #define  DEVICE_READY					(1 << 0)
11716 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
11717 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
11719 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
11720 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
11753 #define  RXSOT_ERROR					(1 << 0)
11755 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
11756 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
11759 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
11765 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
11766 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
11775 #define  DATA_LANES_PRG_REG_SHIFT			0
11776 #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
11778 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
11779 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
11781 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
11783 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
11784 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
11786 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
11788 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
11789 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
11791 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
11793 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
11794 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
11796 #define  DEVICE_RESET_TIMER_MASK			0xffff
11798 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
11799 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
11802 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
11803 #define  HORIZONTAL_ADDRESS_SHIFT			0
11804 #define  HORIZONTAL_ADDRESS_MASK			0xffff
11806 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
11807 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
11809 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
11810 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
11811 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
11813 /* regs below are bits 15:0 */
11814 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
11815 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
11818 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
11819 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
11822 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
11823 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
11826 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
11827 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
11830 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
11831 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
11834 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
11835 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
11838 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
11839 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
11842 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
11843 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
11846 /* regs above are bits 15:0 */
11848 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
11849 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
11857 #define  SHUTDOWN					(1 << 0)
11859 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
11860 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
11862 #define  COMMAND_BYTE_SHIFT				0
11863 #define  COMMAND_BYTE_MASK				(0x3f << 0)
11865 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
11866 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
11868 #define  MASTER_INIT_TIMER_SHIFT			0
11869 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
11871 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
11872 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
11875 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
11876 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
11878 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
11879 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
11884 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
11885 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
11886 #define  VIDEO_MODE_BURST				(3 << 0)
11888 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
11889 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
11900 #define  EOT_DISABLE					(1 << 0)
11902 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
11903 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
11905 #define  LP_BYTECLK_SHIFT				0
11906 #define  LP_BYTECLK_MASK				(0xffff << 0)
11908 #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
11909 #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
11912 #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
11913 #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
11916 /* bits 31:0 */
11917 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
11918 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
11921 /* bits 31:0 */
11922 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
11923 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
11926 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
11927 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
11929 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
11930 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
11933 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
11935 #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
11938 #define  DATA_TYPE_SHIFT				0
11939 #define  DATA_TYPE_MASK					(0x3f << 0)
11942 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
11943 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
11958 #define  HS_DATA_FIFO_FULL				(1 << 0)
11960 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
11961 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
11963 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
11964 #define  DBI_LP_MODE					(1 << 0)
11965 #define  DBI_HS_MODE					(0 << 0)
11967 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
11968 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
11971 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
11973 #define  TRAIL_COUNT_MASK				(0x1f << 16)
11975 #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
11976 #define  PREPARE_COUNT_SHIFT				0
11977 #define  PREPARE_COUNT_MASK				(0x3f << 0)
11979 #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
11980 #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
11985 #define _DPHY_CLK_TIMING_PARAM_0	0x162180
11986 #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
11990 #define _DSI_CLK_TIMING_PARAM_0		0x6b080
11991 #define _DSI_CLK_TIMING_PARAM_1		0x6b880
11997 #define  CLK_PREPARE_MASK		(0x7 << 28)
12001 #define  CLK_ZERO_MASK			(0xf << 20)
12005 #define  CLK_PRE_MASK			(0x3 << 16)
12009 #define  CLK_POST_MASK			(0x7 << 8)
12012 #define  CLK_TRAIL(x)			((x) << 0)
12013 #define  CLK_TRAIL_MASK		(0xf << 0)
12014 #define  CLK_TRAIL_SHIFT		0
12016 #define _DPHY_DATA_TIMING_PARAM_0	0x162184
12017 #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
12021 #define _DSI_DATA_TIMING_PARAM_0	0x6B084
12022 #define _DSI_DATA_TIMING_PARAM_1	0x6B884
12028 #define  HS_PREPARE_MASK		(0x7 << 24)
12032 #define  HS_ZERO_MASK			(0xf << 16)
12036 #define  HS_TRAIL_MASK			(0x7 << 8)
12039 #define  HS_EXIT(x)			((x) << 0)
12040 #define  HS_EXIT_MASK			(0x7 << 0)
12041 #define  HS_EXIT_SHIFT			0
12043 #define _DPHY_TA_TIMING_PARAM_0		0x162188
12044 #define _DPHY_TA_TIMING_PARAM_1		0x6c188
12048 #define _DSI_TA_TIMING_PARAM_0		0x6b098
12049 #define _DSI_TA_TIMING_PARAM_1		0x6b898
12055 #define  TA_SURE_MASK			(0x1f << 16)
12059 #define  TA_GO_MASK			(0xf << 8)
12062 #define  TA_GET(x)			((x) << 0)
12063 #define  TA_GET_MASK			(0xf << 0)
12064 #define  TA_GET_SHIFT			0
12067 #define _DSI_TRANS_FUNC_CONF_0		0x6b030
12068 #define _DSI_TRANS_FUNC_CONF_1		0x6b830
12072 #define  OP_MODE_MASK			(0x3 << 28)
12074 #define  CMD_MODE_NO_GATE		(0x0 << 28)
12075 #define  CMD_MODE_TE_GATE		(0x1 << 28)
12076 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
12077 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
12080 #define  PIX_FMT_MASK			(0x3 << 16)
12082 #define  PIX_FMT_RGB565			(0x0 << 16)
12083 #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
12084 #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
12085 #define  PIX_FMT_RGB888			(0x3 << 16)
12086 #define  PIX_FMT_RGB101010		(0x4 << 16)
12087 #define  PIX_FMT_RGB121212		(0x5 << 16)
12088 #define  PIX_FMT_COMPRESSED		(0x6 << 16)
12091 #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
12093 #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
12095 #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
12096 #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
12097 #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
12098 #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
12099 #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
12101 #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
12102 #define  CLK_HS_OR_LP			(0x2 << 8)
12103 #define  CLK_HS_CONTINUOUS		(0x3 << 8)
12104 #define  LINK_CALIBRATION_MASK		(0x3 << 4)
12106 #define  CALIBRATION_DISABLED		(0x0 << 4)
12107 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
12108 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
12111 #define  EOTP_DISABLED			(1 << 0)
12113 #define _DSI_CMD_RXCTL_0		0x6b0d4
12114 #define _DSI_CMD_RXCTL_1		0x6b8d4
12125 #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
12126 #define  NUMBER_RX_PLOAD_DW_SHIFT	0
12128 #define _DSI_CMD_TXCTL_0		0x6b0d0
12129 #define _DSI_CMD_TXCTL_1		0x6b8d0
12134 #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
12135 #define  FREE_HEADER_CREDIT_SHIFT	0x8
12136 #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
12137 #define  FREE_PLOAD_CREDIT_SHIFT	0
12138 #define  MAX_HEADER_CREDIT		0x10
12139 #define  MAX_PLOAD_CREDIT		0x40
12141 #define _DSI_CMD_TXHDR_0		0x6b100
12142 #define _DSI_CMD_TXHDR_1		0x6b900
12149 #define  PARAM_WC_MASK			(0xffff << 8)
12152 #define  VC_MASK			(0x3 << 6)
12154 #define  DT_MASK			(0x3f << 0)
12155 #define  DT_SHIFT			0
12157 #define _DSI_CMD_TXPYLD_0		0x6b104
12158 #define _DSI_CMD_TXPYLD_1		0x6b904
12163 #define _DSI_LP_MSG_0			0x6b0d8
12164 #define _DSI_LP_MSG_1			0x6b8d8
12171 #define  LINK_ENTER_ULPS		(1 << 0)
12174 #define _DSI_HSTX_TO_0			0x6b044
12175 #define _DSI_HSTX_TO_1			0x6b844
12179 #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
12182 #define  HSTX_TIMED_OUT			(1 << 0)
12184 #define _DSI_LPRX_HOST_TO_0		0x6b048
12185 #define _DSI_LPRX_HOST_TO_1		0x6b848
12190 #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
12191 #define  LPRX_TIMEOUT_VALUE_SHIFT	0
12192 #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
12194 #define _DSI_PWAIT_TO_0			0x6b040
12195 #define _DSI_PWAIT_TO_1			0x6b840
12199 #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
12202 #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
12203 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
12204 #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
12206 #define _DSI_TA_TO_0			0x6b04c
12207 #define _DSI_TA_TO_1			0x6b84c
12212 #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
12213 #define  TA_TIMEOUT_VALUE_SHIFT		0
12214 #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
12216 /* bits 31:0 */
12217 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
12218 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
12221 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
12222 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
12225 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
12226 #define  HS_LP_PWR_SW_CNT_SHIFT				0
12227 #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
12229 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
12230 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
12232 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
12233 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
12235 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
12236 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
12238 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
12239 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
12241 #define  RX_CONTENTION_DETECTED				(1 << 0)
12244 #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
12250 #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
12252 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
12253 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
12258 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
12259 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
12263 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
12268 #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
12284 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
12289 #define  GLK_MIPIIO_ENABLE				(1 << 0)
12291 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
12292 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
12295 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
12296 #define  DATA_VALID					(1 << 0)
12298 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
12299 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
12301 #define  DATA_LENGTH_SHIFT				0
12302 #define  DATA_LENGTH_MASK				(0xfffff << 0)
12304 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
12305 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
12308 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
12311 #define  COMMAND_VALID					(1 << 0)
12313 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
12314 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
12316 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
12317 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
12319 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
12320 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
12321 … n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
12323 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
12324 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
12329 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
12332 #define __GEN9_RCS0_MOCS0	0xc800
12334 #define __GEN9_VCS0_MOCS0	0xc900
12336 #define __GEN9_VCS1_MOCS0	0xca00
12338 #define __GEN9_VECS0_MOCS0	0xcb00
12340 #define __GEN9_BCS0_MOCS0	0xcc00
12342 #define __GEN11_VCS2_MOCS0	0x10000
12345 #define GEN9_SCRATCH_LNCF1		_MMIO(0xb008)
12346 #define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
12348 #define GEN9_SCRATCH1			_MMIO(0xb11c)
12351 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
12356 #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
12358 #define GEN12_GSMBASE			_MMIO(0x108100)
12359 #define GEN12_DSMBASE			_MMIO(0x1080C0)
12362 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12363 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
12364 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
12365 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
12366 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
12368 #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
12372 #define _ICL_PHY_MISC_A		0x64C00
12373 #define _ICL_PHY_MISC_B		0x64C04
12381 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
12382 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
12383 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
12384 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
12385 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
12386 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
12400 #define  DSC_VER_MAJ			(0x1 << 0)
12402 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
12403 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
12404 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
12405 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
12406 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
12407 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
12414 #define  DSC_BPP(bpp)				((bpp) << 0)
12416 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
12417 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
12418 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
12419 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
12420 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
12421 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
12429 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
12431 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
12432 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
12433 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
12434 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
12435 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
12436 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
12444 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12446 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
12447 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
12448 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
12449 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
12450 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
12451 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
12459 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
12461 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
12462 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
12463 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
12464 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
12465 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
12466 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
12474 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
12476 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
12477 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
12478 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
12479 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
12480 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
12481 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
12491 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
12493 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
12494 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
12495 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
12496 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
12497 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
12498 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
12506 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
12508 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
12509 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
12510 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
12511 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
12512 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
12513 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
12521 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
12523 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
12524 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
12525 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
12526 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
12527 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
12528 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
12536 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
12538 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
12539 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
12540 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
12541 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
12542 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
12543 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
12553 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
12555 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
12556 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
12557 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
12558 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
12559 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
12560 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
12568 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
12569 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
12570 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
12571 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
12572 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
12573 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
12581 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
12582 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
12583 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
12584 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
12585 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
12586 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
12594 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
12595 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
12596 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
12597 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
12598 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
12599 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
12607 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
12608 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
12609 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
12610 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
12611 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
12612 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
12620 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
12621 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
12622 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
12623 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
12624 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
12625 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
12634 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
12637 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
12638 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
12639 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
12640 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
12641 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
12642 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
12643 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
12644 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
12645 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
12646 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
12647 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
12648 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
12662 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
12663 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
12664 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
12665 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
12666 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
12667 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
12668 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
12669 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
12670 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
12671 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
12672 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
12673 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
12687 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
12692 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
12695 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
12698 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
12701 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
12703 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
12706 #define _TCSS_DDI_STATUS_1			0x161500
12707 #define _TCSS_DDI_STATUS_2			0x161504
12713 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
12716 #define _DSBSL_INSTANCE_BASE		0x70B00
12718 					 (pipe) * 0x1000 + (id) * 0x100)
12719 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12720 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12721 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12723 #define   DSB_STATUS			(1 << 0)
12725 #define TGL_ROOT_DEVICE_ID		0x9A00
12726 #define TGL_ROOT_DEVICE_MASK		0xFF00
12727 #define TGL_ROOT_DEVICE_SKU_MASK	0xF
12728 #define TGL_ROOT_DEVICE_SKU_ULX		0x2
12729 #define TGL_ROOT_DEVICE_SKU_ULT		0x4
12731 #define CLKREQ_POLICY			_MMIO(0x101038)